1//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600InstrInfo
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_R600_R600INSTRINFO_H
16#define LLVM_LIB_TARGET_R600_R600INSTRINFO_H
17
18#include "AMDGPUInstrInfo.h"
19#include "R600Defines.h"
20#include "R600RegisterInfo.h"
21#include <map>
22
23namespace llvm {
24
25  class AMDGPUTargetMachine;
26  class DFAPacketizer;
27  class ScheduleDAG;
28  class MachineFunction;
29  class MachineInstr;
30  class MachineInstrBuilder;
31
32  class R600InstrInfo : public AMDGPUInstrInfo {
33  private:
34  const R600RegisterInfo RI;
35
36  std::vector<std::pair<int, unsigned> >
37  ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
38
39
40  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
41                                        MachineBasicBlock::iterator I,
42                                        unsigned ValueReg, unsigned Address,
43                                        unsigned OffsetReg,
44                                        unsigned AddrChan) const;
45
46  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
47                                        MachineBasicBlock::iterator I,
48                                        unsigned ValueReg, unsigned Address,
49                                        unsigned OffsetReg,
50                                        unsigned AddrChan) const;
51  public:
52  enum BankSwizzle {
53    ALU_VEC_012_SCL_210 = 0,
54    ALU_VEC_021_SCL_122,
55    ALU_VEC_120_SCL_212,
56    ALU_VEC_102_SCL_221,
57    ALU_VEC_201,
58    ALU_VEC_210
59  };
60
61  explicit R600InstrInfo(const AMDGPUSubtarget &st);
62
63  const R600RegisterInfo &getRegisterInfo() const override;
64  void copyPhysReg(MachineBasicBlock &MBB,
65                   MachineBasicBlock::iterator MI, DebugLoc DL,
66                   unsigned DestReg, unsigned SrcReg,
67                   bool KillSrc) const override;
68  bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
69                           MachineBasicBlock::iterator MBBI) const override;
70
71  bool isTrig(const MachineInstr &MI) const;
72  bool isPlaceHolderOpcode(unsigned opcode) const;
73  bool isReductionOp(unsigned opcode) const;
74  bool isCubeOp(unsigned opcode) const;
75
76  /// \returns true if this \p Opcode represents an ALU instruction.
77  bool isALUInstr(unsigned Opcode) const;
78  bool hasInstrModifiers(unsigned Opcode) const;
79  bool isLDSInstr(unsigned Opcode) const;
80  bool isLDSNoRetInstr(unsigned Opcode) const;
81  bool isLDSRetInstr(unsigned Opcode) const;
82
83  /// \returns true if this \p Opcode represents an ALU instruction or an
84  /// instruction that will be lowered in ExpandSpecialInstrs Pass.
85  bool canBeConsideredALU(const MachineInstr *MI) const;
86
87  bool isTransOnly(unsigned Opcode) const;
88  bool isTransOnly(const MachineInstr *MI) const;
89  bool isVectorOnly(unsigned Opcode) const;
90  bool isVectorOnly(const MachineInstr *MI) const;
91  bool isExport(unsigned Opcode) const;
92
93  bool usesVertexCache(unsigned Opcode) const;
94  bool usesVertexCache(const MachineInstr *MI) const;
95  bool usesTextureCache(unsigned Opcode) const;
96  bool usesTextureCache(const MachineInstr *MI) const;
97
98  bool mustBeLastInClause(unsigned Opcode) const;
99  bool usesAddressRegister(MachineInstr *MI) const;
100  bool definesAddressRegister(MachineInstr *MI) const;
101  bool readsLDSSrcReg(const MachineInstr *MI) const;
102
103  /// \returns The operand index for the given source number.  Legal values
104  /// for SrcNum are 0, 1, and 2.
105  int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
106  /// \returns The operand Index for the Sel operand given an index to one
107  /// of the instruction's src operands.
108  int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
109
110  /// \returns a pair for each src of an ALU instructions.
111  /// The first member of a pair is the register id.
112  /// If register is ALU_CONST, second member is SEL.
113  /// If register is ALU_LITERAL, second member is IMM.
114  /// Otherwise, second member value is undefined.
115  SmallVector<std::pair<MachineOperand *, int64_t>, 3>
116      getSrcs(MachineInstr *MI) const;
117
118  unsigned  isLegalUpTo(
119    const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
120    const std::vector<R600InstrInfo::BankSwizzle> &Swz,
121    const std::vector<std::pair<int, unsigned> > &TransSrcs,
122    R600InstrInfo::BankSwizzle TransSwz) const;
123
124  bool FindSwizzleForVectorSlot(
125    const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
126    std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
127    const std::vector<std::pair<int, unsigned> > &TransSrcs,
128    R600InstrInfo::BankSwizzle TransSwz) const;
129
130  /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
131  /// returns true and the first (in lexical order) BankSwizzle affectation
132  /// starting from the one already provided in the Instruction Group MIs that
133  /// fits Read Port limitations in BS if available. Otherwise returns false
134  /// and undefined content in BS.
135  /// isLastAluTrans should be set if the last Alu of MIs will be executed on
136  /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
137  /// apply to the last instruction.
138  /// PV holds GPR to PV registers in the Instruction Group MIs.
139  bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
140                               const DenseMap<unsigned, unsigned> &PV,
141                               std::vector<BankSwizzle> &BS,
142                               bool isLastAluTrans) const;
143
144  /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
145  /// from KCache bank on R700+. This function check if MI set in input meet
146  /// this limitations
147  bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
148  /// Same but using const index set instead of MI set.
149  bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
150
151  /// \brief Vector instructions are instructions that must fill all
152  /// instruction slots within an instruction group.
153  bool isVector(const MachineInstr &MI) const;
154
155  bool isMov(unsigned Opcode) const override;
156
157  DFAPacketizer *
158  CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
159
160  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
161
162  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
163                     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
164
165  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
166
167  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
168
169  bool isPredicated(const MachineInstr *MI) const override;
170
171  bool isPredicable(MachineInstr *MI) const override;
172
173  bool
174   isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
175                             const BranchProbability &Probability) const override;
176
177  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
178                           unsigned ExtraPredCycles,
179                           const BranchProbability &Probability) const override ;
180
181  bool
182   isProfitableToIfCvt(MachineBasicBlock &TMBB,
183                       unsigned NumTCycles, unsigned ExtraTCycles,
184                       MachineBasicBlock &FMBB,
185                       unsigned NumFCycles, unsigned ExtraFCycles,
186                       const BranchProbability &Probability) const override;
187
188  bool DefinesPredicate(MachineInstr *MI,
189                                  std::vector<MachineOperand> &Pred) const override;
190
191  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
192                         const SmallVectorImpl<MachineOperand> &Pred2) const override;
193
194  bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
195                                          MachineBasicBlock &FMBB) const override;
196
197  bool PredicateInstruction(MachineInstr *MI,
198                        const SmallVectorImpl<MachineOperand> &Pred) const override;
199
200  unsigned int getPredicationCost(const MachineInstr *) const override;
201
202  unsigned int getInstrLatency(const InstrItineraryData *ItinData,
203                               const MachineInstr *MI,
204                               unsigned *PredCost = nullptr) const override;
205
206  int getInstrLatency(const InstrItineraryData *ItinData,
207                      SDNode *Node) const override { return 1;}
208
209  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
210
211  /// \brief Reserve the registers that may be accesed using indirect addressing.
212  void reserveIndirectRegisters(BitVector &Reserved,
213                                const MachineFunction &MF) const;
214
215  unsigned calculateIndirectAddress(unsigned RegIndex,
216                                    unsigned Channel) const override;
217
218  const TargetRegisterClass *getIndirectAddrRegClass() const override;
219
220  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
221                          MachineBasicBlock::iterator I,
222                          unsigned ValueReg, unsigned Address,
223                          unsigned OffsetReg) const override;
224
225  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
226                                        MachineBasicBlock::iterator I,
227                                        unsigned ValueReg, unsigned Address,
228                                        unsigned OffsetReg) const override;
229
230  unsigned getMaxAlusPerClause() const;
231
232  ///buildDefaultInstruction - This function returns a MachineInstr with
233  /// all the instruction modifiers initialized to their default values.
234  /// You can use this function to avoid manually specifying each instruction
235  /// modifier operand when building a new instruction.
236  ///
237  /// \returns a MachineInstr with all the instruction modifiers initialized
238  /// to their default values.
239  MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
240                                              MachineBasicBlock::iterator I,
241                                              unsigned Opcode,
242                                              unsigned DstReg,
243                                              unsigned Src0Reg,
244                                              unsigned Src1Reg = 0) const;
245
246  MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
247                                             MachineInstr *MI,
248                                             unsigned Slot,
249                                             unsigned DstReg) const;
250
251  MachineInstr *buildMovImm(MachineBasicBlock &BB,
252                                  MachineBasicBlock::iterator I,
253                                  unsigned DstReg,
254                                  uint64_t Imm) const;
255
256  MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
257                              MachineBasicBlock::iterator I,
258                              unsigned DstReg, unsigned SrcReg) const override;
259
260  /// \brief Get the index of Op in the MachineInstr.
261  ///
262  /// \returns -1 if the Instruction does not contain the specified \p Op.
263  int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
264
265  /// \brief Get the index of \p Op for the given Opcode.
266  ///
267  /// \returns -1 if the Instruction does not contain the specified \p Op.
268  int getOperandIdx(unsigned Opcode, unsigned Op) const;
269
270  /// \brief Helper function for setting instruction flag values.
271  void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
272
273  /// \returns true if this instruction has an operand for storing target flags.
274  bool hasFlagOperand(const MachineInstr &MI) const;
275
276  ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
277  void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
278
279  ///\brief Determine if the specified \p Flag is set on this \p Operand.
280  bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
281
282  /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
283  /// \param Flag The flag being set.
284  ///
285  /// \returns the operand containing the flags for this instruction.
286  MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
287                            unsigned Flag = 0) const;
288
289  /// \brief Clear the specified flag on the instruction.
290  void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
291};
292
293namespace AMDGPU {
294
295int getLDSNoRetOp(uint16_t Opcode);
296
297} //End namespace AMDGPU
298
299} // End llvm namespace
300
301#endif
302