1//===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides Sparc specific target descriptions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcMCTargetDesc.h" 15#include "InstPrinter/SparcInstPrinter.h" 16#include "SparcMCAsmInfo.h" 17#include "SparcTargetStreamer.h" 18#include "llvm/MC/MCCodeGenInfo.h" 19#include "llvm/MC/MCInstrInfo.h" 20#include "llvm/MC/MCRegisterInfo.h" 21#include "llvm/MC/MCSubtargetInfo.h" 22#include "llvm/Support/ErrorHandling.h" 23#include "llvm/Support/TargetRegistry.h" 24 25using namespace llvm; 26 27#define GET_INSTRINFO_MC_DESC 28#include "SparcGenInstrInfo.inc" 29 30#define GET_SUBTARGETINFO_MC_DESC 31#include "SparcGenSubtargetInfo.inc" 32 33#define GET_REGINFO_MC_DESC 34#include "SparcGenRegisterInfo.inc" 35 36static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, 37 StringRef TT) { 38 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 40 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); 41 MAI->addInitialFrameState(Inst); 42 return MAI; 43} 44 45static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, 46 StringRef TT) { 47 MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); 48 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 49 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047); 50 MAI->addInitialFrameState(Inst); 51 return MAI; 52} 53 54static MCInstrInfo *createSparcMCInstrInfo() { 55 MCInstrInfo *X = new MCInstrInfo(); 56 InitSparcMCInstrInfo(X); 57 return X; 58} 59 60static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) { 61 MCRegisterInfo *X = new MCRegisterInfo(); 62 InitSparcMCRegisterInfo(X, SP::O7); 63 return X; 64} 65 66static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, 67 StringRef FS) { 68 MCSubtargetInfo *X = new MCSubtargetInfo(); 69 Triple TheTriple(TT); 70 if (CPU.empty()) 71 CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8"; 72 InitSparcMCSubtargetInfo(X, TT, CPU, FS); 73 return X; 74} 75 76// Code models. Some only make sense for 64-bit code. 77// 78// SunCC Reloc CodeModel Constraints 79// abs32 Static Small text+data+bss linked below 2^32 bytes 80// abs44 Static Medium text+data+bss linked below 2^44 bytes 81// abs64 Static Large text smaller than 2^31 bytes 82// pic13 PIC_ Small GOT < 2^13 bytes 83// pic32 PIC_ Medium GOT < 2^32 bytes 84// 85// All code models require that the text segment is smaller than 2GB. 86 87static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, 88 CodeModel::Model CM, 89 CodeGenOpt::Level OL) { 90 MCCodeGenInfo *X = new MCCodeGenInfo(); 91 92 // The default 32-bit code model is abs32/pic32 and the default 32-bit 93 // code model for JIT is abs32. 94 switch (CM) { 95 default: break; 96 case CodeModel::Default: 97 case CodeModel::JITDefault: CM = CodeModel::Small; break; 98 } 99 100 X->InitMCCodeGenInfo(RM, CM, OL); 101 return X; 102} 103 104static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, 105 CodeModel::Model CM, 106 CodeGenOpt::Level OL) { 107 MCCodeGenInfo *X = new MCCodeGenInfo(); 108 109 // The default 64-bit code model is abs44/pic32 and the default 64-bit 110 // code model for JIT is abs64. 111 switch (CM) { 112 default: break; 113 case CodeModel::Default: 114 CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 115 break; 116 case CodeModel::JITDefault: 117 CM = CodeModel::Large; 118 break; 119 } 120 121 X->InitMCCodeGenInfo(RM, CM, OL); 122 return X; 123} 124 125static MCTargetStreamer * 126createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 127 return new SparcTargetELFStreamer(S); 128} 129 130static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S, 131 formatted_raw_ostream &OS, 132 MCInstPrinter *InstPrint, 133 bool isVerboseAsm) { 134 return new SparcTargetAsmStreamer(S, OS); 135} 136 137static MCInstPrinter *createSparcMCInstPrinter(const Triple &T, 138 unsigned SyntaxVariant, 139 const MCAsmInfo &MAI, 140 const MCInstrInfo &MII, 141 const MCRegisterInfo &MRI) { 142 return new SparcInstPrinter(MAI, MII, MRI); 143} 144 145extern "C" void LLVMInitializeSparcTargetMC() { 146 // Register the MC asm info. 147 RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo); 148 RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo); 149 150 for (Target *T : {&TheSparcTarget, &TheSparcV9Target}) { 151 // Register the MC instruction info. 152 TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo); 153 154 // Register the MC register info. 155 TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo); 156 157 // Register the MC subtarget info. 158 TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo); 159 160 // Register the MC Code Emitter. 161 TargetRegistry::RegisterMCCodeEmitter(*T, createSparcMCCodeEmitter); 162 163 // Register the asm backend. 164 TargetRegistry::RegisterMCAsmBackend(*T, createSparcAsmBackend); 165 166 // Register the object target streamer. 167 TargetRegistry::RegisterObjectTargetStreamer(*T, 168 createObjectTargetStreamer); 169 170 // Register the asm streamer. 171 TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer); 172 173 // Register the MCInstPrinter 174 TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter); 175 } 176 177 // Register the MC codegen info. 178 TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget, 179 createSparcMCCodeGenInfo); 180 TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target, 181 createSparcV9MCCodeGenInfo); 182 183} 184