1//===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Class definitions 12//===----------------------------------------------------------------------===// 13 14class ImmediateAsmOperand<string name> 15 : AsmOperandClass { 16 let Name = name; 17 let RenderMethod = "addImmOperands"; 18} 19class ImmediateTLSAsmOperand<string name> 20 : AsmOperandClass { 21 let Name = name; 22 let RenderMethod = "addImmTLSOperands"; 23} 24 25// Constructs both a DAG pattern and instruction operand for an immediate 26// of type VT. PRED returns true if a node is acceptable and XFORM returns 27// the operand value associated with the node. ASMOP is the name of the 28// associated asm operand, and also forms the basis of the asm print method. 29class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop> 30 : PatLeaf<(vt imm), pred, xform>, Operand<vt> { 31 let PrintMethod = "print"##asmop##"Operand"; 32 let DecoderMethod = "decode"##asmop##"Operand"; 33 let ParserMatchClass = !cast<AsmOperandClass>(asmop); 34} 35 36// Constructs an asm operand for a PC-relative address. SIZE says how 37// many bits there are. 38class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> { 39 let PredicateMethod = "isImm"; 40 let ParserMethod = "parsePCRel"##size; 41} 42class PCRelTLSAsmOperand<string size> 43 : ImmediateTLSAsmOperand<"PCRelTLS"##size> { 44 let PredicateMethod = "isImmTLS"; 45 let ParserMethod = "parsePCRelTLS"##size; 46} 47 48// Constructs an operand for a PC-relative address with address type VT. 49// ASMOP is the associated asm operand. 50class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> { 51 let PrintMethod = "printPCRelOperand"; 52 let ParserMatchClass = asmop; 53} 54class PCRelTLSOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> { 55 let PrintMethod = "printPCRelTLSOperand"; 56 let ParserMatchClass = asmop; 57} 58 59// Constructs both a DAG pattern and instruction operand for a PC-relative 60// address with address size VT. SELF is the name of the operand and 61// ASMOP is the associated asm operand. 62class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop> 63 : ComplexPattern<vt, 1, "selectPCRelAddress", 64 [z_pcrel_wrapper, z_pcrel_offset]>, 65 PCRelOperand<vt, asmop> { 66 let MIOperandInfo = (ops !cast<Operand>(self)); 67} 68 69// Constructs an AsmOperandClass for addressing mode FORMAT, treating the 70// registers as having BITSIZE bits and displacements as having DISPSIZE bits. 71// LENGTH is "LenN" for addresses with an N-bit length field, otherwise it 72// is "". 73class AddressAsmOperand<string format, string bitsize, string dispsize, 74 string length = ""> 75 : AsmOperandClass { 76 let Name = format##bitsize##"Disp"##dispsize##length; 77 let ParserMethod = "parse"##format##bitsize; 78 let RenderMethod = "add"##format##"Operands"; 79} 80 81// Constructs both a DAG pattern and instruction operand for an addressing mode. 82// FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated 83// AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands 84// (base register, displacement, etc.). SELTYPE is the type of the memory 85// operand for selection purposes; sometimes we want different selection 86// choices for the same underlying addressing mode. SUFFIX is similarly 87// a suffix appended to the displacement for selection purposes; 88// e.g. we want to reject small 20-bit displacements if a 12-bit form 89// also exists, but we want to accept them otherwise. 90class AddressingMode<string seltype, string bitsize, string dispsize, 91 string suffix, string length, int numops, string format, 92 dag operands> 93 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops, 94 "select"##seltype##dispsize##suffix##length, 95 [add, sub, or, frameindex, z_adjdynalloc]>, 96 Operand<!cast<ValueType>("i"##bitsize)> { 97 let PrintMethod = "print"##format##"Operand"; 98 let EncoderMethod = "get"##format##dispsize##length##"Encoding"; 99 let DecoderMethod = 100 "decode"##format##bitsize##"Disp"##dispsize##length##"Operand"; 101 let MIOperandInfo = operands; 102 let ParserMatchClass = 103 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length); 104} 105 106// An addressing mode with a base and displacement but no index. 107class BDMode<string type, string bitsize, string dispsize, string suffix> 108 : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr", 109 (ops !cast<RegisterOperand>("ADDR"##bitsize), 110 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>; 111 112// An addressing mode with a base, displacement and index. 113class BDXMode<string type, string bitsize, string dispsize, string suffix> 114 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr", 115 (ops !cast<RegisterOperand>("ADDR"##bitsize), 116 !cast<Immediate>("disp"##dispsize##"imm"##bitsize), 117 !cast<RegisterOperand>("ADDR"##bitsize))>; 118 119// A BDMode paired with an immediate length operand of LENSIZE bits. 120class BDLMode<string type, string bitsize, string dispsize, string suffix, 121 string lensize> 122 : AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3, 123 "BDLAddr", 124 (ops !cast<RegisterOperand>("ADDR"##bitsize), 125 !cast<Immediate>("disp"##dispsize##"imm"##bitsize), 126 !cast<Immediate>("imm"##bitsize))>; 127 128//===----------------------------------------------------------------------===// 129// Extracting immediate operands from nodes 130// These all create MVT::i64 nodes to ensure the value is not sign-extended 131// when converted from an SDNode to a MachineOperand later on. 132//===----------------------------------------------------------------------===// 133 134// Bits 0-15 (counting from the lsb). 135def LL16 : SDNodeXForm<imm, [{ 136 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL; 137 return CurDAG->getTargetConstant(Value, MVT::i64); 138}]>; 139 140// Bits 16-31 (counting from the lsb). 141def LH16 : SDNodeXForm<imm, [{ 142 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16; 143 return CurDAG->getTargetConstant(Value, MVT::i64); 144}]>; 145 146// Bits 32-47 (counting from the lsb). 147def HL16 : SDNodeXForm<imm, [{ 148 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32; 149 return CurDAG->getTargetConstant(Value, MVT::i64); 150}]>; 151 152// Bits 48-63 (counting from the lsb). 153def HH16 : SDNodeXForm<imm, [{ 154 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48; 155 return CurDAG->getTargetConstant(Value, MVT::i64); 156}]>; 157 158// Low 32 bits. 159def LF32 : SDNodeXForm<imm, [{ 160 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL; 161 return CurDAG->getTargetConstant(Value, MVT::i64); 162}]>; 163 164// High 32 bits. 165def HF32 : SDNodeXForm<imm, [{ 166 uint64_t Value = N->getZExtValue() >> 32; 167 return CurDAG->getTargetConstant(Value, MVT::i64); 168}]>; 169 170// Truncate an immediate to a 8-bit signed quantity. 171def SIMM8 : SDNodeXForm<imm, [{ 172 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64); 173}]>; 174 175// Truncate an immediate to a 8-bit unsigned quantity. 176def UIMM8 : SDNodeXForm<imm, [{ 177 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64); 178}]>; 179 180// Truncate an immediate to a 16-bit signed quantity. 181def SIMM16 : SDNodeXForm<imm, [{ 182 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64); 183}]>; 184 185// Truncate an immediate to a 16-bit unsigned quantity. 186def UIMM16 : SDNodeXForm<imm, [{ 187 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64); 188}]>; 189 190// Truncate an immediate to a 32-bit signed quantity. 191def SIMM32 : SDNodeXForm<imm, [{ 192 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64); 193}]>; 194 195// Truncate an immediate to a 32-bit unsigned quantity. 196def UIMM32 : SDNodeXForm<imm, [{ 197 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64); 198}]>; 199 200// Negate and then truncate an immediate to a 32-bit unsigned quantity. 201def NEGIMM32 : SDNodeXForm<imm, [{ 202 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64); 203}]>; 204 205//===----------------------------------------------------------------------===// 206// Immediate asm operands. 207//===----------------------------------------------------------------------===// 208 209def U4Imm : ImmediateAsmOperand<"U4Imm">; 210def U6Imm : ImmediateAsmOperand<"U6Imm">; 211def S8Imm : ImmediateAsmOperand<"S8Imm">; 212def U8Imm : ImmediateAsmOperand<"U8Imm">; 213def S16Imm : ImmediateAsmOperand<"S16Imm">; 214def U16Imm : ImmediateAsmOperand<"U16Imm">; 215def S32Imm : ImmediateAsmOperand<"S32Imm">; 216def U32Imm : ImmediateAsmOperand<"U32Imm">; 217 218//===----------------------------------------------------------------------===// 219// i32 immediates 220//===----------------------------------------------------------------------===// 221 222// Immediates for the lower and upper 16 bits of an i32, with the other 223// bits of the i32 being zero. 224def imm32ll16 : Immediate<i32, [{ 225 return SystemZ::isImmLL(N->getZExtValue()); 226}], LL16, "U16Imm">; 227 228def imm32lh16 : Immediate<i32, [{ 229 return SystemZ::isImmLH(N->getZExtValue()); 230}], LH16, "U16Imm">; 231 232// Immediates for the lower and upper 16 bits of an i32, with the other 233// bits of the i32 being one. 234def imm32ll16c : Immediate<i32, [{ 235 return SystemZ::isImmLL(uint32_t(~N->getZExtValue())); 236}], LL16, "U16Imm">; 237 238def imm32lh16c : Immediate<i32, [{ 239 return SystemZ::isImmLH(uint32_t(~N->getZExtValue())); 240}], LH16, "U16Imm">; 241 242// Short immediates 243def imm32zx4 : Immediate<i32, [{ 244 return isUInt<4>(N->getZExtValue()); 245}], NOOP_SDNodeXForm, "U4Imm">; 246 247def imm32zx6 : Immediate<i32, [{ 248 return isUInt<6>(N->getZExtValue()); 249}], NOOP_SDNodeXForm, "U6Imm">; 250 251def imm32sx8 : Immediate<i32, [{ 252 return isInt<8>(N->getSExtValue()); 253}], SIMM8, "S8Imm">; 254 255def imm32zx8 : Immediate<i32, [{ 256 return isUInt<8>(N->getZExtValue()); 257}], UIMM8, "U8Imm">; 258 259def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">; 260 261def imm32sx16 : Immediate<i32, [{ 262 return isInt<16>(N->getSExtValue()); 263}], SIMM16, "S16Imm">; 264 265def imm32zx16 : Immediate<i32, [{ 266 return isUInt<16>(N->getZExtValue()); 267}], UIMM16, "U16Imm">; 268 269def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">; 270 271// Full 32-bit immediates. we need both signed and unsigned versions 272// because the assembler is picky. E.g. AFI requires signed operands 273// while NILF requires unsigned ones. 274def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">; 275def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">; 276 277def imm32 : ImmLeaf<i32, [{}]>; 278 279//===----------------------------------------------------------------------===// 280// 64-bit immediates 281//===----------------------------------------------------------------------===// 282 283// Immediates for 16-bit chunks of an i64, with the other bits of the 284// i32 being zero. 285def imm64ll16 : Immediate<i64, [{ 286 return SystemZ::isImmLL(N->getZExtValue()); 287}], LL16, "U16Imm">; 288 289def imm64lh16 : Immediate<i64, [{ 290 return SystemZ::isImmLH(N->getZExtValue()); 291}], LH16, "U16Imm">; 292 293def imm64hl16 : Immediate<i64, [{ 294 return SystemZ::isImmHL(N->getZExtValue()); 295}], HL16, "U16Imm">; 296 297def imm64hh16 : Immediate<i64, [{ 298 return SystemZ::isImmHH(N->getZExtValue()); 299}], HH16, "U16Imm">; 300 301// Immediates for 16-bit chunks of an i64, with the other bits of the 302// i32 being one. 303def imm64ll16c : Immediate<i64, [{ 304 return SystemZ::isImmLL(uint64_t(~N->getZExtValue())); 305}], LL16, "U16Imm">; 306 307def imm64lh16c : Immediate<i64, [{ 308 return SystemZ::isImmLH(uint64_t(~N->getZExtValue())); 309}], LH16, "U16Imm">; 310 311def imm64hl16c : Immediate<i64, [{ 312 return SystemZ::isImmHL(uint64_t(~N->getZExtValue())); 313}], HL16, "U16Imm">; 314 315def imm64hh16c : Immediate<i64, [{ 316 return SystemZ::isImmHH(uint64_t(~N->getZExtValue())); 317}], HH16, "U16Imm">; 318 319// Immediates for the lower and upper 32 bits of an i64, with the other 320// bits of the i32 being zero. 321def imm64lf32 : Immediate<i64, [{ 322 return SystemZ::isImmLF(N->getZExtValue()); 323}], LF32, "U32Imm">; 324 325def imm64hf32 : Immediate<i64, [{ 326 return SystemZ::isImmHF(N->getZExtValue()); 327}], HF32, "U32Imm">; 328 329// Immediates for the lower and upper 32 bits of an i64, with the other 330// bits of the i32 being one. 331def imm64lf32c : Immediate<i64, [{ 332 return SystemZ::isImmLF(uint64_t(~N->getZExtValue())); 333}], LF32, "U32Imm">; 334 335def imm64hf32c : Immediate<i64, [{ 336 return SystemZ::isImmHF(uint64_t(~N->getZExtValue())); 337}], HF32, "U32Imm">; 338 339// Short immediates. 340def imm64sx8 : Immediate<i64, [{ 341 return isInt<8>(N->getSExtValue()); 342}], SIMM8, "S8Imm">; 343 344def imm64zx8 : Immediate<i64, [{ 345 return isUInt<8>(N->getSExtValue()); 346}], UIMM8, "U8Imm">; 347 348def imm64sx16 : Immediate<i64, [{ 349 return isInt<16>(N->getSExtValue()); 350}], SIMM16, "S16Imm">; 351 352def imm64zx16 : Immediate<i64, [{ 353 return isUInt<16>(N->getZExtValue()); 354}], UIMM16, "U16Imm">; 355 356def imm64sx32 : Immediate<i64, [{ 357 return isInt<32>(N->getSExtValue()); 358}], SIMM32, "S32Imm">; 359 360def imm64zx32 : Immediate<i64, [{ 361 return isUInt<32>(N->getZExtValue()); 362}], UIMM32, "U32Imm">; 363 364def imm64zx32n : Immediate<i64, [{ 365 return isUInt<32>(-N->getSExtValue()); 366}], NEGIMM32, "U32Imm">; 367 368def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>; 369 370//===----------------------------------------------------------------------===// 371// Floating-point immediates 372//===----------------------------------------------------------------------===// 373 374// Floating-point zero. 375def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 376 377// Floating point negative zero. 378def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; 379 380//===----------------------------------------------------------------------===// 381// Symbolic address operands 382//===----------------------------------------------------------------------===// 383 384// PC-relative asm operands. 385def PCRel16 : PCRelAsmOperand<"16">; 386def PCRel32 : PCRelAsmOperand<"32">; 387def PCRelTLS16 : PCRelTLSAsmOperand<"16">; 388def PCRelTLS32 : PCRelTLSAsmOperand<"32">; 389 390// PC-relative offsets of a basic block. The offset is sign-extended 391// and multiplied by 2. 392def brtarget16 : PCRelOperand<OtherVT, PCRel16> { 393 let EncoderMethod = "getPC16DBLEncoding"; 394 let DecoderMethod = "decodePC16DBLOperand"; 395} 396def brtarget32 : PCRelOperand<OtherVT, PCRel32> { 397 let EncoderMethod = "getPC32DBLEncoding"; 398 let DecoderMethod = "decodePC32DBLOperand"; 399} 400 401// Variants of brtarget16/32 with an optional additional TLS symbol. 402// These are used to annotate calls to __tls_get_offset. 403def tlssym : Operand<i64> { } 404def brtarget16tls : PCRelTLSOperand<OtherVT, PCRelTLS16> { 405 let MIOperandInfo = (ops brtarget16:$func, tlssym:$sym); 406 let EncoderMethod = "getPC16DBLTLSEncoding"; 407 let DecoderMethod = "decodePC16DBLOperand"; 408} 409def brtarget32tls : PCRelTLSOperand<OtherVT, PCRelTLS32> { 410 let MIOperandInfo = (ops brtarget32:$func, tlssym:$sym); 411 let EncoderMethod = "getPC32DBLTLSEncoding"; 412 let DecoderMethod = "decodePC32DBLOperand"; 413} 414 415// A PC-relative offset of a global value. The offset is sign-extended 416// and multiplied by 2. 417def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> { 418 let EncoderMethod = "getPC32DBLEncoding"; 419 let DecoderMethod = "decodePC32DBLOperand"; 420} 421 422//===----------------------------------------------------------------------===// 423// Addressing modes 424//===----------------------------------------------------------------------===// 425 426// 12-bit displacement operands. 427def disp12imm32 : Operand<i32>; 428def disp12imm64 : Operand<i64>; 429 430// 20-bit displacement operands. 431def disp20imm32 : Operand<i32>; 432def disp20imm64 : Operand<i64>; 433 434def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">; 435def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">; 436def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">; 437def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">; 438def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">; 439def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">; 440def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">; 441 442// DAG patterns and operands for addressing modes. Each mode has 443// the form <type><range><group>[<len>] where: 444// 445// <type> is one of: 446// shift : base + displacement (32-bit) 447// bdaddr : base + displacement 448// mviaddr : like bdaddr, but reject cases with a natural index 449// bdxaddr : base + displacement + index 450// laaddr : like bdxaddr, but used for Load Address operations 451// dynalloc : base + displacement + index + ADJDYNALLOC 452// bdladdr : base + displacement with a length field 453// 454// <range> is one of: 455// 12 : the displacement is an unsigned 12-bit value 456// 20 : the displacement is a signed 20-bit value 457// 458// <group> is one of: 459// pair : used when there is an equivalent instruction with the opposite 460// range value (12 or 20) 461// only : used when there is no equivalent instruction with the opposite 462// range value 463// 464// <len> is one of: 465// 466// <empty> : there is no length field 467// len8 : the length field is 8 bits, with a range of [1, 0x100]. 468def shift12only : BDMode <"BDAddr", "32", "12", "Only">; 469def shift20only : BDMode <"BDAddr", "32", "20", "Only">; 470def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">; 471def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">; 472def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">; 473def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">; 474def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">; 475def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">; 476def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">; 477def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">; 478def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">; 479def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">; 480def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">; 481def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">; 482def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">; 483def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">; 484def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">; 485 486//===----------------------------------------------------------------------===// 487// Miscellaneous 488//===----------------------------------------------------------------------===// 489 490// Access registers. At present we just use them for accessing the thread 491// pointer, so we don't expose them as register to LLVM. 492def AccessReg : AsmOperandClass { 493 let Name = "AccessReg"; 494 let ParserMethod = "parseAccessReg"; 495} 496def access_reg : Immediate<i32, [{ return N->getZExtValue() < 16; }], 497 NOOP_SDNodeXForm, "AccessReg"> { 498 let ParserMatchClass = AccessReg; 499} 500 501// A 4-bit condition-code mask. 502def cond4 : PatLeaf<(i32 imm), [{ return (N->getZExtValue() < 16); }]>, 503 Operand<i32> { 504 let PrintMethod = "printCond4Operand"; 505} 506