1//===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file is part of the X86 Disassembler. 11// It contains common definitions used by both the disassembler and the table 12// generator. 13// Documentation for the disassembler can be found in X86Disassembler.h. 14// 15//===----------------------------------------------------------------------===// 16 17#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODERCOMMON_H 18#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLERDECODERCOMMON_H 19 20#include "llvm/Support/DataTypes.h" 21 22namespace llvm { 23namespace X86Disassembler { 24 25#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers 26#define CONTEXTS_SYM x86DisassemblerContexts 27#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes 28#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes 29#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes 30#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes 31#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes 32#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes 33#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes 34 35#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers" 36#define CONTEXTS_STR "x86DisassemblerContexts" 37#define ONEBYTE_STR "x86DisassemblerOneByteOpcodes" 38#define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes" 39#define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes" 40#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes" 41#define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes" 42#define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes" 43#define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes" 44 45// Attributes of an instruction that must be known before the opcode can be 46// processed correctly. Most of these indicate the presence of particular 47// prefixes, but ATTR_64BIT is simply an attribute of the decoding context. 48#define ATTRIBUTE_BITS \ 49 ENUM_ENTRY(ATTR_NONE, 0x00) \ 50 ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \ 51 ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \ 52 ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \ 53 ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \ 54 ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \ 55 ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \ 56 ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \ 57 ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \ 58 ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \ 59 ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \ 60 ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \ 61 ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \ 62 ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \ 63 ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13)) 64 65#define ENUM_ENTRY(n, v) n = v, 66enum attributeBits { 67 ATTRIBUTE_BITS 68 ATTR_max 69}; 70#undef ENUM_ENTRY 71 72// Combinations of the above attributes that are relevant to instruction 73// decode. Although other combinations are possible, they can be reduced to 74// these without affecting the ultimately decoded instruction. 75 76// Class name Rank Rationale for rank assignment 77#define INSTRUCTION_CONTEXTS \ 78 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ 79 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ 80 "64-bit mode but no more") \ 81 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 82 "operands change width") \ 83 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \ 84 "operands change width") \ 85 ENUM_ENTRY(IC_OPSIZE_ADSIZE, 4, "requires ADSIZE and OPSIZE prefixes") \ 86 ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \ 87 "but not the operands") \ 88 ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \ 89 "but not the operands") \ 90 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 91 "operands change width") \ 92 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 93 "operands change width") \ 94 ENUM_ENTRY(IC_64BIT_REXW, 5, "requires a REX.W prefix, so operands "\ 95 "change width; overrides IC_OPSIZE") \ 96 ENUM_ENTRY(IC_64BIT_REXW_ADSIZE, 6, "requires a REX.W prefix and 0x67 " \ 97 "prefix") \ 98 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ 99 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \ 100 ENUM_ENTRY(IC_64BIT_OPSIZE_ADSIZE, 4, "Just as meaningful as IC_OPSIZE/" \ 101 "IC_ADSIZE") \ 102 ENUM_ENTRY(IC_64BIT_XD, 6, "XD instructions are SSE; REX.W is " \ 103 "secondary") \ 104 ENUM_ENTRY(IC_64BIT_XS, 6, "Just as meaningful as IC_64BIT_XD") \ 105 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \ 106 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \ 107 ENUM_ENTRY(IC_64BIT_REXW_XS, 7, "OPSIZE could mean a different " \ 108 "opcode") \ 109 ENUM_ENTRY(IC_64BIT_REXW_XD, 7, "Just as meaningful as " \ 110 "IC_64BIT_REXW_XS") \ 111 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 8, "The Dynamic Duo! Prefer over all " \ 112 "else because this changes most " \ 113 "operands' meaning") \ 114 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ 115 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ 116 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ 117 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ 118 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ 119 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ 120 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ 121 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ 122 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ 123 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\ 124 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\ 125 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \ 126 ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \ 127 ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \ 128 ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \ 129 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \ 130 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \ 131 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \ 132 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \ 133 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \ 134 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \ 135 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \ 136 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \ 137 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \ 138 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \ 139 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\ 140 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\ 141 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \ 142 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \ 143 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \ 144 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \ 145 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \ 146 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \ 147 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\ 148 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\ 149 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \ 150 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \ 151 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \ 152 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \ 153 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \ 154 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \ 155 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \ 156 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \ 157 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \ 158 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \ 159 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \ 160 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \ 161 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \ 162 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \ 163 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\ 164 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\ 165 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \ 166 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \ 167 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \ 168 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \ 169 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \ 170 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \ 171 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\ 172 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\ 173 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \ 174 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \ 175 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \ 176 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \ 177 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \ 178 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \ 179 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \ 180 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \ 181 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \ 182 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \ 183 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \ 184 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \ 185 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \ 186 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \ 187 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\ 188 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\ 189 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \ 190 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \ 191 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \ 192 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \ 193 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \ 194 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \ 195 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\ 196 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\ 197 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \ 198 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \ 199 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \ 200 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \ 201 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \ 202 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \ 203 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \ 204 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \ 205 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \ 206 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \ 207 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \ 208 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \ 209 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \ 210 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \ 211 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\ 212 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\ 213 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \ 214 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \ 215 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \ 216 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \ 217 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \ 218 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \ 219 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\ 220 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\ 221 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \ 222 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \ 223 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \ 224 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \ 225 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \ 226 ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \ 227 ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \ 228 ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \ 229 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \ 230 ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \ 231 ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \ 232 ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \ 233 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \ 234 ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \ 235 ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\ 236 ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\ 237 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \ 238 ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \ 239 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \ 240 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \ 241 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \ 242 ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \ 243 ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\ 244 ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\ 245 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \ 246 ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \ 247 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \ 248 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \ 249 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \ 250 ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \ 251 ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \ 252 ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \ 253 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \ 254 ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \ 255 ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \ 256 ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \ 257 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \ 258 ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \ 259 ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\ 260 ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\ 261 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \ 262 ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \ 263 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \ 264 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \ 265 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \ 266 ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \ 267 ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\ 268 ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\ 269 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \ 270 ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \ 271 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \ 272 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \ 273 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize") 274 275#define ENUM_ENTRY(n, r, d) n, 276enum InstructionContext { 277 INSTRUCTION_CONTEXTS 278 IC_max 279}; 280#undef ENUM_ENTRY 281 282// Opcode types, which determine which decode table to use, both in the Intel 283// manual and also for the decoder. 284enum OpcodeType { 285 ONEBYTE = 0, 286 TWOBYTE = 1, 287 THREEBYTE_38 = 2, 288 THREEBYTE_3A = 3, 289 XOP8_MAP = 4, 290 XOP9_MAP = 5, 291 XOPA_MAP = 6 292}; 293 294// The following structs are used for the hierarchical decode table. After 295// determining the instruction's class (i.e., which IC_* constant applies to 296// it), the decoder reads the opcode. Some instructions require specific 297// values of the ModR/M byte, so the ModR/M byte indexes into the final table. 298// 299// If a ModR/M byte is not required, "required" is left unset, and the values 300// for each instructionID are identical. 301typedef uint16_t InstrUID; 302 303// ModRMDecisionType - describes the type of ModR/M decision, allowing the 304// consumer to determine the number of entries in it. 305// 306// MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded 307// instruction is the same. 308// MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode 309// corresponds to one instruction; otherwise, it corresponds to 310// a different instruction. 311// MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte 312// divided by 8 is used to select instruction; otherwise, each 313// value of the ModR/M byte could correspond to a different 314// instruction. 315// MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This 316// corresponds to instructions that use reg field as opcode 317// MODRM_FULL - Potentially, each value of the ModR/M byte could correspond 318// to a different instruction. 319#define MODRMTYPES \ 320 ENUM_ENTRY(MODRM_ONEENTRY) \ 321 ENUM_ENTRY(MODRM_SPLITRM) \ 322 ENUM_ENTRY(MODRM_SPLITMISC) \ 323 ENUM_ENTRY(MODRM_SPLITREG) \ 324 ENUM_ENTRY(MODRM_FULL) 325 326#define ENUM_ENTRY(n) n, 327enum ModRMDecisionType { 328 MODRMTYPES 329 MODRM_max 330}; 331#undef ENUM_ENTRY 332 333#define CASE_ENCODING_RM \ 334 case ENCODING_RM: \ 335 case ENCODING_RM_CD2: \ 336 case ENCODING_RM_CD4: \ 337 case ENCODING_RM_CD8: \ 338 case ENCODING_RM_CD16: \ 339 case ENCODING_RM_CD32: \ 340 case ENCODING_RM_CD64 341 342// Physical encodings of instruction operands. 343#define ENCODINGS \ 344 ENUM_ENTRY(ENCODING_NONE, "") \ 345 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ 346 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ 347 ENUM_ENTRY(ENCODING_RM_CD2, "R/M operand with CDisp scaling of 2") \ 348 ENUM_ENTRY(ENCODING_RM_CD4, "R/M operand with CDisp scaling of 4") \ 349 ENUM_ENTRY(ENCODING_RM_CD8, "R/M operand with CDisp scaling of 8") \ 350 ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \ 351 ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \ 352 ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ 353 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ 354 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ 355 ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \ 356 ENUM_ENTRY(ENCODING_CW, "2-byte") \ 357 ENUM_ENTRY(ENCODING_CD, "4-byte") \ 358 ENUM_ENTRY(ENCODING_CP, "6-byte") \ 359 ENUM_ENTRY(ENCODING_CO, "8-byte") \ 360 ENUM_ENTRY(ENCODING_CT, "10-byte") \ 361 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ 362 ENUM_ENTRY(ENCODING_IW, "2-byte") \ 363 ENUM_ENTRY(ENCODING_ID, "4-byte") \ 364 ENUM_ENTRY(ENCODING_IO, "8-byte") \ 365 ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \ 366 "the opcode byte") \ 367 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ 368 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ 369 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ 370 ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \ 371 "byte.") \ 372 \ 373 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ 374 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ 375 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \ 376 "opcode byte") \ 377 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \ 378 "in type") \ 379 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \ 380 ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes") 381 382#define ENUM_ENTRY(n, d) n, 383enum OperandEncoding { 384 ENCODINGS 385 ENCODING_max 386}; 387#undef ENUM_ENTRY 388 389// Semantic interpretations of instruction operands. 390#define TYPES \ 391 ENUM_ENTRY(TYPE_NONE, "") \ 392 ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \ 393 ENUM_ENTRY(TYPE_REL16, "2-byte") \ 394 ENUM_ENTRY(TYPE_REL32, "4-byte") \ 395 ENUM_ENTRY(TYPE_REL64, "8-byte") \ 396 ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \ 397 ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \ 398 ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \ 399 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ 400 ENUM_ENTRY(TYPE_R16, "2-byte") \ 401 ENUM_ENTRY(TYPE_R32, "4-byte") \ 402 ENUM_ENTRY(TYPE_R64, "8-byte") \ 403 ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \ 404 ENUM_ENTRY(TYPE_IMM16, "2-byte") \ 405 ENUM_ENTRY(TYPE_IMM32, "4-byte") \ 406 ENUM_ENTRY(TYPE_IMM64, "8-byte") \ 407 ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ 408 ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \ 409 ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \ 410 ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ 411 ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \ 412 ENUM_ENTRY(TYPE_RM16, "2-byte") \ 413 ENUM_ENTRY(TYPE_RM32, "4-byte") \ 414 ENUM_ENTRY(TYPE_RM64, "8-byte") \ 415 ENUM_ENTRY(TYPE_M, "Memory operand") \ 416 ENUM_ENTRY(TYPE_M8, "1-byte") \ 417 ENUM_ENTRY(TYPE_M16, "2-byte") \ 418 ENUM_ENTRY(TYPE_M32, "4-byte") \ 419 ENUM_ENTRY(TYPE_M64, "8-byte") \ 420 ENUM_ENTRY(TYPE_LEA, "Effective address") \ 421 ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \ 422 ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \ 423 ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \ 424 ENUM_ENTRY(TYPE_M1632, "2+4-byte") \ 425 ENUM_ENTRY(TYPE_M1664, "2+8-byte") \ 426 ENUM_ENTRY(TYPE_SRCIDX8, "1-byte memory at source index") \ 427 ENUM_ENTRY(TYPE_SRCIDX16, "2-byte memory at source index") \ 428 ENUM_ENTRY(TYPE_SRCIDX32, "4-byte memory at source index") \ 429 ENUM_ENTRY(TYPE_SRCIDX64, "8-byte memory at source index") \ 430 ENUM_ENTRY(TYPE_DSTIDX8, "1-byte memory at destination index") \ 431 ENUM_ENTRY(TYPE_DSTIDX16, "2-byte memory at destination index") \ 432 ENUM_ENTRY(TYPE_DSTIDX32, "4-byte memory at destination index") \ 433 ENUM_ENTRY(TYPE_DSTIDX64, "8-byte memory at destination index") \ 434 ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \ 435 "base)") \ 436 ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \ 437 ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \ 438 ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \ 439 ENUM_ENTRY(TYPE_SREG, "Byte with single bit set: 0 = ES, 1 = CS, " \ 440 "2 = SS, 3 = DS, 4 = FS, 5 = GS") \ 441 ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \ 442 ENUM_ENTRY(TYPE_M64FP, "64-bit") \ 443 ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \ 444 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ 445 ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ 446 ENUM_ENTRY(TYPE_XMM, "XMM register operand") \ 447 ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \ 448 ENUM_ENTRY(TYPE_XMM64, "8-byte") \ 449 ENUM_ENTRY(TYPE_XMM128, "16-byte") \ 450 ENUM_ENTRY(TYPE_XMM256, "32-byte") \ 451 ENUM_ENTRY(TYPE_XMM512, "64-byte") \ 452 ENUM_ENTRY(TYPE_VK1, "1-bit") \ 453 ENUM_ENTRY(TYPE_VK2, "2-bit") \ 454 ENUM_ENTRY(TYPE_VK4, "4-bit") \ 455 ENUM_ENTRY(TYPE_VK8, "8-bit") \ 456 ENUM_ENTRY(TYPE_VK16, "16-bit") \ 457 ENUM_ENTRY(TYPE_VK32, "32-bit") \ 458 ENUM_ENTRY(TYPE_VK64, "64-bit") \ 459 ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \ 460 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ 461 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ 462 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ 463 \ 464 ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \ 465 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ 466 ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \ 467 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ 468 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ 469 ENUM_ENTRY(TYPE_DUP1, "operand 1") \ 470 ENUM_ENTRY(TYPE_DUP2, "operand 2") \ 471 ENUM_ENTRY(TYPE_DUP3, "operand 3") \ 472 ENUM_ENTRY(TYPE_DUP4, "operand 4") \ 473 ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state") 474 475#define ENUM_ENTRY(n, d) n, 476enum OperandType { 477 TYPES 478 TYPE_max 479}; 480#undef ENUM_ENTRY 481 482/// \brief The specification for how to extract and interpret one operand. 483struct OperandSpecifier { 484 uint8_t encoding; 485 uint8_t type; 486}; 487 488static const unsigned X86_MAX_OPERANDS = 6; 489 490/// Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode 491/// are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, 492/// respectively. 493enum DisassemblerMode { 494 MODE_16BIT, 495 MODE_32BIT, 496 MODE_64BIT 497}; 498 499} // namespace X86Disassembler 500} // namespace llvm 501 502#endif 503