1// Copyright 2014, ARM Limited
2// All rights reserved.
3//
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5// modification, are permitted provided that the following conditions are met:
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26
27#ifndef VIXL_CPU_A64_H
28#define VIXL_CPU_A64_H
29
30#include "vixl/globals.h"
31#include "vixl/a64/instructions-a64.h"
32
33namespace vixl {
34
35class CPU {
36 public:
37  // Initialise CPU support.
38  static void SetUp();
39
40  // Ensures the data at a given address and with a given size is the same for
41  // the I and D caches. I and D caches are not automatically coherent on ARM
42  // so this operation is required before any dynamically generated code can
43  // safely run.
44  static void EnsureIAndDCacheCoherency(void *address, size_t length);
45
46  // Handle tagged pointers.
47  template <typename T>
48  static T SetPointerTag(T pointer, uint64_t tag) {
49    VIXL_ASSERT(is_uintn(kAddressTagWidth, tag));
50
51    // Use C-style casts to get static_cast behaviour for integral types (T),
52    // and reinterpret_cast behaviour for other types.
53
54    uint64_t raw = (uint64_t)pointer;
55    VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw));
56
57    raw = (raw & ~kAddressTagMask) | (tag << kAddressTagOffset);
58    return (T)raw;
59  }
60
61  template <typename T>
62  static uint64_t GetPointerTag(T pointer) {
63    // Use C-style casts to get static_cast behaviour for integral types (T),
64    // and reinterpret_cast behaviour for other types.
65
66    uint64_t raw = (uint64_t)pointer;
67    VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw));
68
69    return (raw & kAddressTagMask) >> kAddressTagOffset;
70  }
71
72 private:
73  // Return the content of the cache type register.
74  static uint32_t GetCacheType();
75
76  // I and D cache line size in bytes.
77  static unsigned icache_line_size_;
78  static unsigned dcache_line_size_;
79};
80
81}  // namespace vixl
82
83#endif  // VIXL_CPU_A64_H
84