History log of /art/compiler/optimizing/codegen_test.cc
Revision Date Author Comments
badd826664896d4a9628a5a89b78016894aa414b 02-Feb-2016 David Brazdil <dbrazdil@google.com> ART: Run SsaBuilder from HGraphBuilder

First step towards merging the two passes, which will later result in
HGraphBuilder directly producing SSA form. This CL mostly just updates
tests broken by not being able to inspect the pre-SSA form.

Using HLocals outside the HGraphBuilder is now deprecated.

Bug: 27150508
Change-Id: I00fb6050580f409dcc5aa5b5aa3a536d6e8d759e
6e332529c33be4d7dae5dad3609a839f4c0d3bfc 02-Feb-2016 David Brazdil <dbrazdil@google.com> ART: Remove HTemporary

Change-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03
b11b0725d02aafd6e3ea4eb514b215149c893bf0 28-Jan-2016 David Brazdil <dbrazdil@google.com> ART: Fix gtest after liveness CL

Change-Id: I2d029044cebe6e1ee7d7efb2e20541060f88c07c
58282f4510961317b8d5a364a6f740a78926716f 14-Jan-2016 David Brazdil <dbrazdil@google.com> ART: Remove Baseline compiler

We don't need Baseline any more and it hasn't been maintained for
a while anyway. Let's remove it.

Change-Id: I442ed26855527be2df3c79935403a25b1ee55df6
751beff19b36f777d9e3a966d754fd9cfad5d534 28-Aug-2015 Phil Wang <phil.wang@linaro.org> Revert "Revert "Introduce support for hardware simulators, starting with ARM64""

This reverts commit 4cd27d64b0bbdde61fa3f6674ceb24221853ac2c.

This depends on VIXL 1.11.

Change-Id: I402c1fd6bbb218ba80ef8e59af203c9276151059
f652cecb984c104d44a0223c3c98400ef8ed8ce2 25-Aug-2015 Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> MIPS: Initial version of optimizing compiler for MIPS32

Change-Id: I370388e8d5de52c7001552b513877ef5833aa621
e9f37600e98ba21308ad4f70d9d68cf6c057bdbe 09-Oct-2015 Aart Bik <ajcbik@google.com> Added support for unsigned comparisons

Rationale: even though not directly supported in input graph,
having the ability to express unsigned comparisons
in HIR is useful for all sorts of optimizations.

Change-Id: I4543c96a8c1895c3d33aaf85685afbf80fe27d72
ec7802a102d49ab5c17495118d4fe0bcc7287beb 01-Oct-2015 Vladimir Marko <vmarko@google.com> Add DCHECKs to ArenaVector and ScopedArenaVector.

Implement dchecked_vector<> template that DCHECK()s element
access and insert()/emplace()/erase() positions. Change the
ArenaVector<> and ScopedArenaVector<> aliases to use the new
template instead of std::vector<>. Remove DCHECK()s that
have now become unnecessary from the Optimizing compiler.

Change-Id: Ib8506bd30d223f68f52bd4476c76d9991acacadc
fa6b93c4b69e6d7ddfa2a4ed0aff01b0608c5a3a 15-Sep-2015 Vladimir Marko <vmarko@google.com> Optimizing: Tag arena allocations in HGraph.

Replace GrowableArray with ArenaVector in HGraph and related
classes HEnvironment, HLoopInformation, HInvoke and HPhi,
and tag allocations with new arena allocation types.

Change-Id: I3d79897af405b9a1a5b98bfc372e70fe0b3bc40d
6058455d486219994921b63a2d774dc9908415a2 03-Sep-2015 Vladimir Marko <vmarko@google.com> Optimizing: Tag basic block allocations with their source.

Replace GrowableArray with ArenaVector in HBasicBlock and,
to track the source of allocations, assign one new and two
Quick's arena allocation types to these vectors. Rename
kArenaAllocSuccessor to kArenaAllocSuccessors.

Bug: 23736311
Change-Id: Ib52e51698890675bde61f007fe6039338cf1a025
145acc5361deb769eed998f057bc23abaef6e116 03-Sep-2015 Vladimir Marko <vmarko@google.com> Revert "Optimizing: Tag basic block allocations with their source."

Reverting so that we can have more discussion about the STL API.

This reverts commit 91e11c0c840193c6822e66846020b6647de243d5.

Change-Id: I187fe52f2c16b6e7c5c9d49c42921eb6c7063dba
91e11c0c840193c6822e66846020b6647de243d5 02-Sep-2015 Vladimir Marko <vmarko@google.com> Optimizing: Tag basic block allocations with their source.

Replace GrowableArray with ArenaVector in HBasicBlock and,
to track the source of allocations, assign one new and two
Quick's arena allocation types to these vectors. Rename
kArenaAllocSuccessor to kArenaAllocSuccessors.

Bug: 23736311
Change-Id: I984aef6e615ae2380a532f5c6726af21015f43f5
4cd27d64b0bbdde61fa3f6674ceb24221853ac2c 19-Aug-2015 Alex Light <allight@google.com> Revert "Introduce support for hardware simulators, starting with ARM64"

This reverts commit c2e1a5edc438274159c6ef8e65455ac73723a8f1.

This breaks the build for x86_64 targets. This is because on target the libvixl is not included as a
library for the libart.so target build. The build of non-x86_64 targets only works because the
compilers removes the dead-code that contains the libvixl symbols.

Bug: 23321940
Change-Id: I39e93ff05b887665c47fb0986867f1d13ca65b9b
17ff917877041a6f212537e062f06684adcbf171 18-Aug-2015 Roland Levillain <rpl@google.com> Fix codegen_test.

Allow the execution of Thumb-2 code on ARM32 hardware.

Change-Id: I2fec71e39d538249569ffa88435f3198e8c28c01
c2e1a5edc438274159c6ef8e65455ac73723a8f1 29-Jul-2015 Phil Wang <phil.wang@linaro.org> Introduce support for hardware simulators, starting with ARM64

Simulator support for ARM64 is implemented with VIXL.
Now codegen_test will also run on all supported hardware simulators.

Change-Id: Idc740f566175d1a23c373ea9292b8fc5ba526d00
a1935c4fa255b5c20f5e9b2abce6be2d0f7cb0a8 26-Jun-2015 Roland Levillain <rpl@google.com> MIPS: Initial version of optimizing compiler for MIPS64R6.

(cherry picked from commit 4dda3376b71209fae07f5c3c8ac3eb4b54207aa8)
(amended for mnc-dev)

Bug: 21555893
Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf
Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com>
Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
0fd292ddd463f1acf26b2b17d34d9b5a4ba93985 24-Jun-2015 Nicolas Geoffray <ngeoffray@google.com> Fix codegen_test after DCE fix.

(cherry picked from commit ea80942c39cb5e9bc3e38a388583d1646c1e2a3f)

bug:22031382

Change-Id: If410045779adb9e7e611af22c988232b5bf9a902
ea80942c39cb5e9bc3e38a388583d1646c1e2a3f 24-Jun-2015 Nicolas Geoffray <ngeoffray@google.com> Fix codegen_test after DCE fix.

Change-Id: I16c64abc26c64815da4cb4034276d60e9bfb6996
4dda3376b71209fae07f5c3c8ac3eb4b54207aa8 02-Jun-2015 Alexey Frunze <Alexey.Frunze@imgtec.com> MIPS: Initial version of optimizing compiler for MIPS64R6.

Bug: 21555893
Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf
Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com>
Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
0a23d74dc2751440822960eab218be4cb8843647 07-May-2015 Nicolas Geoffray <ngeoffray@google.com> Add a parent environment to HEnvironment.

This code has no functionality change. It adds a placeholder
for chaining inlined frames.

Change-Id: I5ec57335af76ee406052345b947aad98a6a4423a
5da2180e684ae6afcb55d787f6a69bc97489bb83 20-Apr-2015 Nicolas Geoffray <ngeoffray@google.com> Fix codegen_test for long multiplication.

It seems like clang (that we use on the host) was *very* forgiving
with this broken test: the code generated for for MulLong used ebx
but this is a callee-save register in C but not ART. Also, the test
was not properly written for handling longs, so it was taking
unitialized stack entries.

GCC on target is not as forgiving.

Change-Id: I5d7a962f8a72b3ce407dce50ca50b4ffc690c99e
0d9f17de8f21a10702de1510b73e89d07b3b9bbf 15-Apr-2015 Nicolas Geoffray <ngeoffray@google.com> Move the linear order to the HGraph.

Bug found by Zheng Xu: SsaLivenessAnalysis being a stack allocated
object, we should not refer to it in later phases of the compiler.
Specifically, the code generator was using the linear order, which
was stored in the liveness analysis object.

Change-Id: I574641f522b7b86fc43f3914166108efc72edb3b
fb8d279bc011b31d0765dc7ca59afea324fd0d0c 01-Apr-2015 Mark Mendell <mark.p.mendell@intel.com> [optimizing] Implement x86/x86_64 math intrinsics

Implement floor/ceil/round/RoundFloat on x86 and x86_64.
Implement RoundDouble on x86_64.

Add support for roundss and roundsd on both architectures. Support them
in the disassembler as well.

Add the instruction set features for x86, as the 'round' instruction is
only supported if SSE4.1 is supported.

Fix the tests to handle the addition of passing the instruction set
features to x86 and x86_64.

Add assembler tests for roundsd and roundss to x86_64 assembler tests.

Change-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
8d5b8b295930aaa43255c4f0b74ece3ee8b43a47 24-Mar-2015 David Brazdil <dbrazdil@google.com> ART: Force constants into the entry block

Optimizations such as GVN and BCE make the assumption that all
constants are located in the entry block of the CFG, but not all
passes adhere to this rule.

This patch makes constructors of constants private and only accessible
to friend classes - HGraph for int/long constants and SsaBuilder for
float/double - which ensure that they are placed correctly and not
duplicated.

Note that the ArenaAllocatorAdapter was modified to not increment
the ArenaAllocator's internal reference counter in order to allow
for use of ArenaSafeMap inside an arena-allocated objects. Because
their destructor is not called, the counter does not get decremented.

Change-Id: I36a4fa29ae34fb905cdefd482ccbf386cff14166
10f56cb6b4e39ed0032e9a23b179b557463e65ad 24-Mar-2015 David Brazdil <dbrazdil@google.com> ART: Fix crash in gtests

SsaLivenessAnalysis was crashing after change of iteration order in
142377 because gtests do not always build reverse post order.

Change-Id: If5ad5b7c52040b119c4415f0b942988049fa3c16
579885a26d761f5ba9550f2a1cd7f0f598c2e1e3 22-Feb-2015 Serban Constantinescu <serban.constantinescu@arm.com> Opt Compiler: ARM64: Enable explicit memory barriers over acquire/release

Implement remaining explicit memory barrier code paths and temporarily
enable the use of explicit memory barriers for testing.

This CL also enables the use of instruction set features in the ARM64
backend. kUseAcquireRelease has been replaced with PreferAcquireRelease(),
which for now is statically set to false (prefer explicit memory barriers).

Please note that we still prefer acquire-release for the ARM64 Optimizing
Compiler, but we would like to exercise the explicit memory barrier code
path too.

Change-Id: I84e047ecd43b6fbefc5b82cf532e3f5c59076458
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
5e8b137d28c840b128e2488f954cccee3e86db14 23-Jan-2015 David Brazdil <dbrazdil@google.com> Create HGraph outside Builder, print timings

This patch refactors the way HGraph objects are created, moving the
instantiation out of the Builder class and creating the CodeGenerator
earlier. The patch uses this to build a single interface for printing
timings info and dumping the CFG.

Change-Id: I2eb63eabf28e2d0f5cdc7affaa690c3a4b1bdd21
e6362281bb4586f45fd927e9cd1b3b14c6b037ed 26-Jan-2015 Nicolas Geoffray <ngeoffray@google.com> Fix lint error and typo.

Change-Id: Ie2787a4da5b2d76975664e64f443c081127b7cd9
a0bb2bd5b6a049ad806c223f00672d1f0210db67 26-Jan-2015 Nicolas Geoffray <ngeoffray@google.com> Fix codegen_test.

Native and ART do not have the same calling convention for ART,
so we need to adjust blocked and allocated registers.

Change-Id: I606b2620c0e5a54bd60d6100a137c06616ad40b4
cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f 08-Jan-2015 Calin Juravle <calin@google.com> Add implicit null checks for the optimizing compiler

- for backends: arm, arm64, x86, x86_64
- fixed parameter passing for CodeGenerator
- 003-omnibus-opcodes test verifies that NullPointerExceptions work as
expected

Change-Id: I1b302acd353342504716c9169a80706cf3aba2c8
df64950a466c0f00cd36120d1afd389c577cae87 06-Jan-2015 Andreas Gampe <agampe@google.com> ART: Fix leak in codegen_test

Make sure the InstructionSetFeatures isn't leaked.

Change-Id: Ide25773500c1513ecb204a380bb0a95513ff7276
3416601a9e9be81bb7494864287fd3602d18ef13 19-Dec-2014 Calin Juravle <calin@google.com> Look at instruction set features when generating volatiles code

Change-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a
3e69f16ae3fddfd24f4f0e29deb106d564ab296c 10-Dec-2014 Alexandre Rames <alexandre.rames@arm.com> Opt compiler: Add arm64 support for register allocation.

Change-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7
d582fa4ea62083a7598dded5b82dc2198b3daac7 06-Nov-2014 Ian Rogers <irogers@google.com> Instruction set features for ARM64, MIPS and X86.

Also, refactor how feature strings are handled so they are additive or
subtractive.
Make MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler
rather than #ifdefs that wouldn't have worked in cross-compilation.
Add SIMD features for x86/x86-64 proposed in:
https://android-review.googlesource.com/#/c/112370/

Bug: 18056890

Change-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666
946e143941d456a4ec666f7f54719c65c5aa3f5d 11-Nov-2014 Roland Levillain <rpl@google.com> Revert "Revert "Add support for long-to-int in the optimizing compiler.""

This reverts commit 3adfd1b4fb20ac2b0217b5d2737bfe30ad90257a.

Change-Id: Iacf0c6492d49267e24f1b727dbf6379b21fd02db
3adfd1b4fb20ac2b0217b5d2737bfe30ad90257a 11-Nov-2014 Roland Levillain <rpl@google.com> Revert "Add support for long-to-int in the optimizing compiler."

This reverts commit 647b96f29cb81832e698f863884fdba06674c9de.

Change-Id: I552f23585463c676acbd547521b4d3ee5c0342eb
5ad0582482756fc6a97218472e458f31c985e922 11-Nov-2014 Calin Juravle <calin@google.com> Fix lint error.

Change-Id: Ief9b9fe6982e7e76aae74d6c909bd9f4b3f82673
647b96f29cb81832e698f863884fdba06674c9de 11-Nov-2014 Roland Levillain <rpl@google.com> Add support for long-to-int in the optimizing compiler.

- Add support for the long-to-int Dex instruction in the
optimizing compiler.
- Generate x86, x86-64 and ARM (but not ARM64) code for
long-to-int HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
- Also fix comments in test/415-optimizing-arith-neg and
in test/416-optimizing-arith-not.

Change-Id: I3084af30f2a495d178362ae1154dc7ceb7bf3a58
865fc88fdfd006ce0362c2c0d55c66a7bffdab61 06-Nov-2014 Calin Juravle <calin@google.com> [optimizing compiler] Add DIV_INT_2ADDR

Change-Id: I38fc7e216f820d8ccc8bbf8b8e7a67b75fb9de87
55dcfb5e0dd626993bb2b7b9f692c1b02b5d955f 24-Oct-2014 Roland Levillain <rpl@google.com> Add support for not-long on ARM64 in the optimizing compiler.

Change-Id: I3e98ff411ba358d92774def18a12daccdc4f558f
cd2de0c1c7f1051a2f7bdb0e827dd6057f3bafcd 06-Nov-2014 Nicolas Geoffray <ngeoffray@google.com> Fix failures after div support.

- We need to special case divide by -1 because of x86.
- Disable div test on arm64, which does not support div yet.

Change-Id: I07e137cb555a958b02a6c4070f296503b7e30bae
d0d4852847432368b090c184d6639e573538dccf 04-Nov-2014 Calin Juravle <calin@google.com> [optimizing compiler] Add div-int and exception handling.

- for backends: arm, x86, x86_64
- fixed a register allocator bug: the request for a fixed register for
the first input was ignored if the output was kSameAsFirstInput
- added divide by zero exception
- more tests
- shuffle around some code in the builder to reduce the number of lines
of code for a single function.

Change-Id: Id3a515e02bfbc66cd9d16cb9746f7551bdab3d42
277ccbd200ea43590dfc06a93ae184a765327ad0 04-Nov-2014 Andreas Gampe <agampe@google.com> ART: More warnings

Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,
and -Wunused-but-set-parameter for GCC builds.

Change-Id: I81bbdd762213444673c65d85edae594a523836e5
42d641bfd9ef3c03c68177b2a429b20056670d86 27-Oct-2014 Alexandre Rames <alexandre.rames@arm.com> Opt compiler: Add ARM64 support for the Mul IR.

Also disable compilation and use of the boot image with
the optimizing compiler: this won't work with the way
we're bringing up arm64 and we need to find a better
solution.

Bug: 18147756

Change-Id: I6ec0de73681f9226d095bc3db92338dbd46499aa
927307433af0a9322e8ba77eda37168512a73683 01-Oct-2014 Alexandre Rames <alexandre.rames@arm.com> ART: Add basic tests for materialized conditions.

Change-Id: I4acef30cc6a48b5fe07d55db6b9cf0d093b326ee
5319defdf502fc4569316473846b83180ec08035 23-Oct-2014 Alexandre Rames <alexandre.rames@arm.com> ART: optimizing compiler: initial support for ARM64.

The ARM64 port uses VIXL for code generation, to which it defers work
like label binding and branch resolving, register type coherency
checking, and immediate values handling.

Change-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Signed-off-by: Alexandre Rames <alexandre.rames@arm.com>
039b6e2fd3bfadbd1ee8583002f673d6ccba5b7e 23-Oct-2014 Calin Juravle <calin@google.com> Remove obsolete TODOs from codegen tests

The features are already exercised by the art test 411-optimizing-arith.

Change-Id: Id008931e0ed8206ced11ecc85a80a7e4aef3e68e
1cc5f251df558b0e22cea5000626365eb644c727 22-Oct-2014 Roland Levillain <rpl@google.com> Implement int bit-wise not operation in the optimizing compiler.

- Add support for the not-int (integer one's complement
negate) instruction in the optimizing compiler.
- Extend the HNot control-flow graph node type and make it
inherit from HUnaryOperation.
- Generate ARM, x86 and x86-64 code for integer HNeg nodes.
- Exercise these additions in the codegen_test gtest, as there
is not direct way to assess the support of not-int from a
Java source. Indeed, compiling a Java expression such as
`~a' using javac and then dx generates an xor-int/lit8 Dex
instruction instead of the expected not-int Dex instruction.
This is probably because the Java bytecode has an `ixor'
instruction, but there's not instruction directly
corresponding to a bit-wise not operation.

Change-Id: I223aed75c4dac5785e04d99da0d22e8d699aee2b
48dee04f4e4214b0fdd8acd0587ef6b08d3d2456 22-Oct-2014 Calin Juravle <calin@google.com> Minor fix in codegen tests.

Change-Id: I9b843536353d4f820b969895d5f75ee9b679aff0
34bacdf7eb46c0ffbf24ba7aa14a904bc9176fb2 07-Oct-2014 Calin Juravle <calin@google.com> Add multiplication for integral types

This also fixes an issue where we could allocate a pair register even if
one of its parts was already blocked.

Change-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01
360231a056e796c36ffe62348507e904dc9efb9b 08-Oct-2014 Nicolas Geoffray <ngeoffray@google.com> Fix code generation of materialized conditions.

Move the logic for knowing if a condition needs to be materialized
in an optimization pass (so that the information does not change
as a side effect of another optimization).

Also clean-up arm and x86_64 codegen:
- arm: ldr and str are for power-users when a constant is
in play. We should use LoadFromOffset and StoreToOffset.
- x86_64: fix misuses of movq instead of movl.

Change-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3
fbc695f9b8e2084697e19c1355ab925f99f0d235 15-Sep-2014 Nicolas Geoffray <ngeoffray@google.com> Revert "Revert "Implement suspend checks in new compiler.""

This reverts commit 7e3652c45c30c1f2f840e6088e24e2db716eaea7.

Change-Id: Ib489440c34e41cba9e9e297054f9274f6e81a2d8
a1c22c172046d51579f2adb1f12f658022ff022e 11-Sep-2014 Nicolas Geoffray <ngeoffray@google.com> Fix builds on archs the compiler does not support.

Change-Id: Ibfc47026596c868fb6d48465a6e564a0b1e07fd0
8a16d97fb8f031822b206e65f9109a071da40563 11-Sep-2014 Nicolas Geoffray <ngeoffray@google.com> Fix valgrind errors.

For now just stack allocate the code generator. Will think
about cleaning up the root problem later (CodeGenerator being an
arena object).

Change-Id: I161a6f61c5f27ea88851b446f3c1e12ee9c594d7
73e80c3ae76fafdb53afe3a85306dcb491fb5b00 22-Jul-2014 Nicolas Geoffray <ngeoffray@google.com> Make unit test tell if a method is a leaf.

The runtime is not initialized completely in gtests, so we
cannot run code (such as explicit stack overflow checks) that
look at tls values.

Change-Id: I74a4449b01eb203f1b411dda700e9459878d0d55
8d486731559ba0c5e12c27b4a507181333702b7e 16-Jul-2014 Nicolas Geoffray <ngeoffray@google.com> Use the thumb2 assembler for the optimizing compiler.

Change-Id: I2b058f4433504dc3299c06f5cb0b5ab12f34aa82
20550910e608ed7d86db97927d2ce9d2191061a4 25-Jun-2014 Nicolas Geoffray <ngeoffray@google.com> Re-enable tests with the optimizing compiler.

Tests run ok on my host/target. I reverted the move to
using thumb2, because tests were crashing. But I could not
reproduce file limits issues.

Change-Id: I26bc4ec1eb6c227750d11210e012d9d3b1d824af
f61b5377068f22c0be7b2f6e62961e620408beb2 25-Jun-2014 Nicolas Geoffray <ngeoffray@google.com> Re-enable tests with the optimizing compiler.

Tests run ok on my host/target. I reverted the move to
using thumb2, because tests were crashing. But I could not
reproduce file limits issues.

Make SignalTest as crashing for optimizing. We need to implement
stack overflow checks.

Change-Id: Ieda575501eaf30af7aaa2c44e71544c9c467c24f
e61fd353c06f51f1b8ca5af69997d0185b7659b2 25-Jun-2014 Nicolas Geoffray <ngeoffray@google.com> Revert "Re-enable tests with the optimizing compiler."

This reverts commit 20550910e608ed7d86db97927d2ce9d2191061a4.

Change-Id: Ic28b719946c795378838a18162a2a2b2cf41a0e8
20dfc797dc631bf8d655dcf123f46f13332d3074 17-Jun-2014 Dave Allison <dallison@google.com> Add some more instruction support to optimizing compiler.

This adds a few more DEX instructions to the optimizing compiler's
builder (constants, moves, if_xx, etc).

Also:
* Changes the codegen for IF_XX instructions to use a condition
rather than comparing a value against 0.
* Fixes some instructions in the ARM disassembler.
* Fixes PushList and PopList in the thumb2 assembler.
* Switches the assembler for the optimizing compiler to thumb2
rather than ARM.

Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
86dbb9a12119273039ce272b41c809fa548b37b6 04-Jun-2014 Nicolas Geoffray <ngeoffray@google.com> Final CL to enable register allocation on x86.

This CL implements:
1) Resolution after allocation: connecting the locations
allocated to an interval within a block and between blocks.
2) Handling of fixed registers: some instructions require
inputs/output to be at a specific location, and the allocator
needs to deal with them in a special way.
3) ParallelMoveResolver::EmitNativeCode for x86.

Change-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858
49c105d624e4bf8e56b85caaecfeb80864bd3f59 13-Jun-2014 Nicolas Geoffray <ngeoffray@google.com> Guard `Run` for platforms we're not compiling to, yet.

Change-Id: I0dc210d2734e95714bed6c481a31fa4daabb9332
9cf35523764d829ae0470dae2d5dd99be469c841 09-Jun-2014 Nicolas Geoffray <ngeoffray@google.com> Add x86_64 support to the optimizing compiler.

Change-Id: I4462d9ae15be56c4a3dc1bd4d1c0c6548c1b94be
700a402244a1a423da4f3ba8032459f4b65fa18f 20-May-2014 Ian Rogers <irogers@google.com> Now we have a proper C++ library, use std::unique_ptr.

Also remove the Android.libcxx.mk and other bits of stlport compatibility
mechanics.

Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
d8ee737fdbf380c5bb90c9270c8d1087ac23e76c 28-Mar-2014 Nicolas Geoffray <ngeoffray@google.com> Add support for adding two integers in optimizing compiler.

Change-Id: I5524e193cd07f2692a57c6b4f8069904471b2928
787c3076635cf117eb646c5a89a9014b2072fb44 17-Mar-2014 Nicolas Geoffray <ngeoffray@google.com> Plug new optimizing compiler in compilation pipeline.

Also rename accessors to ART's conventions.

Change-Id: I344807055b98aa4b27215704ec362191464acecc
39d57e2de8ec7420f2395a28cd7bd51e658d57b8 13-Mar-2014 Nicolas Geoffray <ngeoffray@google.com> Fix non-{arm, x86} builds.

Change-Id: If4c13775f8e1fd0fd26b4a731f3011c77b0bfed1
bab4ed7057799a4fadc6283108ab56f389d117d4 11-Mar-2014 Nicolas Geoffray <ngeoffray@google.com> More code generation for the optimizing compiler.

- Add HReturn instruction
- Generate code for locals/if/return
- Setup infrastructure for register allocation. Currently
emulate a stack.

Change-Id: Ib28c2dba80f6c526177ed9a7b09c0689ac8122fb
3ff386aafefd5282bb76c8a50506a70a4321e698 04-Mar-2014 Nicolas Geoffray <ngeoffray@google.com> Add register support to the optimizing compiler.

Also make if take an input and build the use list for instructions.

Change-Id: I1938cee7dce5bd4c66b259fa2b431d2c79b3cf82
d4dd255db1d110ceb5551f6d95ff31fb57420994 28-Feb-2014 Nicolas Geoffray <ngeoffray@google.com> Add codegen support to the optimizing compiler.

Change-Id: I9aae76908ff1d6e64fb71a6718fc1426b67a5c28