| 0d5a281c671444bfa75d63caf1427a8c0e6e1177 |
|
13-Nov-2015 |
Roland Levillain <rpl@google.com> |
x86/x86-64 read barrier support for concurrent GC in Optimizing.
This first implementation uses slow paths to instrument heap
reference loads and GC root loads for the concurrent copying
collector, respectively calling the artReadBarrierSlow and
artReadBarrierForRootSlow (new) runtime entry points.
Notes:
- This implementation does not instrument HInvokeVirtual
nor HInvokeInterface instructions (for class reference
loads), as the corresponding read barriers are not stricly
required with the current concurrent copying collector.
- Intrinsics which may eventually call (on slow path) are
disabled when read barriers are enabled, as the current
slow path infrastructure does not support this case.
- When read barriers are enabled, the code generated for a
HArraySet instruction always go into the array set slow
path for object arrays (delegating the operation to the
runtime), as we are lacking a mechanism to keep a
temporary register live accross a runtime call (needed for
the instrumentation of type checking code, which requires
two successive read barriers).
Bug: 12687968
Change-Id: I14cd6107233c326389120336f93955b28ffbb329
|
| ea5af68d6dda832bdfb5978a0c5d6f86a3f67e80 |
|
22-Oct-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
X86-64: Split long/double constant array/field set
A long constant needs to be in a register to store to memory.
By allowing stores of constants that are outside of the range of
int32_t, we reduce register usage.
Also support sets of float/double constants by using integer stores.
Rename RegisterOrInt32LongConstant to RegisterOrInt32Constant as it
now handles any type of constant.
Change-Id: I025d9ef889a5a433e45aa03b376bae40f14197d2
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| ec7802a102d49ab5c17495118d4fe0bcc7287beb |
|
01-Oct-2015 |
Vladimir Marko <vmarko@google.com> |
Add DCHECKs to ArenaVector and ScopedArenaVector.
Implement dchecked_vector<> template that DCHECK()s element
access and insert()/emplace()/erase() positions. Change the
ArenaVector<> and ScopedArenaVector<> aliases to use the new
template instead of std::vector<>. Remove DCHECK()s that
have now become unnecessary from the Optimizing compiler.
Change-Id: Ib8506bd30d223f68f52bd4476c76d9991acacadc
|
| 5233f93ee336b3581ccdb993ff6342c52fec34b0 |
|
29-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Tag even more arena allocations.
Tag previously "Misc" arena allocations with more specific
allocation types. Move some native heap allocations to the
arena in BCE.
Bug: 23736311
Change-Id: If8ef15a8b614dc3314bdfb35caa23862c9d4d25c
|
| 225b6464a58ebe11c156144653f11a1c6607f4eb |
|
28-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Tag arena allocations in code generators.
And completely remove the deprecated GrowableArray.
Replace GrowableArray with ArenaVector in code generators
and related classes and tag arena allocations.
Label arrays use direct allocations from ArenaAllocator
because Label is non-copyable and non-movable and as such
cannot be really held in a container. The GrowableArray
never actually constructed them, instead relying on the
zero-initialized storage from the arena allocator to be
correct. We now actually construct the labels.
Also avoid StackMapStream::ComputeDexRegisterMapSize() being
passed null references, even though unused.
Change-Id: I26a46fdd406b23a3969300a67739d55528df8bf4
|
| 2aaa4b5532d30c4e65d8892b556400bb61f9dc8c |
|
17-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Tag more arena allocations.
Replace GrowableArray with ArenaVector and tag arena
allocations with new allocation types.
As part of this, make the register allocator a bit more
efficient, doing bulk insert/erase. Some loops are now
O(n) instead of O(n^2).
Change-Id: Ifac0871ffb34b121cc0447801a2d07eefd308c14
|
| 76c92ac73eeda2582caee39dd427ca035caf172b |
|
17-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Allow storing value objects in containers.
Change-Id: Ic9c6b62e36706e571fd71c18d24d8e76ae2d5c7b
|
| fa6b93c4b69e6d7ddfa2a4ed0aff01b0608c5a3a |
|
15-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Tag arena allocations in HGraph.
Replace GrowableArray with ArenaVector in HGraph and related
classes HEnvironment, HLoopInformation, HInvoke and HPhi,
and tag allocations with new arena allocation types.
Change-Id: I3d79897af405b9a1a5b98bfc372e70fe0b3bc40d
|
| 45b83aff85a8a8dfcae0da90d010fa2d7eb299a7 |
|
06-Jul-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Fix LSRA bug with explicit register temporaries""
This reverts commit a5fc140ff315dda9bc0a8e59963ed547676cd941.
Change-Id: Ic322484176e55d0c7cd7250d629b9e5046006a4f
|
| a5fc140ff315dda9bc0a8e59963ed547676cd941 |
|
06-Jul-2015 |
Calin Juravle <calin@google.com> |
Revert "Fix LSRA bug with explicit register temporaries"
register_allocator_test32 fails.
This reverts commit 283b8541546e7673d33d104241623d07c91cf500.
Change-Id: I2a46f3c68de3e8273e402102065c13797045c481
|
| 283b8541546e7673d33d104241623d07c91cf500 |
|
03-Jul-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
Fix LSRA bug with explicit register temporaries
A temporary with an explicit RegisterLocation, such as ESI on x86 didn't
have the register marked as allocated. This caused it to not be
saved/restored in the prologue/epilogue, causing problems in the caller
routine, which expected it to be saved. Found while implementing
https://android-review.googlesource.com/#/c/157522/.
Change-Id: I22ca2b24c2d21b1c6ab6cfb7dec26cb38034a891
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| 94015b939060f5041d408d48717f22443e55b6ad |
|
04-Jun-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Use HCurrentMethod in HInvokeStaticOrDirect.""
Fix was to special case baseline for x86, which does not have enough
registers to allocate the current method.
This reverts commit c345f141f11faad177aa9635a78088d00cf66086.
Change-Id: I5997aa52f8d4df373ae5ff4d4150dac0c44c4c10
|
| c345f141f11faad177aa9635a78088d00cf66086 |
|
04-Jun-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Use HCurrentMethod in HInvokeStaticOrDirect."
Fails on baseline/x86.
This reverts commit 38207af82afb6f99c687f64b15601ed20d82220a.
Change-Id: Ib71018367eb7c6046965494a7e996c22af3de403
|
| 38207af82afb6f99c687f64b15601ed20d82220a |
|
01-Jun-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Use HCurrentMethod in HInvokeStaticOrDirect.
Change-Id: I0d15244b6b44c8b10079398c55da5071a3e3af66
|
| 0a23d74dc2751440822960eab218be4cb8843647 |
|
07-May-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a parent environment to HEnvironment.
This code has no functionality change. It adds a placeholder
for chaining inlined frames.
Change-Id: I5ec57335af76ee406052345b947aad98a6a4423a
|
| ad4450e5c3ffaa9566216cc6fafbf5c11186c467 |
|
17-Apr-2015 |
Zheng Xu <zheng.xu@arm.com> |
Opt compiler: Implement parallel move resolver without using swap.
The algorithm of ParallelMoveResolverNoSwap() is almost the same with
ParallelMoveResolverWithSwap(), except the way we resolve the circular
dependency. NoSwap() uses additional scratch register to resolve the
circular dependency. For example, (0->1) (1->2) (2->0) will be performed
as (2->scratch) (1->2) (0->1) (scratch->0).
On architectures without swap register support, NoSwap() can reduce the
number of moves from 3x(N-1) to (N+1) when there is circular dependency
with N moves.
And also, NoSwap() algorithm does not depend on architecture register
layout information, which means it can support register pairs on arm32
and X/W, D/S registers on arm64 without additional modification.
Change-Id: Idf56bd5469bb78c0e339e43ab16387428a082318
|
| a978d43fc40984e0cef0c4d42076263f5a20b5b5 |
|
15-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Add a check in the location summary."
My assumption was wrong. We actually can use same as first input with any, *only if* the generate code does not clobber the first input. We use this for, e.g. DivZeroCheck, NullCheck.
This reverts commit 95bf7547986e68d4ac93b0a529aaa8eb3c998c1f.
Change-Id: Ib72d73fe580f5bc707b41c651f2c8936bd4e2407
|
| 95bf7547986e68d4ac93b0a529aaa8eb3c998c1f |
|
14-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a check in the location summary.
Having SameAsFirstInput for out, and first input Any does not
make sense currently. If it's stack, we are going to overwrite
it, potentially clobbering another local. And constant does not
make sense.
Change-Id: I0ce357137487ed3dcecf4efd9922a039a2a1a29d
|
| 3f6c7f61855172d3d9b7a9221baba76136088e7c |
|
13-Mar-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
[optimizing] Improve x86, x86_64 code
Tweak the generated code to allow more use of constants and other small
changes
- Use test vs. compare to 0
- EmitMove of 0.0 should use xorps
- VisitCompare kPrimLong can use constants
- cmp/add/sub/mul on x86_64 can use constants if in int32_t range
- long bit operations on x86 examine long constant high/low to optimize
- Use 3 operand imulq if constant is in int32_t range
Change-Id: I2dd4010fdffa129fe00905b0020590fe95f3f926
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| 234d69d075d1608f80adb647f7935077b62b6376 |
|
09-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "[optimizing] Enable x86 long support.""
This reverts commit 154552e666347d41d95d7619c6ee56249ff4feca.
Change-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13
|
| 154552e666347d41d95d7619c6ee56249ff4feca |
|
06-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "[optimizing] Enable x86 long support."
Few libcore failures.
This reverts commit b4ba354cf8d22b261205494875cc014f18587b50.
Change-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63
|
| b4ba354cf8d22b261205494875cc014f18587b50 |
|
05-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
[optimizing] Enable x86 long support.
Change-Id: I9006972a65a1f191c45691104a960366747f9d16
|
| b666f4805c8ae707ea6fd7f6c7f375e0b000dba8 |
|
18-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move arenas into runtime
Moved arena pool into the runtime.
Motivation:
Allow GC to use arena allocators, recycle arena pool for linear alloc.
Bug: 19264997
Change-Id: I8ddbb6d55ee923a980b28fb656c758c5d7697c2f
|
| da02afe615191a19eae9a039786c4c4fc20dbfff |
|
11-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Support hints for register pairs.
Change-Id: Ia49dc5bf3e9a2bd481425bfe7fbeea9feb66c8e6
|
| f7a0c4e421b5edaad5b7a15bfff687da28d0b287 |
|
10-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Improve ParallelMoveResolver to work with pairs.
Change-Id: Ie2a540ffdb78f7f15d69c16a08ca2d3e794f65b9
|
| 829280cc90b7a84db42864589b4bafb4c94a79d9 |
|
28-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Finally implement Location::kNoOutputOverlap.
The [i, i + 1) interval scheme we chose for representing
lifetime positions is not optimal for doing this optimization.
It however doesn't prevent recognizing a non-split interval
during the TryAllocateFreeReg phase, and try to re-use
its inputs' registers.
Change-Id: I80a2823b0048d3310becfc5f5fb7b1230dfd8201
|
| 3e6a3bf797e49b7f449256455c7e522e888687d8 |
|
19-Jan-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Change x86 long param ABI (Quick/JNI/Opt)
Ensure that we don't pass a long parameter across the last register
and the stack: skip the register and allocate it only on the stack.
This was requested to simplify the optimizing compiler code
generation for x86.
Optimizing (Baseline) compiler support for x86 longs:
- Remove QuickParameter from Location, as there are no longer any uses
of it.
Bump oat.h version because we changed an ABI again.
I changed IsParamALong() to return false for argument 0 (this argument).
I am not sure why it differed from all other tests.
I have not tested on ARM. I followed Nicolas's suggestions for setting
the value of kSplitPairAcrossRegisterAndStack for different
architectures.
Change-Id: I2f16b33c1dac58dd4f4f503e9c2309d845f5fb7a
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| 878d58cbaf6b17a9e3dcab790754527f3ebc69e5 |
|
16-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Arm64 optimizing compiler intrinsics
Implement most intrinsics for the optimizing compiler for Arm64.
Change-Id: Idb459be09f0524cb9aeab7a5c7fccb1c6b65a707
|
| 988939683c26c0b1c8808fc206add6337319509a |
|
21-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Enable core callee-save on x64.
Will work on other architectures and FP support in other CLs.
Change-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d
|
| 6c2dff8ff8e1440fa4d9e1b2ba2a44d036882801 |
|
21-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Fully support pairs in the register allocator.""
This reverts commit c399fdc442db82dfda66e6c25518872ab0f1d24f.
Change-Id: I19f8215c4b98f2f0827e04bf7806c3ca439794e5
|
| c399fdc442db82dfda66e6c25518872ab0f1d24f |
|
21-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Fully support pairs in the register allocator."
Libcore tests fail.
This reverts commit 41aedbb684ccef76ff8373f39aba606ce4cb3194.
Change-Id: I2572f120d4bbaeb7a4d4cbfd47ab00c9ea39ac6c
|
| 41aedbb684ccef76ff8373f39aba606ce4cb3194 |
|
14-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Fully support pairs in the register allocator.
Enabled on ARM for longs and doubles.
Change-Id: Id8792d08bd7ca9fb049c5db8a40ae694bafc2d8b
|
| 42d1f5f006c8bdbcbf855c53036cd50f9c69753e |
|
16-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Do not use register pair in a parallel move.
The ParallelMoveResolver does not work with pairs. Instead,
decompose the pair into two individual moves.
Change-Id: Ie9d3f0b078cef8dc20640c98b20bb20cc4971a7f
|
| 71fb52fee246b7d511f520febbd73dc7a9bbca79 |
|
30-Dec-2014 |
Andreas Gampe <agampe@google.com> |
ART: Optimizing compiler intrinsics
Add intrinsics infrastructure to the optimizing compiler.
Add almost all intrinsics supported by Quick to the x86-64 backend.
Further intrinsics require more assembler support.
Change-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807
|
| 840e5461a85f8908f51e7f6cd562a9129ff0e7ce |
|
07-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement double and float support for arm in register allocator.
The basic approach is:
- An instruction that needs two registers gets two intervals.
- When allocating the low part, we also allocate the high part.
- When splitting a low (or high) interval, we also split the high
(or low) equivalent.
- Allocation follows the (S/D register) requirement that low
registers are always even and the high equivalent is low + 1.
Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
|
| 271ab9c916980209fbc6b26e5545d76e58471569 |
|
27-Nov-2014 |
Roland Levillain <rpl@google.com> |
Ensure opt. compiler doesn't get core & FP registers mixed up.
Replace Location::As<T>() with two method methods
(Location::AsRegister<T>() and Location::AsFpuRegister<T>())
checking the kind of the location (register).
Change-Id: I22b4abee1a124b684becd2dc1caf33652b911070
|
| 87d03761f35ad6cbe0bffbf1ec739875a471da6d |
|
19-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix safepoint bug when computing live registers.
Change-Id: I8f28dd287c0e04223c49dea6a323058c1b210913
|
| f43083d560565aea46c602adb86423daeefe589d |
|
07-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Do not update Out after it has a valid location.
Slow paths use LocationSummary to know where to move
things around, and they are executed at the end of the
code generation.
This fix is needed for https://android-review.googlesource.com/#/c/113345/.
Change-Id: Id336c6409479b1de6dc839b736a7234d08a7774a
|
| 424f676379f2f872acd1478672022f19f3240fc1 |
|
03-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement CONST_CLASS in optimizing compiler.
Change-Id: Ia8c8dfbef87cb2f7893bfb6e178466154eec9efd
|
| 785d2f2116bb57418d81bb55b55a087afee11053 |
|
04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: Replace COMPILE_ASSERT with static_assert (compiler)
Replace all occurrences of COMPILE_ASSERT in the compiler tree.
Change-Id: Icc40a38c8bdeaaf7305ab3352a838a2cd7e7d840
|
| 6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f |
|
31-Oct-2014 |
Ian Rogers <irogers@google.com> |
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.
Fix associated errors about unused paramenters and implict sign conversions.
For sign conversion this was largely in the area of enums, so add ostream
operators for the effected enums and fix tools/generate-operator-out.py.
Tidy arena allocation code and arena allocated data types, rather than fixing
new and delete operators.
Remove dead code.
Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
|
| 0a6c459f713ff61769a02204cd736167e062bf4c |
|
30-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix for long parameter passed both in stack and register.
Fix for long parameter passed both in stack and register
on 32bits architectures.
The move to hard float ABI makes it so that the
register index does not necessarily match the stack index anymore.
Change-Id: I26b483f68ac86d336b4a37d94c38b04917668659
|
| 19a19cffd197a28ae4c9c3e59eff6352fd392241 |
|
22-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for static fields in optimizing compiler.
Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
|
| 1ba0f596e9e4ddd778ab431237d11baa85594eba |
|
27-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support hard float on arm in optimizing compiler.
Also bump oat version, needed after latest hard float switch.
Change-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965
|
| 8e3964b766652a0478e8e0e303e8556c997675f1 |
|
17-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Remove the notion of dies at entry.
- Instead, explicitly say that the output does not overlap.
- Inputs that must be in a fixed register do die at entry,
as we know they have a location that others can not take.
- There is also no need to differentiate between an input move
and a connecting sibling move - those can be put in the
same parallel move instruction.
Change-Id: I1b2b2827906601f822b59fb9d6a21d48e43bae27
|
| 13735955f39b3b304c37d2b2840663c131262c18 |
|
08-Oct-2014 |
Ian Rogers <irogers@google.com> |
stdint types all the way!
Change-Id: I4e4ef3a2002fc59ebd9097087f150eaf3f2a7e08
|
| 0279ebb3efd653e6bb255470c99d26949c7bcd95 |
|
09-Oct-2014 |
Ian Rogers <irogers@google.com> |
Tidy ELF builder.
Don't do "if (ptr)". Use const. Use DISALLOW_COPY_AND_ASSIGN. Avoid public
member variables.
Move ValueObject to base and use in ELF builder.
Tidy VectorOutputStream to not use non-const reference arguments.
Change-Id: I2c727c3fc61769c3726de7cfb68b2d6eb4477e53
|
| 56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f |
|
09-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Stop converting from Location to ManagedRegister.
Now the source of truth is the Location object that knows
which register (core, pair, fpu) it needs to refer to.
Change-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1
|
| 7fb49da8ec62e8a10ed9419ade9f32c6b1174687 |
|
06-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for floats and doubles.
- Follows Quick conventions.
- Currently only works with baseline register allocator.
Change-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3
|
| 26a25ef62a13f409f941aa39825a51b4d6f0f047 |
|
30-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a prepare for register allocation pass.
- Currently the pass just changes the uses of checks to the
actual values.
- Also optimize array access, now that inputs can be constants.
- And fix another bug in the register allocator reveiled by
this change.
Change-Id: I43be0dbde9330ee5c8f9d678de11361292d8bd98
|
| 9ae0daa60c568f98ef0020e52366856ff314615f |
|
30-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for inputs dying at entry of instructions.
- Start using it in places where it makes sense.
- Also improve suspend check on arm to use subs directly.
Change-Id: I09ac0589f5ccb9b850ee757c76dcbcf35ee8cd01
|
| 7690562d40878f44823d5fb03a2084cfc677ec4a |
|
25-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Register allocator: refine instructions liveness.
Add support for instructions that die at the beginning
of another instruction. Before, an instruction needed
to stay alive during the instruction, so the register
allocator was not able not reuse the register.
Change-Id: I5f11a80b0a20778227229eb797816edcc6365297
|
| 5799fc0754da7ff2b50b472e05c65cd4ba32dda2 |
|
25-Sep-2014 |
Roland Levillain <rpl@google.com> |
Optimizing compiler: remove unnecessary `explicit' keywords.
Change-Id: I5927fd92d53308c81e14edbd6e7d1c943bfa085b
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| 3c04974a90b0e03f4b509010bff49f0b2a3da57f |
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24-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Optimize suspend checks in optimizing compiler.
- Remove the ones added during graph build (they were added
for the baseline code generator).
- Emit them at loop back edges after phi moves, so that the test
can directly jump to the loop header.
- Fix x86 and x86_64 suspend check by using cmpw instead of cmpl.
Change-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a
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| 3bca0df855f0e575c6ee020ed016999fc8f14122 |
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19-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support for saving and restoring live registers in a slow path.
And use it in suspend check slow paths.
Change-Id: I79caf28f334c145a36180c79a6e2fceae3990c31
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| 3946844c34ad965515f677084b07d663d70ad1b8 |
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02-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Runtime support for the new stack maps for the opt compiler.
Now most of the methods supported by the compiler can be optimized,
instead of using the baseline.
Change-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa
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| 96f89a290eb67d7bf4b1636798fa28df14309cc7 |
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11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add assembly operations with constants in optimizing compiler.
Change-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f
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| 9cf35523764d829ae0470dae2d5dd99be469c841 |
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09-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add x86_64 support to the optimizing compiler.
Change-Id: I4462d9ae15be56c4a3dc1bd4d1c0c6548c1b94be
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| ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
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03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE
Merge ART from AOSP to lmp-preview-dev.
Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
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| 76716a69a0e51b3516227e8b7e365e4b9490618c |
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23-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Forgot these files from last commit.
Change-Id: I9ab7975daa5ed7aae6bff8730bb63fb48a798ea8
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