History log of /external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
cddc3e03e4ec99c0268c03a126195173e519ed58 04-Mar-2016 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r256229

http://b/26987366

(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)

Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
6948897e478cbd66626159776a8017b3c18579b9 01-Jul-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r239765

Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.

Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
4c5e43da7792f75567b693105cc53e3f1992ad98 08-Apr-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master llvm for rebase to r233350

Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
ffc7dca885151ed42642c2d6733e8db75d276621 29-Oct-2013 Rafael Espindola <rafael.espindola@gmail.com> Add a helper getSymbol to AsmPrinter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
a300b1cc29020b7dfaf7bfe443d38af8fbec7433 29-Oct-2013 Rafael Espindola <rafael.espindola@gmail.com> The asm printer has a mangler. Use it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
d04a8d4b33ff316ca4cf961e06c9e312eff8e64f 03-Dec-2012 Chandler Carruth <chandlerc@gmail.com> Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
f09a03776dbbc882c9b15eeccb8ec847058fbfa0 21-Nov-2012 Akira Hatanaka <ahatanaka@mips.com> [mips] Generate big GOT code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
a7570a3d8686a1fe2075b5bee01650490fa52b26 06-Sep-2012 Jack Carter <jcarter@mips.com> There are some Mips instructions that are lowered by the
assembler such as shifts greater than 32. In the case
of direct object, the code gen needs to do this lowering
since the assembler is not involved.

With the advent of the llvm-mc assembler, it also needs
to do the same lowering.

This patch makes that specific lowering code accessible
to both the direct object output and the assembler.

This patch does not affect generated output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163287 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
3185f9a2ea80afec30064b7cd095f82c31dc154e 31-Aug-2012 Jack Carter <jcarter@mips.com> The instruction DINS may be transformed into DINSU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
714313b4828cec98b086b54b356407540aa775c4 28-Aug-2012 Jack Carter <jcarter@mips.com> The instruction DEXT may be transformed into DEXTU or DEXTM depending
on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
b22c9289b0dd8255f63038e9bb8229111eb082ae 21-Jul-2012 Akira Hatanaka <ahatanaka@mips.com> Add HIGHER and HIGHEST relocations to Mips backend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
e035f65b16956cdb7ba29e741b7e3c04a8ce4d24 16-Jul-2012 Jack Carter <jcarter@mips.com> Doubleword Shift Left Logical Plus 32

Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63

Here is a description of DSLL:

Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits

Description: GPR[rd] <- GPR[rt] << (sa+32)

The 64-bit doubleword contents of GPR rt are shifted left, inserting
zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.

This patch implements the direct object output of these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
864f66085cd9543070ef01b9f7371c110ecd7898 14-Jun-2012 Akira Hatanaka <ahatanaka@mips.com> Fix coding style violations. Remove white spaces and tabs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
63b37f122d592c7451090ea32281686de967fcd4 14-Jun-2012 Akira Hatanaka <ahatanaka@mips.com> Remove code in MipsAsmPrinter and MipsMCInstLower.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
4c8acecfe3351084b5856a8131f77cc9df4fbfec 02-Jun-2012 Akira Hatanaka <ahatanaka@mips.com> Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157867 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
bed5b0db452f9f94facf260ca8667cf670c26c5c 02-Jun-2012 Akira Hatanaka <ahatanaka@mips.com> In MipsMCInstLower::LowerSymbolOperand, get offset from symbol if
the MachineOperand type has a valid offset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
8951abd9934de0cf11bb2abc8d3fc4ff172cc026 25-May-2012 Akira Hatanaka <ahatanaka@mips.com> Remove the code that expands MIPS' .cpload directive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
6a1a2b139562bb2b17771a88f68dcb7dd006b4d4 25-May-2012 Akira Hatanaka <ahatanaka@mips.com> Remove the code that emits MIPS' .cprestore directive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
4147e4d054b62eb2ea8259db0385791ec23c460b 12-May-2012 Akira Hatanaka <ahatanaka@mips.com> Make the following changes in MipsAsmPrinter.cpp:

- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
f93b86306683f8e860c8824efb717995cb072a70 28-Mar-2012 Akira Hatanaka <ahatanaka@mips.com> Emit all directives except for ".cprestore" during asm printing rather than emit
them as machine instructions. Directives ".set noat" and ".set at" are now
emitted only at the beginning and end of a function except in the case where
they are emitted to enclose .cpload with an immediate operand that doesn't fit
in 16-bit field or unaligned load/stores.

Also, make the following changes:
- Remove function isUnalignedLoadStore and use a switch-case statement to
determine whether an instruction is an unaligned load or store.

- Define helper function CreateMCInst which generates an instance of an MCInst
from an opcode and a list of operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
79aa3417eb6f58d668aadfedf075240a41d35a26 17-Mar-2012 Craig Topper <craig.topper@gmail.com> Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
bb481f882093fb738d2bb15610c79364bada5496 28-Feb-2012 Jia Liu <proljc@gmail.com> remove blanks, and some code format

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
648f00c2f0eb29c0ae2a333fa0bfa55970059f08 24-Feb-2012 Akira Hatanaka <ahatanaka@mips.com> Add an option to use a virtual register as the global base register instead of
reserving a physical register ($gp or $28) for that purpose.

This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register.

example:

.cpload $25 // set $gp.
...
.cprestore 16 // store $gp to stack slot 16($sp).
...
jalr $25 // function call. clobbers $gp.
lw $gp, 16($sp) // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25 // function call.
lw $gp, 16($sp) // not emitted if $gp is not live after this instruction.
...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
c5707112e7635d1dd2f2cc9c4f42e79a51302cca 17-Feb-2012 Jia Liu <proljc@gmail.com> remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
8f5e8c1cd69fa77bea20140a7132ee2dea166c6d 17-Feb-2012 Jia Liu <proljc@gmail.com> add Emacs tag and fix some comment error in file headers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
bc2198133a1836598b54b943420748e75d5dea94 07-Feb-2012 Craig Topper <craig.topper@gmail.com> Convert assert(0) to llvm_unreachable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
71f0fc1ca88965b69b4b2c8794a7144bc93d4bba 19-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Ignore register mask operands when lowering instructions to MC.

This is similar to implicit register operands. MC doesn't understand
register liveness and call clobbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
ce8524c0160787fc727c16816979302df42b914a 30-Dec-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Cleanup Mips code and rename some variables. Patch by Jack Carter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147383 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
82099683060abb1f74453d06e78a3729a75ef7ee 19-Dec-2011 Akira Hatanaka <ahatanaka@mips.com> Tidy up. Simplify logic. No functional change intended.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
3faac0a78c7a70d3dcd2af102a132bb9da2d639c 14-Dec-2011 Akira Hatanaka <ahatanaka@mips.com> Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
emission is not supported yet, but a patch that adds the support should follow
soon.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
044a784fa586cf92bb712c6dc54f925f539e19d1 13-Dec-2011 Akira Hatanaka <ahatanaka@mips.com> Expand .cprestore directive to multiple instructions if the offset does not fit
in a 16-bit field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
e3d3572e282733bd7aa5ac14115ed0804174e426 07-Dec-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Add a few moreLocal/Global R_MIPS_GOT related fixups and
make the addend fixup code a bit more generic

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
421455f1ea081e2e1767e782ac0d57ca55976e9b 23-Nov-2011 Akira Hatanaka <ahatanaka@mips.com> This patch makes the following changes necessary for MIPS' direct code emission.

- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145113 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
47b92f3d8362518596d57269dc53d985bc13323a 11-Nov-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Mips MC object code emission improvements:

"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144414 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
ce1a538ab5b7ae7e0ed48d18c02571280fe105aa 08-Nov-2011 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
e33ca9ce1f978b8129972922f1ac0c16eec9e5f1 22-Sep-2011 Akira Hatanaka <ahatanak@gmail.com> Add enums and functions for symbols Mips64 uses.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
8ddf6531b88937dec35bf2bb3a55245b1af9cbf5 09-Sep-2011 Akira Hatanaka <ahatanak@gmail.com> Drop support for Mips1 and Mips2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
614051a1c534aff052152b0162a414b3271e8fca 16-Aug-2011 Akira Hatanaka <ahatanak@gmail.com> Fix handling of double precision loads and stores when Mips1 is targeted.

Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
8957481e6a3a4217499f739bae24401576ade078 16-Aug-2011 Akira Hatanaka <ahatanak@gmail.com> Define function MipsMCInstLower::LowerOperand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
78d1b11aa57e5a2683e4be3baaaa9576ac04eea2 16-Aug-2011 Akira Hatanaka <ahatanak@gmail.com> Add parameter Offset to MipsMCInstLower::LowerSymbolOperand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137706 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
01843361953463519db42e8098dc8b31b45407c8 08-Jul-2011 Akira Hatanaka <ahatanak@gmail.com> Raise assertion when MachineOperand has unexpected target flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134671 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
18dfcb8a2809204e9cd38099a766e3bb101cc249 08-Jul-2011 Akira Hatanaka <ahatanak@gmail.com> Make sure variable Kind is assigned a value to suppress warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp
17a2f8e551dd4a772d389d1a193235ae56f8a399 07-Jul-2011 Akira Hatanaka <ahatanak@gmail.com> Define class MipsMCInstLower.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsMCInstLower.cpp