aa5b393c69cf24d47a5727d15584f3daeba1aead |
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11-Oct-2012 |
David Chisnall <csdavec@swan.ac.uk> |
Expose move to/from coprocessor instructions in MIPS64 mode. Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/Mips/mips-coprocessor-encodings.s
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