| d9c7fcff8fb3247f2ff241d97326b329f5bab487 |
|
23-Jan-2013 |
Chad Versace <chad.versace@linux.intel.com> |
i965/disasm: Fix horizontal stride of dest registers
The bug: The printed horizontal stride was the numerical value of the
BRW_HORIZONTAL_$N enum.
The fix: Translate the enum before printing.
Note: This is a candidate for the stable releases.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
(cherry picked from commit ca7d332253e237c51fdf5c88a8f7937e65e8abff)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| bddb2edab616d30f7894cfff7071a70d273a848e |
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12-Mar-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for gen6+ UIP/JIP on BREAK/CONT/HALT.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 2b28fd6ca603df40a5d02aac4035eced3a1d079a |
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22-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the MAD opcode on gen6+.
v2: Fix MRF handling on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| dcdfd1905c8012fe0a90e553f2a894c12cf144cf |
|
18-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix disassembly of data port writes on Ivybridge.
msg_type moved by a bit, so the message type was being disassembled
incorrectly. In particular, render target writes were showing up as
"OWORD block write".
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| a608be5d3333244f5357c459135b17b4c2298e18 |
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18-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix disassembly of sampler messages on Ivybridge.
Compared to sampler_gen5, simd_mode shifted by a bit and msg_type grew
by a bit. So we were printing slightly incorrect numbers.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 60982976ee14c271353b9545ca5ac085b97ab9b0 |
|
19-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add sensible disasm for the JMPI instruction.
We care about the jump distance, not that the first src is always the
ip register.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 188f0742558196367df24086c4dc9865ebd86f7e |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disassemble Ivybridge Data Port/Data Cache messages.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 53798f90e818e9bf213c3ae4298751362a5ecd50 |
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08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename pixel_scoreboard_clear to last_render_target for clarity.
Finding this bit in the documentation proved challenging. It wasn't in
the SEND instruction's message descriptor section, nor the data port
message descriptor section. It turns out to be part of the Render
Target Write message's control bits, and in the documentation is named
"Last Render Target Select".
Shaders that use Multiple Render Targets should set this bit on the last
RT write, but not on any prior ones.
The GPU does update the Pixel Scoreboard appropriately, but doesn't
document this bit as directly causing a scoreboard clear.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| feaff3aeebb2eebfa93ad641e0ed286ab0409d21 |
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08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove duplicate copies of mlen & rlen from instruction decode.
After printing the details of a specific message, we always print out
the message length and response length with nice "mlen" and "rlen"
labels.
For Gen5+ URB writes, we were dumping mlen and rlen a second time:
urb 0 urb_write interleave used complete mlen 5, rlen 0 mlen 5 rlen 0
Also, for Gen6 data port messages, we were including mlen and rlen in
the tuple of undecipherable integers.
Both of these are completely redundant. So, remove them.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 2e124388a4642d1e7f5154e7b83d38578c6b2789 |
|
08-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename BRW_MESSAGE_TARGET_* to BRW_SFID_* and document them.
When reading the data port code, it was not clear to me what these
values meant, nor where I could find them in the documentation.
Especially since the latest BSpec and older PRMs document them in
radically different places...neither of which are near the descriptions
of individual messages.
Cite the documentation, and rename them to SFID to signify that these
are Shared Function IDs that one can read about in the GPU overview,
rather than arbitrary bitfields. While we're add it, make them an enum.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 8de3314f636f57145e008697df34560d3badf41c |
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03-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix disassembly for intdiv/intmod math functions.
The opcodes and strings were reversed. Quotient means division, and
modulus means remainder.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| e94bdbe04a4f0adb73ab92153987f0c9f48814f7 |
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08-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add gen6 disassembly for DP render cache messages.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| c77855d64eae45786d2d637bd065c8a700b788e5 |
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13-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename dp_render_target struct to gen6_dp.
This is actually just the message descriptor for Gen6+ dataport access;
it has nothing to do with the render cache. Access to the sampler cache
and constant cache also would use this struct; rename for clarity.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 5dc53444c8323c1787dddbe6b67048828df9c684 |
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23-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Correct the dp_read message descriptor setup on g4x.
It's mostly like gen4 message descriptor setup, except that the sizes
of type/control changed to be like gen5. Fixes 21 piglit cases on
gm45, including the regressions in bug #32311 from increased VS
constant buffer usage.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| a9f62881a316539658845a98b856f1bf31ca44bc |
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02-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Dump the WHILE jump distance on gen6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 9b1d26f78f74ba7f0d5c940f848c21b43ef69398 |
|
26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for the flag register.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 1732a8bc72fe0a8eaf7449eda65eba1a017ae909 |
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26-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use SENDC on the first render target write on gen6.
This is apparently required, as the thread will be initiated while it
still has dependencies, and this is what waits for those to be
resolved before writing color.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 5d99b01501128c7179cdd6aa29bc8953d0d81e75 |
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06-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add some clarification of the WECtrl field.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| feca6609390d4642418cf7aab878e654964510c4 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up IF/ELSE/ENDIF for gen6.
The jump delta is now in the part of the instruction where the
destination fields used to be, and the src args are ignored (or not,
for the new non-predicated IF that we don't use yet).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 739aec39bd25e79adce306d6cf48296b7c9e4fc0 |
|
05-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.
It instead sensibly appears in the src0 slot.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| bf60f3593452f6ab6340c7a8737cc74f223f2a62 |
|
17-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: disasm quarter and write enable instruction control on sandybridge
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| af62060ef264998f96eb977d6e0a5de9fe2bd651 |
|
29-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for gen5 sampler messages.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 93ba0055c325007656c14ba38302e21be3dc599f |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add AccWrCtl support on Sandybridge.
Whenever the accumulator results are needed, this bit must be set.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| ffb5095d56c0f58a35e12d40bb4ffc869e4071bd |
|
20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Mention the mlen and rlen for URB reads.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 0e2d0cc577270f86691d6bb84a50d11e3a6d0754 |
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20-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Adjust disasm of subreg numbers to be in units of the register type.
This makes reading the code easier when matching up to the specs,
which also use this format.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 62383ae6fe5d2ca092e8f9d8dae2ba9562e03d95 |
|
09-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for Compr4 instruction compression.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 4ea71cbd0e5f622f760a01120b0ccf4baf4ee7c7 |
|
22-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix the disasm output for da16 src widths.
This has confused me twice now. It's a fixed width of 4 (usually a
region description of <4,4,1>), not 1. If it was 1, we'd have been
skipping all over register space.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 0ecf5128a43ed1eff980825e425a030d2b71e50b |
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21-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for dataport reads (register unspilling).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 8a3f2eb9e6c830ff953751221961f2a6c8f76661 |
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08-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for SEND mlen/rlen on Sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| a3cc7585eae1dd7aa1f2257e787c784672f49831 |
|
08-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix disasm of a SEND's mlen and rlen on Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 3f906621da3647d06b7c9903f4b7367efebd82b7 |
|
29-Jun-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Add decode for Sandybridge DP write messages.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 1c25353bc66902ed684b41bb8198b9787c0ce25b |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Parse the ff_sync URB send opcode on Ironlake disasm.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 36eda76fea02130d30be6a5f0d83f04698da2853 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Dump out the correct shared function for SEND on Ironlake.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| d9ea1af82c233a10adbf9b842546e9322480591b |
|
22-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add disasm for SNB MATH opcode.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|
| 56ff30a9f97a1a7094432333906544d6138d6bf2 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the PLN instruction when possible in interpolation.
Saves an instruction in PINTERP, LINTERP, and PIXEL_W from
brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have
to be laid out differently.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| c8ef7a09664d29dac682b953eb66efaebbdd6fd7 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Print the offset for IFF in disasm
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 280abdacf900d591ef909cf697f0c5679389c3f6 |
|
09-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Print the offsets for WHILE and BREAK in disasm.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 25024d948298a9f3f3210a0b91486f79a3917b0f |
|
31-Dec-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
configs/darwin
src/gallium/auxiliary/util/u_clear.h
src/gallium/state_trackers/xorg/xorg_exa_tgsi.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
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| 070bbd4fcd5d2b669b880b91730a7ad9d130e416 |
|
23-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix setup of immediate types for gen4 disasm.
Caught by clang.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| f5ad1d0d02cae06bff3ee120c75ad4ab458d2c7d |
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25-Dec-2009 |
Vinson Lee <vlee@vmware.com> |
i965: Add missing va_end.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 8288ab4518241746be9989e008b48345c7394d10 |
|
05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Print out ELSE and ENDIF src1 arguments like IF does.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| 1d4bace9fca64c61ccd9f4205262417fa0ae3883 |
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05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out,
and running intel-gen4disasm on it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
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| ce63e9929cf3515e4ad4ea54fa5227d71ae48b93 |
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05-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Initial import of disasm code from intel-gen4asm.
There's a bunch of stuff from gen4asm and gpu-tools that we probably want
to make into a library instead of cargo-culting it around.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_disasm.c
|