| b922999a404322a1034c4f96c21acae860483bb0 |
|
25-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix primitive restart on Haswell.
Haswell moved the "Cut Index Enable" bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us
to specify the cut index rather than assuming it's 0xffffffff.
This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.
Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 815d9d405c69bb07d550ae9f79283dcdc7466e2c)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 0586a94929bb276c349220026cfac6267b776fb3 |
|
21-Sep-2012 |
Eric Anholt <eric@anholt.net> |
i965: Remove broken non-interleaved-to-interleaved upload code.
This failed when all the uploads to occur were uniform-type vertex data (like
glColor4f being active across a DrawArrays), because it would upload 1 element
instead of 1 element per vertex. There was no citation for how this code
helped any particular application, and it breaks ETQW, so just remove it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47170
NOTE: This is a candidate for the 9.0 and 8.0 branches.
Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 0334e8dc25d09e3254e61d5d122b4fd7bfbd627a)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 628dfe9511c15cc265b103e4752e3ee31b04602b |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Drop the old sw fallback for position array being disabled.
This code has been in the driver since the first commit. I think it was
trying to stop rendering from happening with a disabled position array. Core
mesa has since had changes to deal with disabled position arrays correctly.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 04a11b5f5e22155e5816e2da560b485eb0eaaec9 |
|
28-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for edge flags.
Fixes the 3 new piglit edgeflag tests.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40707
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b3367f56d880550befb31a0100c448e1d607915f |
|
28-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Convert EdgeFlagPointer values appropriately for the VS on gen4.
Fixes piglit gl-2.0/edgeflag.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3588098ed85bbd6bacac5a8dd3774569f1314783 |
|
27-May-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: enable ARB_instanced_arrays extension
Set the step_rate value when drawing to implement
ARB_instanced_arrays for gen >= 4.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f9389fbfb204995a650047949c48ab2b2703bfcf |
|
13-May-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: add flag to enable cut_index
When brw->prim_restart.enable_cut_index is set, the cut index
will be enabled when uploading index_buffer commands.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c59bdee12ebc14fb97e33b8ef9df666422dafba5 |
|
27-Feb-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Disable PrimitiveID upload.
We currently don't support gl_PrimitiveID, and I believe asking the
hardware to generate it results in vertex cache invalidations.
This could result in slowdowns for applications that use gl_InstanceID,
which would be counter-productive. Just turn it off for now.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| dca6a28a14f22d77273d79d44f57b0d853c0242d |
|
31-Oct-2011 |
Mathias Fröhlich <Mathias.Froehlich@web.de> |
mesa: Make gl_program::InputsRead 64 bits.
Make gl_program::InputsRead a 64 bits bitfield.
Adapt the intel and radeon driver to handle a 64 bits
InputsRead value.
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1c65abb211e6a3df8c46180ae3242486ee97dc8d |
|
09-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gl_VertexID and gl_InstanceID.
The compiler setup for these VF-uploaded attributes looks a little
cheesy with mixing system values and real VBO-sourced attributes. It
would be nice if we could just compute the ATTR[] map to GRF index up
front and use it at visit time instead of using ir->location in the
ATTR file. However, we don't know the reg_offset at
visit(ir_variable *) time, so we can't do the mapping that early.
Fixes piglit vertexid test.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9472f6677672ac89d6addba025b33287670da9e9 |
|
09-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Replace a should-never-happen fallback with asserts where it matters.
We only allow 16 vec4s of attributes in our GLSL/ARB_vp programs, and
1 more element will get used for gl_VertexID/gl_InstanceID. So it
should never have been possible to hit this fallback, unless there was
another bug. If you do hit this, you're probably using gl_VertexID
and falling back to swrast won't work for you anyway.
This also updates the limits for gen6+.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 29e2bc8b13be0f7ec48f8514e47322353e041365 |
|
01-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Add support for integral vertex attributes.
When a vertex shader input attribute is declared with an integral type
(e.g. ivec4), we need to ensure that the generated vertex shader code
addresses the vertex attribute register using the proper register
type. (Previously, we assumed all vertex shader input attributes were
floating-point).
In addition, when uploading vertex data that was specified with
VertexAttribIPointer, we need to instruct the vertex fetch unit to
convert the data to signed or unsigned int, rather than float. And
when filling in the implied w=1 on a vector with less than 4
components, we need to fill it in with the integer representation of 1
rather than the floating-point representation of 1.
Fixes piglit tests vs-attrib-{ivec4,uvec4}-precision.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c83bfeabc6af82f061d53b8b5923ee26f14efb58 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move index buffer upload to emit() time.
It's consumed by the brw_emit_index_buffer() code at emit() time.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 78a010127f3eb600fb7b145bc562b62a77af5a34 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Do a hack job of merging VB prepare()/emit() together.
I don't really want to touch this impenetrable code in this series, so
just call the one function from the other, since no other atom cares
about them.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| eaf4d3e6e2493a6e0b20d1205a5fb33ce500c9c2 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove the validated BO list, now that it's unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ddc348d83eff8c12ff0e6c245c32fa65120e7f4a |
|
27-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Make sure to upload the data for a collection of Stride == 0 arrays.
Commit d631c19db47181129811080bfa772b210d762d4d avoided this problem
by forcing the driver to get the min/max index, but that commit was
broken, so just fix the driver problem (confusion between "do I need
to upload any data?" and "do I need the index bounds in order to
upload any data?").
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 0d636213d491f88726155e12c3b445a88e0f1cd8 |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Only map the necessary buffer range in brw_prepare_indices
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 28249bd260f4c52badf3eb61ade2744604b21bca |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Eliminate dd_function_table::MapBuffer
Replace all calls to dd_function_table::MapBuffer with appropriate
calls to dd_function_table::MapBufferRange, then remove all the cruft.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b2184da684fc20849b5e6e554f0a0f92d2872ce9 |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Fix incorrect access parameter passed to MapBuffer
The code previously passed GL_DYNAMIC_DRAW for the access parameter.
By inspection, I believe that all drivers would treat this as
GL_READ_WRITE because it's not GL_READ_ONLY and it's not
GL_WRITE_ONLY.
It appears the i965 code wants GL_WRITE_ONLY (it's about to write a
bunch of data in, never read data), while the arrayelt code is
GL_READ_ONLY (just dereffed as arguments to CALL_Whatever*v).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Keith Whitwell <keithw@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 12d924c5ae14a1c6a05a3dcae29b77e7668e227d |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Remove target parameter from dd_function_table::MapBuffer
No driver used that parameter, and most drivers ended up with a bunch
of unused-parameter warnings because it was there.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 56f0c00f125ee75caeadc1c9e8cab8a488635e5e |
|
22-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Remove target parameter from dd_function_table::UnmapBuffer
No driver used that parameter, and most drivers ended up with a bunch
of unused-parameter warnings because it was there.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 797522f1c9c0f4aa75e4c9c854e79c44ed374169 |
|
13-Jul-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename CMD_VERTEX_(BUFFER|ELEMENT) to 3DSTATE_VERTEX_...S.
This makes our code use the same names as the documentation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a5a36d9b158a317daa1cf10a6b6ed2bed6b22750 |
|
11-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't try to continue space before the start of a VBO.
This loop is trying to see if all the buffers to be uploaded happen to
be the same increment from the start of the 3DSTATE_VERTEX_BUFFERS
currently loaded in the hardware. However, we might be at a smaller
offset than the previous set of VERTEX_BUFFERS, so we can't reuse
because that packet made the first entry be its starting offset (you
can't access outside the given bounds).
Fixes piglit ARB_vertex_buffer_object/elements-negative-offset.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5c2c60175d0e5da9b0e9688538b84dedf05107de |
|
11-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add missing state flag for vertex elements on current VS program.
Fixes a missing 3DSTATE_VERTEX_ELEMENTS on topogun.trace.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 4176025d463e7733dac19788b45b6472b65d62d4 |
|
08-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_FIXED vertex attributes.
This sadly requires work in the VS to rescale them, because the
hardware doesn't support this format natively.
Fixes arb_es2_compatibility-fixed-type and gtf/fixed_data_type.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 62b79b4bb9d8a4a8679c3d1e1f5455ce33d7b90a |
|
20-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Set Address Modify Enable in VERTEX_BUFFER on Ivybridge.
Otherwise, Ivybridge seems to ignore the newly supplied data, giving us
rubbish for vertices.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f703ba8c42e924ee6d5e4308c3888e434d8ba98c |
|
12-Apr-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
Revert "i965: Reinstate max-index paranoia"
This reverts commit b4cbd2b312d53a50603e2cda925711bc9def4517.
It looked like a safe sanity check. It missed the issue of the start of
the buffer not being at 0, but even that was not enough to explain why
setting the max vertex index caused glyphs to be dropped from the game
'Achron'.
Instead, the issue appears to be related to the use of the vertex bias
and so we would need to re-emit the max-index every time we adjusted the
bias, so re-emitting the relocations and defeating the original
optimisation.
Reported-and-tested-by: Thomas Jones <thomas.jones@utoronto.ca>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35163
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5ae1d195061b5f01d85b8f6d48d89d7995b07f4f |
|
09-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use ffs() on a 32-bit int value instad of ffsll().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9d31138f53c0bee9193af73850ab6febddd29f51 |
|
03-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Fix extending VB packets
Computation of the delta of this array from the last had a silly little
bug and ignored any initial delta==0 causing grief in Nexuiz and
friends.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1546291e5b8d3ac02f5bee38252f9d479bcf95cc |
|
03-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Align index to type size and flush if the type changes
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b93684f5f311f89c965960ab42bfea71a397b180 |
|
03-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Prevent using a zero sized (or of unknown type) vertex array
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 900a5c91eeb3acae7ee0ad331154531c4dba96e1 |
|
01-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Use negative relocation deltas to minimse vertex uploads
With relaxed relocation checking in the kernel, we can specify a
negative delta (i.e. pointing outside of the target bo) in order to fake
a range in a large buffer. We only then need to upload the elements used
and adjust the buffer offset such that they correspond with the indices
used in the DrawArrays.
(Depends on libdrm 0209428b3918c4336018da9293cdcbf7f8fedfb6)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9fa380ccdcf987430b9bff8e5216869e05b0aaea |
|
01-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Undo 'continuation of vb packets'
This breaks nexuiz for unknown reason; disable until a true fix can be
found.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 69b3f24658b74f15b622adda6464a6fcb87f4ee6 |
|
01-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Fix uploading of shortened vertex packets
... handle all cases and not just the interleaved upload.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 6ddfb322f58c7e00db73e25689ee55ffa1111bd9 |
|
24-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Upload all vertices used
... and take advantage of start_vertex_bias to trim to [min_index,
max_index] where possible (i.e. when we need to upload all arrays).
Fixes half_float_vertex(misc.fillmode.wireframe)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34595
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5ce0f7f10908a0636900bae783cb426a6c607673 |
|
24-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Reset the buffer offset after releasing reference to packed upload
Fixes oglc/vbo(basic.bufferdata)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 135ccb2daecb7792dfb17e66ab0acb79a97f78c8 |
|
24-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Unmap the correct pointer after discontiguous upload
Fixes piglit/fbo-depth-sample-compare:
==14722== Invalid free() / delete / delete[]
==14722== at 0x4C240FD: free (vg_replace_malloc.c:366)
==14722== by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695)
==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd
==14722== at 0x4C244E8: malloc (vg_replace_malloc.c:236)
==14722== by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256)
==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3adc108b4a7460ef5d92c0f5f0ee655d4ca6cb32 |
|
22-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Trim the interleaved upload to the minimum number of vertices
... should have no impact on a properly formatted draw operation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b4cbd2b312d53a50603e2cda925711bc9def4517 |
|
22-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Reinstate max-index paranoia
Don't trust the applications not to reference beyond the end of the
vertex buffers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3377faffcdc7227bd27381894c87c7600547744f |
|
22-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Zero the offset into the vbo when uploading non-interleaved
Fixes regression from 559435d9152acc7162e4e60aae6591c7c6c8274b.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9e872a5865c66ed0a518dd1c6c54e72f3afa71f1 |
|
22-Feb-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.
Fixes regression in scissor-stencil-clear and 5 other tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a43f20e0699f0b60d1e1e3e7a0693192f8d2895d |
|
21-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Remove spurious duplicate ADVANCE_BATCH
... a leftover from a bad merge.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c625aa19cb53ed27f91bfd16fea6ea727e9a5bbd |
|
18-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: extend current vertex buffers
If the next vertex arrays are a (discontiguous) continuation of the
current arrays, such that the new vertices are simply offset from the
start of the current vertex buffer definitions we can reuse those
defintions and avoid the overhead of relocations and invalidations.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a07e4811794051dc65187d17b7f85e340e61854e |
|
18-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Use specified alignment for writes into the upload buffer
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d9e591391d490c83ce301aa568a2e0afe4cc3c0a |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Clean up brw_prepare_vertices()
Use a temporary glarray variable to replace the numerous input->glarray.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3630d5b69afcecc3142d2c4897835175886f4bd8 |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: combine short memcpy using a temporary allocated buffer
Using a temporary buffer for large discontiguous uploads into the common
buffer and a single buffered upload is faster than performing the
discontiguous copies through a mapping into the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| dfc6c96e5c470f6136cad26b753c024538fd09a0 |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: upload normal arrays as interleaved
Upload the non-vbo arrays into a single interleaved buffer object, and
so need to just emit a single vertex buffer relocation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 94d73d700e804ce78c214c58e84382c81dcb8280 |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: interleaved vbo
If the user passed in several arrays interleaved in the same vbo, only
emit a single vertex buffer and relocation.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 559435d9152acc7162e4e60aae6591c7c6c8274b |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: emit one vb packet per vbo
Track reuse of the vertex buffer objects and so minimise the number of
vertex buffers used by the hardware (and their relocations).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| abb51097566c401344b22a7ee9d699f002a1977f |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: upload transient indices into the same discontiguous buffer
As we now pack the indices into a common upload buffer, we can reuse a
single CMD_INDEX_BUFFER packet and translate each invocation with a
start vertex offset.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 60bb3e5614a533ff886bf1ddb6341ff34f75c886 |
|
20-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: suppress repeat-emission of identical vertex elements
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8a9e67b8df9836408270a4bc3660ec45b622ae56 |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Buffered upload
Rather than performing lots of little writes to update the common bo
upon each update, write those into a static buffer and flush that when
full (or at the end of the batch). Doing so gives a dramatic performance
improvement over and above using mmaped access.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| abb37861d9f3310fe2d16194d893682092f41087 |
|
08-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Combine vb upload buffer with the general upload buffer
Reuse the new common upload buffer for uploading temporary indices and
rebuilt vertex arrays.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e476e122207e6195a16a8c7d2cab90eeba227934 |
|
08-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: Pack dynamic draws together
Dynamic arrays have the tendency to be small and so allocating a bo for
each one is overkill and we can exploit many efficiency gains by packing
them together.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 45ba7afbd15b28ffd61548ee46334ff4527a7cde |
|
29-Jan-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Trim the trailing NOOP from 3DSTATE_INDEX_BUFFER
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 43873b53c4d15f10f0321c770b1b8bd537cc226d |
|
12-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't rebase the index buffer to min 0 if any arrays are in VBOs.
There was a check to only do the rebase if we didn't have everything
in VBOs, but nexuiz apparently hands us a mix of VBOs and arrays,
resulting in blocking on the GPU to do a rebase.
Improves nexuiz 800x600, high-settings performance on my Ironlake 41%
(+/- 1.3%), from 14.0fps to 19.7fps.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 527a9a4de218cae89d7faf92788f88ce1f9387b6 |
|
22-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use intel->gen >= 6 instead of IS_GEN6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f5bd48cf673456ffea730f28c9b95c6883399162 |
|
14-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use R16G16B16A16_FLOAT for 3-component half-float.
The RGBX version isn't supported as a vertex input type, but since we
force the last channel's value anyway, this should be fine. The only
potential risk I see is in the limiter on VBO reads past the end of
the buffer forcing the whole vertex to 0 when the A channel lands past
the end.
Fixes piglit draw-vertices-half-float.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| bb35000b4b6dfe60048b2f5d60bc102c4a7fd791 |
|
05-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-kernel-exec-fencing support.
Shaves 60k off the driver from removing the broken spans code. This
means we now require 2.6.29, which seems fair given that it's a year
old and we've removed support for non-KMS already in the last release
of 2D.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1489f108f4a9b53b42d3d4123da64ccdb7aafdde |
|
21-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix up some Sandybridge define checks for the structure rebase.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ff3997904ab988824e744fdbecde6eb79d9bf40f |
|
04-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Reconnect the index/vertex setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 298be2b028263b2c343a707662c6fbfa18293cb2 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace the _mesa_*printf() wrappers with the plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 32f2fd1c5d6088692551c80352b7d6fa35b0cd09 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace _mesa_malloc, _mesa_calloc and _mesa_free with plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 96f2f0daeadd5bd2d8433e31a1b122c2bd709390 |
|
18-Jan-2010 |
Dave Airlie <airlied@linux.ie> |
i965: add support for ARB_half_float_vertex
enables the extension on i965 and adds support to the draw upload for
the vertex format.
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5203b7227ccb6b618fa42f08434d4a3cf123dca2 |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop batchbuffer cliprect_mode tracking
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c67bb15d4e3da430d511444bd7d159ccb0c84b73 |
|
29-Dec-2009 |
Vinson Lee <vlee@vmware.com> |
intel: Silence compiler warnings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-GEM support.
This really isn't supported at this point. GEM's been in the kernel for
a year, and the fake bufmgr never really worked.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3d36d6b4cf735e93a6ae5eadf28e671252fb5303 |
|
13-Nov-2009 |
Eric Anholt <eric@anholt.net> |
Merge remote branch 'origin/mesa_7_6_branch'
|
| 5f305b1db925c819ddeb29a75f6fbad6500a2d11 |
|
11-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix VBO last-valid-offset setup on Ironlake.
Instead of doing math based on the (broken for VBO && offset != 0)
input->count number, just use the BO size. Fixes assertion failure in ETQW.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e9b17d6477f99838fc7f261ea1b8d47eea12f42f |
|
27-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: be clear that the Fallback field is a boolean, not a bitfield
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 755161b88843f3cfead9a02e076d1a04687d9082 |
|
27-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()"
This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c.
It turns out the i965 driver uses the intel->Fallback field as a boolean,
not as a bitmask. The intelFallback() function is a no-op in the i965
driver. It would have been nice if there were some comments about this.
I'll fix that next...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 43dc91f8bbb69499a6a0326a78e434b313f73c2c |
|
27-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: be clear that the Fallback field is a boolean, not a bitfield
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f9e334cb32152fd342ac6b1dd4776215af6e1d49 |
|
27-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()"
This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c.
It turns out the i965 driver uses the intel->Fallback field as a boolean,
not as a bitmask. The intelFallback() function is a no-op in the i965
driver. It would have been nice if there were some comments about this.
I'll fix that next...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ab9d1011f5549502a4b960c2067cde69856a2719 |
|
23-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
|
| 8810b8f67135185d1044746bb861fe2ff997626c |
|
23-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix hacked Fallback usage in brw_prepare_vertices()
Setting intel->Fallback = 1 clobbered any fallback state that was already
set. Not sure where this hack originated (the git history is a little
convoluted). Define and use a new BRW_FALLBACK_DRAW bit instead. This
shouldn't break anything and could potentially fix some bugs (but no
specific ones are known).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ce3801ab87ef6eb29e5b81c2acfdd102f7b9c0ae |
|
14-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
|
| f3be27c0cf8a4c47230f31d9d66bde7340ffb204 |
|
11-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix the last valid address setting for the index buffer.
Again, last valid address, not first invalid address. Fixes regression
in 255e5be265133280293bbfd8b2f9b74b2dec50bb that the kernel now catches
and caused piglit draw_elements_base_vertex to fail.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a82da7fa263c7fb6b902285994136890e6dc3278 |
|
11-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix the bounds emitted in the vertex buffer packets.
It's the address of the last valid byte, not the address of the first
invalid byte.
This should also fix problems with rendering with the new sanity checks in
the kernel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7bf63473623e01933adc0e8f4464eda8f2860564 |
|
09-Sep-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
|
| 0c309bb494b6ee1c403442d1207743f749f95b6e |
|
09-Sep-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
Conflicts:
Makefile
configs/default
progs/glsl/Makefile
src/gallium/auxiliary/util/u_simple_shaders.c
src/gallium/state_trackers/glx/xlib/xm_api.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/intel/intel_context.h
src/mesa/drivers/dri/intel/intel_pixel.c
src/mesa/drivers/dri/intel/intel_pixel_read.c
src/mesa/main/texenvprogram.c
src/mesa/main/version.h
|
| b2de02852381dccea6cb9bdca049d5629cca80ef |
|
08-Sep-2009 |
Brian Paul <brianp@vmware.com> |
i965: #include clean-ups
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 00aac1d29a7ca06d1f1ac429371d9a6774873389 |
|
08-Sep-2009 |
Brian Paul <brianp@vmware.com> |
i965: use _mesa_is_bufferobj()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 8de625c7cf639c583e8bf43acb1214010989bb64 |
|
08-Sep-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix incorrect test for vertex position attribute
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 63b3fa2bcecc75a116ce651da435d205ccd43584 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Assert that the offset in the VBO is below the VBO size.
This avoids sending a bad buffer address to the GPU due to programmer error,
and is permitted by the ARB_vbo spec. Note that we still have the opportunity
to dereference past the end of the GPU, because we aren't clipping to a
correct _MaxElement, but that appears to be harder than it should be. This
gets us the 90% solution.
Bug #19911.
(cherry picked from commit d7430d942f6c7950a92367aeb13b80cf76ccad78)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9eca0e5350377148976e0d1200f98bd20ac28197 |
|
30-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i965: Don't emit bad packets when no VBs are referenced.
It appears that sometimes Mesa (and I suppose a VS could as well) emits
a program which references no vertex data, and thus we end up with
nr_enabled == 0 even though some VBs are enabled. We'd end up emitting
VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs.
Bug #22945 (wine with an uncompiled VS)
(cherry picked from commit d1fbfd0f962347e4153db3852292d44de5aea863)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7e26bdb849b75f4aeb69cf8b1fdffbc461265490 |
|
03-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Calculate enabled[] and nr_enabled once and re-use the values.
The code duplication bothered me.
(cherry picked from commit 9b9cb30d128fc5f1ba77287696ecd508e640efde)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 213ac4bb5de1cef601e0677ef2e5ca1779851e28 |
|
24-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set the max index buffer address correctly according to the docs.
It's the last addressable byte, not the byte after the end of the buffer.
(cherry picked from commit b72dea5441e8e9226dabf1826fa3bc129c7bc281)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| cab307ce6b32d2ffdb0eb3bb5bae93c6fb9305fb |
|
15-May-2009 |
Brian Paul <brianp@vmware.com> |
i965: rename var: s/tmp/vs_inputs/
(cherry picked from commit 840c09fc71542fdfc71edd2a2802925d467567bb)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b9789948e0b5c5fad7952ea5b731c675d50a4f58 |
|
15-Aug-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: disable bounds checking on arrays with stride 0
if stride is 0 we cannot use count as max index for bounds checking,
since the hardware will simply return 0 as data for indices failing
bounds check. If stride is 0 any index should be valid hence simply
disable bounds checking in this case.
This fixes bugs introduced with e643bc5fc7afb563028f5a089ca5e38172af41a8.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 255e5be265133280293bbfd8b2f9b74b2dec50bb |
|
11-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Avoid re-uploading the index buffer when we don't need to.
No performance difference proven at 95% confidence with my GLSL demo (n=10).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e643bc5fc7afb563028f5a089ca5e38172af41a8 |
|
11-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use _MaxElement instead of index-calculated min/max for VBO bounds.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d7430d942f6c7950a92367aeb13b80cf76ccad78 |
|
04-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Assert that the offset in the VBO is below the VBO size.
This avoids sending a bad buffer address to the GPU due to programmer error,
and is permitted by the ARB_vbo spec. Note that we still have the opportunity
to dereference past the end of the GPU, because we aren't clipping to a
correct _MaxElement, but that appears to be harder than it should be. This
gets us the 90% solution.
Bug #19911.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d1fbfd0f962347e4153db3852292d44de5aea863 |
|
30-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i965: Don't emit bad packets when no VBs are referenced.
It appears that sometimes Mesa (and I suppose a VS could as well) emits
a program which references no vertex data, and thus we end up with
nr_enabled == 0 even though some VBs are enabled. We'd end up emitting
VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs.
Bug #22945 (wine with an uncompiled VS)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9b9cb30d128fc5f1ba77287696ecd508e640efde |
|
03-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Calculate enabled[] and nr_enabled once and re-use the values.
The code duplication bothered me.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b72dea5441e8e9226dabf1826fa3bc129c7bc281 |
|
24-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set the max index buffer address correctly according to the docs.
It's the last addressable byte, not the byte after the end of the buffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 840c09fc71542fdfc71edd2a2802925d467567bb |
|
15-May-2009 |
Brian Paul <brianp@vmware.com> |
i965: rename var: s/tmp/vs_inputs/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e7aef006e50d0b859c621267af8376f5a0f43445 |
|
06-Apr-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use GTT maps when available to upload vertex arrays and system VBOs.
This speeds up OA on my GM45 by 21% (more than the original CPU cost of
the upload path). We might still be able to squeeze a few more percent out
by avoiding repeatedly mapping/unmapping buffers as we upload elements into
them.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 36daee1c7bec44b9d3641f056c84b3b2f39fabd9 |
|
26-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: asst. casts to silence warnings
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| dab586b0755bffa7c4da0fdc571e0f504f4066c2 |
|
23-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: enable GL_EXT_vertex_array_bgra
Simply a matter of choosing the right surface/vertex format for GLubyte/GL_BGRA arrays.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2fc9d671e0be77676818da51cd3b35b52af79421 |
|
12-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix VB refcount leak on aperture overflow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 |
|
24-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix check_aperture calls to cover everything needed for the prim at once.
Previously, since my check_aperture API change, we would check each piece of
state against the batchbuffer individually, but not all the state against the
batchbuffer at once. In addition to not being terribly useful in assuring
success, it probably also increased CPU load by calling check_aperture many
times per primitive.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c157cfc6376f7469ab272b18868183e5ff9ac754 |
|
07-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Add ARB_occlusion_query support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 94d3a30df759bb7c2724fdcee9e89a350d3a4d8b |
|
08-Oct-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Fix a potential assertion failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d533da2db873942b3f8676a754b8be3c9718bedf |
|
24-Sep-2008 |
Eric Anholt <eric@anholt.net> |
i965: Cope with batch getting flushed in the middle of batchbuffer emits.
This isn't required for GEM (at least, yet), but the check_aperture code
for non-GEM results in batch getting flushed during emit. brw_state_upload
restarts state emits, but a bunch of the state emit functions were assuming
that they would be called exactly once, after prepare and before new_batch.
Bug #17179.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 35fd72756a05463568d94862f4fcd234903e1204 |
|
08-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track move of bo_exec from drivers to bufmgr.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 687cd467b3461691a6fd03d3bc38c01ed79c06fd |
|
21-Aug-2008 |
Eric Anholt <eric@anholt.net> |
i965: use dri_bo_subdata in vertex upload to get pwrite used.
Otherwise, we would ping-pong objects to GTT and back as we did pwrite on
indices (flushed and mapped to GTT) and mapped for vertices (moved back to
CPU domain).
Fixes bug #17180.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 407ce3da3c53c9ebba0fbf827d7b0f610122d44b |
|
11-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| dbf3c5247c90bd35c0b2002e3b972a2dd4c8b130 |
|
04-Jun-2008 |
Keith Packard <keithp@keithp.com> |
Merge commit 'origin/master' into drm-gem
Conflicts:
src/mesa/drivers/dri/common/dri_bufmgr.h
src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c
src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h
src/mesa/drivers/dri/intel/intel_ioctl.c
|
| 4b5b008d54e86ac4f0a2176429d062100978ca8c |
|
03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ab50ddaa9173ae108833db0edb209045788efc41 |
|
07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 17adf04e5c1da72a51815f3fdb9de2f3a8149c1a |
|
06-May-2008 |
Dave Airlie <airlied@panoply-rh.(none)> |
i965: fix googleearth in classic mode.
In classic mode googleearth triggered a case where vbos weren't getting accounted properly.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| fda4895d26eec6d810da51a6c023a5459230ff6a |
|
18-Apr-2008 |
Dave Airlie <airlied@panoply-rh.(none)> |
i965: fix vb aperture space check
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e92e3848e7c8c1481e785973d8609072f2f5db21 |
|
18-Apr-2008 |
Dave Airlie <airlied@panoply-rh.(none)> |
965: fix vb upload size check
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
|
17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 2abcc512a3ce81bc11ff2b45a2208d3400a2385d |
|
03-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Convert brw_draw_upload to managing dri_bos, not gl_buffer_objects.
This helps us avoid a bunch of mess with gl_client_arrays that we filled
with unused data and confused readers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 0907c639c8509cda4507b28c1399813a09a81c5e |
|
02-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove dead structure in brw_draw_upload.c.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 7b8892f50482359625e36005c2b460a921ff796c |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Move temporary vbo array storage into the function using it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c86ec87830dba86b257ccddc832b746af955eb05 |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove dead brw_vertex_element members.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 4e13067d0f95b280da3fef2deb7e59466ea73818 |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Add a wrapper around interleaved copy_array_to_vbo_array for profiling.
If compiled with optimization, it shouldn't appear at all, and helps me for
now.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| df44fefced61d35c302907cb716fa0f9337ae526 |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Avoid overloaded use of the term 'input' for clarity.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 931685e243af52271d4cdc0ddc8ea153036dee42 |
|
22-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Replace VEP/VBP state structures with inline batch emits.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 540faf5f91057ef311999afc5a6366bebe7dec33 |
|
11-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove an open-coded memcpy.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a04b632350e5d0e9994fc667afc59407a39da0ba |
|
10-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Add more cliprect modes to cover other meanings for batch emits.
The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:
- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
(copybuffers, clears).
All callers should now be fixed to use one of these states for any batchbuffer
emits. Thanks to Keith Whitwell for pointing out the failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5a49e84fcd858a1ad9c0ad839ccbe93504593cd0 |
|
09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Clarify a bit of index buffer upload code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| bea6b5fe5aa3138cec8d057766ae48da4aa57dee |
|
20-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Enable EXT_framebuffer_object.
To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| c0b4257aa9ba783674ccf7162799385734dff211 |
|
16-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Move to using shared texture management code.
This removes the delayed texture upload optimization from 965, in exchange for
bringing us closer to PBO support. It also disables SGIS_generate_mipmap,
which didn't seem to be working before anyway, according to the lodbias demo.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 3fe9d5cbb7c680c6fb88a2eba678b28a2a06949e |
|
15-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Merge intel_buffer_objects to shared.
965 gains fixed TTM typing of the buffer object buffers and unused PBO
functions, and 915 gains buffer size == 0 fixes from 965.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 84a076079d3a038115a39b1c283b46a574591e07 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] warnings cleanup
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 77e0523fb7769df4bf43747e136b1653b2421b97 |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace various alignment code with a shared ALIGN() macro.
In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 0fc9efd8f0b1b6c4e3525a50e3478e5aef72531a |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
Replace bmBufferOffset usage in batchbuffer setup with OUT_RELOC.
This is in preparation for 965 TTM.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| e886ae4c58bc98897d6901e3f30deea008bc7f8a |
|
28-Sep-2007 |
Eric Anholt <eric@anholt.net> |
Revert "WIP 965 conversion to dri_bufmgr."
This reverts commit b2f1aa2389473ed09170713301b042661d70a48e.
Somehow I ended up with my branch's save-this-while-I-work-on-master commit
actually on master.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b2f1aa2389473ed09170713301b042661d70a48e |
|
27-Sep-2007 |
Eric Anholt <eric@anholt.net> |
WIP 965 conversion to dri_bufmgr.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 38c30a81844214b030c9c637f9cf97bd2bf19cde |
|
26-Sep-2007 |
Eric Anholt <eric@anholt.net> |
[965] Remove AUB file support.
This code existed to dump logs of hardware access to be replayed in simulation.
Since we have real hardware now, it's not really needed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| ea07a0df9a2f689b8f5acaf92c40bbbd602cab3c |
|
14-Sep-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: align the address of the first element within
the index buffer. (fix#11910)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| b59657ad965f9471574e914b861bb1d2a17d772e |
|
02-Feb-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Merge branch 'vbo-0.2'
Conflicts:
src/mesa/main/texcompress_s3tc.c
src/mesa/tnl/t_array_api.c
|
| 47d463e954efcd15d20ab2c96a455aa16ddffdcc |
|
02-Feb-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Modify assert to reflect rebase criteria
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 5368ae5ec329ddad5963d55b17cd4eccbc83d32f |
|
01-Feb-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Correct usage/meaning of max_index parameter.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 893526b8a823fe1b88f2b46376155afb91c84016 |
|
30-Jan-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Use new rebase helper. Remove other rebase code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 869b8ad499717eda4a1be04de4e516134123402c |
|
21-Jan-2007 |
Eric Anholt <eric@anholt.net> |
Add _mesa_ffsll() for compatibility on OSes without ffsll(), and use it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 6a3fdc3a1ea6c306d9543791bf172dd1052d7382 |
|
16-Jan-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Merge branch 'master' of git+ssh://keithw@git.freedesktop.org/git/mesa/mesa into vbo-0.2
Conflicts:
src/mesa/array_cache/sources
src/mesa/drivers/dri/i965/brw_context.c
src/mesa/drivers/dri/i965/brw_draw.c
src/mesa/drivers/dri/i965/brw_fallback.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/i965/brw_vs_tnl.c
src/mesa/drivers/dri/mach64/mach64_context.c
src/mesa/main/extensions.c
src/mesa/main/getstring.c
src/mesa/tnl/sources
src/mesa/tnl/t_save_api.c
src/mesa/tnl/t_save_playback.c
src/mesa/tnl/t_vtx_api.c
src/mesa/tnl/t_vtx_exec.c
src/mesa/vbo/vbo_attrib.h
src/mesa/vbo/vbo_exec_api.c
src/mesa/vbo/vbo_save_api.c
src/mesa/vbo/vbo_save_draw.c
|
| f58ec215c5669f36c2649acc9cbeda7383b86879 |
|
21-Nov-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Gary Wong's fix for 64 bit cleanness of vertex program inputs bitmask.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| f2eb6434ab1cf72e938956c82d2f530368a6be4a |
|
31-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
cleanup code, compiles with vbo changes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| efef291dc71eb57f90785a26957f4b3e01733156 |
|
30-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
checkpoint - remove dead files, otherwise untested
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| a2c50b0f4ad16855cf8a2ff2ab4029342f4297dd |
|
13-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Upload of interleaved arrays currently assumes that position is the
first element in the interleaved group. Add a test to catch cases
where this isn't true and use per-array uploads instead. Fixes compiz
glitches on x64.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw_upload.c
|