bc7112746d4663b814aab018c8c1fb97af03fb42 |
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17-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Store texturing results into a vec4 temporary. The sampler appears to ignore writemasks (even when correcting the WRITEMASK_XYZW in brw_vec4_emit.cpp to the proper writemask) and just always writes all four values. To cope with this, just texture into a temporary, then MOV out into a register that has the proper number of components. NOTE: This is a candidate for stable branches. Fixes es3conform's shadow_execution_vert.test. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org> (cherry picked from commit f0dbd9255b5813d1567e1f09266f80e35dcbeb70)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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29bc8e7d8f166ae09edb8efda0b8c3bd8b7b7321 |
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17-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Set LOD to 0 for ordinary texture() calls. Previously it was left undefined, causing us to select a random LOD. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org> (cherry picked from commit aeff9a0d9889c4583e4f7fc89539380c1e6d043c)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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de150e24781cfb9f2f7e62355f3af68d23c681df |
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17-Jan-2013 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Create a 'lod_type' temporary for ir->lod_info.lod->type. This is purely a refactor. However, in a moment, we'll want to set lod_type to float for ir_tex, where ir->lod_info.lod is NULL. NOTE: This is a candidate for stable branches (for the next patch). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <idr@freedesktop.org> (cherry picked from commit 56ce55d198af65d4a9de7119eb9e2417296c54ea)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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cb415d4df644a8caffe861626dec5f7aa4cefa49 |
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02-Oct-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Fix unit mismatch in scratch base_offset parameter. move_grf_array_access_to_scratch() calculates scratch buffer offsets in bytes. However, emit_scratch_read/write() expects the base_offset parameter to be measured in OWords. As a result, a shader using a scratch read/write offset greater than zero (in practice, a shader containing more than one variable in scratch) would use too large an offset, frequently exceeding the available scratch space. This patch corrects the mismatch by removing spurious conversion from OWords to bytes in move_grf_array_access_to_scratch(). This is based on a patch by Paul Berry. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 46e529672bb124b78eb454cbf55c72074ef6d35c)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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f3d0daf7ea7e42ff9ce11e8bd6fba1059a2406e8 |
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26-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Index sampler program key data by linker-assigned index. Now that most things are based on the linker-assigned index, it makes sense to convert the arrays in the VS/WM program key as well. It seems silly to leave them indexed by texture unit. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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85e8e9e000732908b259a7e2cbc1724a1be2d447 |
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24-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use linker-assigned sampler IDs in instruction encoding. When assigning uniform locations, the linker assigns each sampler uniform a sequential numerical ID. gl_shader_program::SamplerUnits maps these sampler variable IDs to the actual texture units they reference (specified via glUniform1i). Previously, we encoded this mapping in the SEND instruction encoding: the "sampler" was the texture unit number, and the binding table index was SURF_INDEX_TEXTURE(the texture unit number). This unfortunately meant that whenever the application changed the value of a sampler uniform, we had to recompile the shader to change the SEND instructions. This was horrible for the game Cogs, which repeatedly switches between using texture unit 0 and 1. It also made fragment shader precompiles useless: we'd do the precompile at glLinkShader() time, before the application called glUniform1i to set the sampler values. As soon as it did that, we'd have to recompile, wasting time and space in the program cache. This patch encodes the SamplerUnits indirection in the binding table, sampler state, and sampler default color tables. Instead of baking the texture unit number into the shader, we bake in the sampler variable ID assigned by the linker. Since those never change, we don't need to recompile programs on uniform changes. This does mean that the tables now depend on the linked shader program being used for rendering, rather than simply representing all available texture units. This could cause an increase in state emission. Another plus is that the sampler state and sampler default color tables are now compact: we only emit as many entries as there are sampler uniforms, with no holes in the table since the new sampler IDs are sequential. Previously we had to emit a full 16 entries every time, since the tables tracked the state of all active texture units. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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96a22f35830859c938901ecbb4817aa8e1a9dff9 |
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21-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Rename "sampler" to "texunit" in texturing code. The number we're passing around is actually the ID of the texture unit, as opposed to the numerical value our of sampler uniforms. Calling it "texunit" clarifies this slightly. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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e119f98472f6ceb03ffd564eb0398233e7b81437 |
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27-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for copying user edge flags. Fixes the glsl skinning demo regression since changing to the new GLSL compiler, and is part of fixing piglit gl-2.0-edgeflag. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50079 NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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04871058eb01c5b51a0180055e7dbdc967f56604 |
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25-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for loading uniform buffer variables as pull constants. Unlike the FS side in the previous commit, this does variable indexing just fine, using the same code as we used for other variable-indexed pull constants. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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bb020d09c382285210a5aebe412ddabfad19e4a0 |
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25-Jun-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add a surface index to VS_OPCODE_PULL_CONSTANT instructions. Similar to the previous commit for the fragment shader, now we have a buffer index and an offset. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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2ea3ab14f2182978f471674c9dfce029d37f70a7 |
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10-Jul-2012 |
Eric Anholt <eric@anholt.net> |
glsl: Add a "ubo_load" expression type for fetches from UBOs. Drivers will probably want to be able to take UBO references in a shader like: uniform ubo1 { float a; float b; float c; float d; } void main() { gl_FragColor = vec4(a, b, c, d); } and generate a single aligned vec4 load out of the UBO. For intel, this involves recognizing the shared offset of the aligned loads and CSEing them out. Obviously that involves breaking things down to loads from an offset from a particular UBO first. Thus, the driver doesn't want to see variable_ref(ir_variable("a")), and even more so does it not want to see array_ref(record_ref(variable_ref(ir_variable("a")), "field1"), variable_ref(ir_variable("i"))). where a.field1[i] is a row_major matrix. Instead, we're going to make a lowering pass to break UBO references down to expressions that are obvious to codegen, and amenable to merging through CSE. v2: Fix some partial thoughts in the ir_binop comment (review by Kenneth) Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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54c045b93cd205bcf031e70d65238d60bfc07da4 |
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05-Aug-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Don't clobber sampler message MRFs with subexpressions. See the preceding commit for a description of the problem. NOTE: This is a candidate for stable release branches. v2: Use a separate dPdx variable rather than reusing the lod src_reg. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52129 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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25ca9cc8236845a4be32a6f39b4a6d1664d4b403 |
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04-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Move the other two src_reg/dst_reg constructors to brw_vec4.cpp. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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11a7b93592c22c8165f8fde6395f76778fca452e |
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14-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Add support for ir_unop_f2u to i965 backend. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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05790746df077183d6c3caf87ca2d276a60302a8 |
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07-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable the GL_ARB_shader_bit_encode extension. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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cb18472eca9910e7a4222ebc1b6b1b66869f5b53 |
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04-Jun-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Fix texelFetchOffset() on pre-Gen7. Commit 4650aea7a536ddce120576fadb91845076e8e37a fixed texelFetchOffset() on Ivybridge, but didn't update the Ironlake/Sandybridge code. +18 piglits on Sandybridge. NOTE: This and 4650aea7a536ddce are both candidates for stable branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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aa02884c4fdcbc20cf7ac89ec50f9d6c8d1e1682 |
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11-May-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix up swizzle for dereference_array of matrices. Fixes assertion failure in piglit: vs-mat2-struct-assignment.shader_test vs-mat2-array-assignment.shader_test Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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4650aea7a536ddce120576fadb91845076e8e37a |
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17-Apr-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix texelFetchOffset() It appears that when using 'ld' with the offset bits, address bounds checking happens before the offset is applied, so parts of the drawing in piglit texelFetchOffset() with a negative texcoord go black.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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e568b00562cf38afd779560c7431a94672531e95 |
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09-Feb-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix swizzles for system values such as gl_InstanceID. visit(ir_variable *) sets dst_reg::writemask to the appropriate channel for system values. Unfortunately, visit(ir_dereference_variable *) then calls swizzle_for_size, which for a float, sets the swizzle to .x. This works for gl_VertexID, since we store it in the .x component (see brw_draw_upload.c:732 - VID), but fails for gl_InstanceID (IID) since we store it in the .y channel. To fix this, avoid calling swizzle_for_size on ir_var_system_values. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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f0cecd43d6b6d3f5def3fd43b9c95baaf3be9b16 |
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13-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Move VUE map computation to once at VS compile time. With this and the previous patch, 640x480 nexuiz is running 0.169118% +/- 0.0863696% faster (n=121). On a VS state change microbenchmark, performance is increased 8.28645% +/- 0.460478% (n=52). v2: Fix CACHE_NEW_VS comment. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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9f3d3216cf25d8ffed4d72fbce6feacbc2990e4b |
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13-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Make the userclip flag for the VUE map come from VS prog data. This reduces recomputation of state based on non-clipping-related transform changes, and is a step toward removing VUE map recomputation. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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9195191e50429d9cf25e6498f9fb108758ac2be6 |
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27-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Avoid allocating registers in to the gen7 MRF hack region. This is the corresponding fix to the previous one for the FS, but I don't have a particular test for it. NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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e2274aa7398d6d710683c1a2518353750700bcc0 |
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20-Jan-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/vs: Fix bogus assertion in emit_block_move() i965 processes assignments of whole structures using vec4_visitor::emit_block_move, a recursive function which visits each element of a structure or array (to arbitrary nesting depth) and copies it from the source to the destination. Then it increments the source and destination register numbers so that further recursive invocations will copy the rest of the structure. In addition, it sets the swizzle field for the source register to an appropriate value of swizzle_for_size(...) for the size of each element being copied, so that later optimization passes won't be fooled into thinking that unused vector elements are live. This all works fine. However, emit_block_move also contains an assertion to verify, before setting the swizzle field for the source register, that the source register doesn't already contain a nontrivial swizzle. The intention is to make sure that the caller of emit_block_move hasn't already done some swizzling of the data before the call, which emit_block_move would then counteract when it overwrites the swizzle field. But the assertion is at the lowest level of nesting of emit_block_move, which means that after the first element is copied, instead of checking the swizzle field set by the caller, it checks the swizzle field used when moving the previous element. That means that if the structure contains elements of different vector sizes (which therefore require different swizzles), the assertion will erroneously fire. This patch moves the assertion from emit_block_move to the calling function, vec4_visitor::visit(ir_assignment *). Since the caller is non-recursive, the assertion will only happen once, and won't be fooled by emit_block_move's modification of the swizzle field. This patch also reverts commit fe006a7 (i965/vs: Fix swizzle related assertion), which attempted to fix the bug by making the assertion more lenient, but only worked properly for structures, arrays, and matrices in which each constituent vector is the same size. This fixes the problem described in comment 9 of https://bugs.freedesktop.org/show_bug.cgi?id=40865. Unfortunately, it doesn't fix the whole bug, since the test in question is also failing due to lack of register spilling support in the VS. Fixes piglit test vs-assign-varied-struct. No piglit regressions on Sandy Bridge. This is a candidate for the 8.0 release branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40865#c9 Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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3353626a6a2cc20301c65f3f6c1c5beb80721181 |
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18-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Enable workaround-free math on gen7. This is similar to a commit that did the same for the FS. Shaves several more instructions off of the VS in Lightsmark, but no statistically significant performance difference (n=5). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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1fde76b8771350933d0a0b562ff1bd91e8340ac5 |
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18-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Use the embedded-comparison SEL on gen6+, like the FS does. Shaves a few instructions off of the VS in Lightsmark, but no statistically significant performance difference on gen7 (n=5). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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2e712e41db0c0676e9f30fc73172c0e8de8d84d4 |
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18-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Take attributes into account when deciding urb_entry_size. Both the VF and VS share space in the URB. First, the VF stores attributes (shader inputs) there. The VS then reads the attributes, executes, and reuses the space to store varyings (shader outputs). Thus, we need to calculate the amount of URB space necessary for inputs, outputs, and pick whichever is greater. The old VS backend correctly did this (brw_vs_emit.c:408), but the new VS backend only considered outputs. Fixes vertex scrambling in GLBenchmark PRO on Ivybridge. NOTE: This is a candidate for the 8.0 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41318 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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7f278e15ad271daaa08dd2fef84cca5e344d5771 |
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12-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix leak of an empty hash_table structure per compile. This statement got duplicated above, probably in a rebase resolution, so we never freed the extra one. NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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2c623c2be529edc974ca293f3c71929c639ec0c9 |
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06-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/vs: Try to emit more components of constant vectors at once. We were naively emitting each component at a time, even if we were emitting the same value to multiple channels. Improves on a codegen regression from the old VS to the new VS on some unigine shaders (because we emit constant vecs/matrices as immediates instead of loading them as push constants, so we had over 4x the instructions for using them). shader-db results: Total instructions: 58594 -> 58540 11/870 programs affected (1.3%) 765 -> 711 instructions in affected programs (7.1% reduction)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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fbbbc8c04e2462a0ae272d81e61eee5f85f08aa6 |
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03-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Use the proper dimensionality for the sampler result register. textureSize() returns an int, ivec2, or ivec3, but never an ivec4. Creating the destination register as an ivec4 triggered later failures, even though the register did hold the proper values. For example, piglit test vs-textureSize-compare calls textureSize on a 2D texture and compares the result to an expected value. Unfortunately, our generated code also tried to compare the third and fourth components which were undefined, and failed. Fixes piglit test vs-textureSize-compare as well as 19 subcases of oglconform's glsl-bif-tex-size test. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44339 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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c82c24b18bb78d500db3c0481e10c58583fd3160 |
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30-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Silence gcc warning about uninitialized "inst" in assert() case.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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8e34021099527868097b2c877fc32f29aa4d7bb6 |
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07-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement EXT_texture_swizzle support for VS texturing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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328b693a199a67ce3a17d258f34d7bfd26790871 |
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12-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Add support for texel offsets. The visit() half computes the values to put in the header based on the IR and simply stuffs that in the vec4_instruction; the emit() half uses this to set up the message header. This works out well since emit() can use brw_reg directly and access individual DWords without kludgery. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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d93aa54d2dea79d8216e10b6bbbb00b0c8443dc2 |
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26-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement vec4_visitor::visit(ir_texture *). This translates the GLSL compiler's IR into vec4_instruction IR, generating code to load coordinates, LOD info, shadow comparitors, and so on into the appropriate message registers. It turns out that the SIMD4x2 parameters are identical on Gen 5-7, and the Gen4 code is similar enough that, unlike in the FS, it's easy enough to support all generations in a single function. v2: Load zeros for missing coordinates (fixing vs-texelFetch-sampler1D and 2D on G45), and fix G45 message length for shadow comparisons. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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1c65abb211e6a3df8c46180ae3242486ee97dc8d |
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09-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for gl_VertexID and gl_InstanceID. The compiler setup for these VF-uploaded attributes looks a little cheesy with mixing system values and real VBO-sourced attributes. It would be nice if we could just compute the ATTR[] map to GRF index up front and use it at visit time instead of using ir->location in the ATTR file. However, we don't know the reg_offset at visit(ir_variable *) time, so we can't do the mapping that early. Fixes piglit vertexid test. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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29e2bc8b13be0f7ec48f8514e47322353e041365 |
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01-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Add support for integral vertex attributes. When a vertex shader input attribute is declared with an integral type (e.g. ivec4), we need to ensure that the generated vertex shader code addresses the vertex attribute register using the proper register type. (Previously, we assumed all vertex shader input attributes were floating-point). In addition, when uploading vertex data that was specified with VertexAttribIPointer, we need to instruct the vertex fetch unit to convert the data to signed or unsigned int, rather than float. And when filling in the implied w=1 on a vector with less than 4 components, we need to fill it in with the integer representation of 1 rather than the floating-point representation of 1. Fixes piglit tests vs-attrib-{ivec4,uvec4}-precision. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
9734bd05608c00a1d84851f3d46d5deb52e75d5e |
|
25-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix flat integral varyings. Previously, the vertex and fragment shader back-ends assumed that all varyings were floats. In GLSL 1.30 this is no longer true--they can also be of integral types provided that they have an interpolation qualifier of "flat". This required two changes in each back-end: assigning the correct type to the register that holds the varying value during shader execution, and assigning the correct type to the register that ties the varying value to the rest of the graphics pipeline (the message register in the case of VS, and the payload register in the case of FS). Fixes piglit tests fs-int-interpolation and fs-uint-interpolation. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
6da9b21f716d97fc9ef4797abb6368b0a5f92a14 |
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22-Oct-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Use glsl_type::column_type instead of open-coding it Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
31874f074c2eaf2a9421c57f0798c79078d296c4 |
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04-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix comparisons with uint negation. The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes vs-op-neg-* Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
3560027977804a3ac4ae8e6c9390f0936f7f7a1a |
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16-Oct-2011 |
Brian Paul <brianp@vmware.com> |
i965: silence signed/unsigned comparison warning Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
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07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h. I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chad Versace <chad@chad-versace.us> Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
010cc547ca8c1fb2107106b0ad0de560780ce9aa |
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20-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
mesa: Use gl_shader_program::_LinkedShaders instead of VertexProgram Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
018ea68d8780ab5baeef0b8122b8410e5e55ae6d |
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27-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 Gen6+: De-compact clip planes. Previously, if the user enabled a non-consecutive set of clip planes (e.g. 0, 1, and 3), the driver would compact them down to a consecutive set starting at 0. This optimization was of dubious value, and complicated the implementation of gl_ClipDistance. This patch changes the driver so that with Gen6 and later chipsets, we no longer compact the clip planes. However, we still discard any clip planes beyond the highest number that is in use, so performance should not be affected for applications that use clip planes consecutively from 0. With chipsets previous to Gen6, we still compact the clip planes, since the pre-Gen6 clipper thread relies on this behavior. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
f4f686e825ad2d64e50fb9e2491ef60507d59c38 |
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30-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 VS: Change nr_userclip to nr_userclip_planes. The only remaining uses of brw_vs_prog_key::nr_userclip only occurred when using clip planes (as opposed to gl_ClipDistance). This patch renames the value to nr_userclip_planes and sets it to zero when gl_ClipDistance is in use. This avoids unnecessary VS recompiles. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
18e2e19b07b312c978dfbb6d336f69fa84b3ffe2 |
|
27-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Make brw_compute_vue_map's userclip dependency a boolean. Previously, brw_compute_vue_map required an argument indicating the number of clip planes in use, but all it did with it was check if it was nonzero. This patch changes brw_compute_vue_map to take a boolean instead. This allows us to avoid some unnecessary recompilation of the Gen4/5 GS and SF threads. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
8f6920a7b69bd20f04f807e88c22cf1eb78b4e79 |
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28-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Move ClipPlanesEnabled state to VS cache key. Previous to this patch, setup_uniform_clipplane_values() was setting up clip plane uniforms based on ctx->Transform.ClipPlanesEnabled, a piece of state not stored in the vertex shader cache key. As a result, a change to this piece of state might not trigger a necessary vertex shader recompile. The patch adds a field to the vertex shader cache key, userclip_planes_enabled, to store the current value of ctx->Transform.ClipPlanesEnabled. Also, it changes setup_uniform_clipplane_values() to read from this new field, so that it's manifestly clear that the vertex shader isn't depending on state not stored in the cache key. Note: when the vertex shader uses gl_ClipDistance, the VS backend doesn't need to know which clip planes are in use, so we leave the field as zero in that case to avoid unnecessary recompiles. Fixes Piglit test vs-clip-vertex-enables. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
d912669034eb7bf5c162358a7a574ec7a4c963c7 |
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26-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 Gen6: Implement gl_ClipVertex. This patch implements proper support for gl_ClipVertex by causing the new VS backend to populate the clip distance VUE slots using VERT_RESULT_CLIP_VERTEX when appropriate, and by using the untransformed clip planes in ctx->Transform.EyeUserPlane rather than the transformed clip planes in ctx->Transform._ClipUserPlane when a GLSL-based vertex shader is in use. When not using a GLSL-based vertex shader, we use ctx->Transform._ClipUserPlane (which is what we used prior to this patch). This ensures that clipping is still performed correctly for fixed function and ARB vertex programs. A new function, brw_select_clip_planes() is used to determine whether to use _ClipUserPlane or EyeUserPlane, so that the logic for making this decision is shared between the new and old vertex shaders. Fixes the following Piglit tests on i965 Gen6: - vs-clip-vertex-const-accept - vs-clip-vertex-const-reject - vs-clip-vertex-different-from-position - vs-clip-vertex-equal-to-position - vs-clip-vertex-homogeneity - vs-clip-based-on-position - vs-clip-based-on-position-homogeneity - clip-plane-transformation clipvert_pos - clip-plane-transformation pos_clipvert - clip-plane-transformation pos Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
1d4f3ca8f0442821c914b758b323e6e5124149a3 |
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29-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/vs: Implement integer quotient and remainder math operations. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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fe006a74f6fd1ddeec778226111938193a995a6c |
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01-Oct-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
i965/vs: Fix swizzle related assertion As innocuous as it seemed, ebca47a basically broke the world (e.g., >200 piglit regressions). In vec4_visitor::emit_block_move, src->swizzle was expected to be BRW_SWIZZLE_NOOP before setting it to a swizzle that would replicate the existing channels of the source type to a vec4 (e.g., .xyyy for a vec2). The original assertion seems to have been a little bogus. In addition to being BRW_SWIZZLE_NOOP, src->swizzle might already be a swizzle that would replicate the existing channels of the source type to a vec4. In other words, it might already have the value that we're about to assign to it. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
ebca47af8507e0fc3f03d6c0f49be6b2d4d9a8a4 |
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30-Sep-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Assign instead of compare inside assert This is from a Coverity defect report. src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 1314 void 1315 vec4_visitor::emit_block_move(dst_reg *dst, src_reg *src, 1316 const struct glsl_type *type, bool predicated) ... 1351 /* Do we need to worry about swizzling a swizzle? */ ->1352 assert(src->swizzle = BRW_SWIZZLE_NOOP); 1353 src->swizzle = swizzle_for_size(type->vector_elements); Reported-by: Vinson Lee <vlee@vmware.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40158 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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158a5854502ce071e3f07d4ad9622b8ddb3c9859 |
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27-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for bit-shift operations. Reviewed-by: Chad Versace <chad@chad-versace.us> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
64ce64a3f88f0c33a3f9a97f231bd98983887e27 |
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24-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 new VS: Fix bugs in pre-GEN6 psiz/flags computation This patch corrects two errors in the computation of the psiz/flags VUE slot on pre-GEN5 when using the new VS backend: - The clip flags (which should be stored in the w component of the first VUE slot) were being accidentally duplicated in all other components of that VUE slot, causing partially clipped triangles to sometimes disappear completely. - The OR instruction wasn't being stored in "inst", causing the BRW_PREDICATE_NORMAL flag to be applied to the wrong instruction. This patch fixes regressions in clipping behavior when using shaders on GEN4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
e7da40afe84349a640fe15e3af408a0dfe880e85 |
|
24-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 new VS: don't share clip plane constants in pre-GEN6 In pre-GEN6, when using clip planes, both the vertex shader and the clipper need access to the client-supplied clip planes, since the vertex shader needs them to set the clip flags, and the clipper needs them to determine where to insert new vertices. With the old VS backend, we used a clever optimization to avoid placing duplicate copies of these planes in the CURBE: we used the same block of memory for both the clipper and vertex shader constants, with the clip planes at the front of it, and then we instructed the clipper to read just the initial part of this block containing the clip planes. This optimization was tricky, of dubious value, and not completely working in the new VS backend, so I've removed it. Now, when using the new VS backend, separate parts of the CURBE are used for the clipper and the vertex shader. Note that this doesn't affect the number of push constants available to the vertex shader, it simply causes the CURBE to occupy a few more bytes of URB memory. The old VS backend is unaffected. GEN6+, which does clipping entirely in hardware, is also unaffected. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
62bad54727690bff5ed42a74272e7822fd36cdb6 |
|
02-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Set up clip distance VUE slots appropriately for gl_ClipDistance. When gl_ClipDistance is in use, the contents of the gl_ClipDistance array just need to be copied directly into the clip distance VUE slots, so we re-use the code that copies all other generic VUE slots (this has been extracted to its own method). When gl_ClipDistance is not in use, the vertex shader needs to calculate the clip distances based on user-specified clipping planes. This patch also removes the i965-specific enum values BRW_VERT_RESULT_CLIP[01], since we now have generic Mesa enums that serve the same purpose (VERT_RESULT_CLIP_DIST[01]). Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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d4444b8e5b914cde428e549c0db9418ddc1402f6 |
|
09-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Return a dummy value when visiting ir_texture. While the program won't successfully link in the end, this avoids possible assertion failure in the driver during linking if this->result isn't initialized with something already.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
0502db1eabad23a90d658cbf5cd65305b9e0c077 |
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06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Do VUE writes using the MRF file instead of hardware register. We'll only do compute-to-MRF on accesses to this file.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
87b51fc4a807616eaab0c4b38e41c328c08875e3 |
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01-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Keep track of indices into a per-register array for virtual GRFs. Tracking virtual GRFs has tension between using a packed array per virtual GRF (which is good for register allocation), and sparse arrays where there's an element per actual register (so the first and second column of a mat2 can be distinguished inside of an optimization pass). The FS mostly avoided the need for this second sparse array by doing virtual GRF splitting, but that meant that instances where virtual GRF splitting didn't work, instructions using those registers got much less optimized.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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27c03cb86aa9149d001eefb3cf1e67a97f5bc886 |
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07-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix variable indexed array access with more than one array. The offset to the arrays after the first was mis-scaled, so we'd go access off the end of the surface and read 0s. Fixes glsl-vs-uniform-array-3. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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6af968b6736c87c05ea579df50e23b6f23b900d4 |
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06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add annotation to more of the URB write. While we had nice debug output for most of the instruction stream, it was terminated by a series of anonymous MOVs and a send. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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9bd8d90646572a170bd96a72d2f8d5739df381be |
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31-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix point size handling on gen4. Fixes glsl-vs-point-size. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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bba910373fc6cdca939422d94adfe58b43e41b86 |
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31-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for vector comparison ops resulting in bool cond codes. Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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2ffc5ac1da40186ef1c5155df21caa3aa3c34ccb |
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03-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix gen4 comparisons used for predication. When we tried to retype a brw_null_reg() in CMP(), the retyping didn't take effect because HW_REG just ignores the type field. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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becd54eedb26ec9076e6f5f98f485861b3e13a90 |
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03-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Remove two_side_color from brw_compute_vue_map(). Since we now lay out the VUE the same way regardless of whether two-sided color is enabled, brw_compute_vue_map() no longer needs to know whether two-sided color is enabled. This allows the two-sided color flag to be removed from the clip, GS, and VS keys, so that fewer GPU programs need to be recompiled when turning two-sided color on and off. Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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f3ecc90730c1637b82e7a8eb8bef6d9a7a0531e8 |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: Compute urb entry size based on the VUE map. Previously, the new VS backend computed the size of the URB entry by counting the number of MRFs used in emitting the URB entry. Now it just gets it straight from the VUE map. Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
ee3195a5ff9ce3e549fd254ecd751319a0bd9db5 |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: Clarify comments about max_usable_mrf and add an assertion. max_usable_mrf has been carefully set such that (max_usable_mrf - base_mrf) is a multiple of 2, so that an even number of VUE slots are emitted with each URB write (which Gen6 requires). This patch adds an assertion to confirm that this is the case, and moves the comment to this effect to be near the assertion. Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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e604f98f580b74dd6c597ef492706ce74697443e |
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23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: use the VUE map to write out vertex attributes. Previously, the new VS backend used two functions, emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed parts of the VUE, and then a pair of carefully-constructed loops to emit the rest of the VUE, leaving out the parts that were already emitted as part of the header. This patch changes the new VS backend to use the VUE map to emit the entire VUE. Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
d1435a49e9765ab4e988dd8b65a5599da34f3512 |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: move clip distance computation (GEN5+) to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
d9eca0b27903acef97f7b69a70dc791b433f1c98 |
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23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: Move PSIZ/flags computation to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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f86d1976f81811aec0a555946e263295ed1403db |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: move NDC computation (GEN4-5) to a separate function. Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
34fbab2125555ba0afffa361e1c74fb3359ef3a7 |
|
23-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: new VS: Use output_reg[] to find NDC and HPOS registers. Previously, emit_vue_header_gen4() used local variables to keep track of which registers were storing the NDC and HPOS. This patch uses the output_reg[] array instead, so that the code that manipulates NDC and HPOS can be more easily refactored. Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
0c9ae24dbdfcfea06fb0e8cdfd7737da48fa4e31 |
|
27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Avoid the emit(), remove(), insert_before() for array instructions. v2: Add generator instructions for the scratch opcodes. Add emit_before() for handling ->ir and ->annotation inheritance. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
e45d0270c9f6f170e35ae39e95977b60f0f0be9a |
|
27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Move logic for weird CMP type handling to CMP generators. v2: Don't bother with the no-dst-reg version of CMP() Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
a8e29987f5a64d566a128a1c1ac18dae3f3953db |
|
27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Convert emit() calls to the new instruction generators. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
ead7ffc62a99c83c3f41a3f229cfbb9ed1826df0 |
|
27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Convert gen6 userclip handling to new generators. This DP4 had one of its operands missing, so we were generating garbage clip distances. Using the per-opcode instruction generators made it obvious. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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2f12be5c952ec84eece74a321e5b0a92314aba3a |
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27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Create instruction generators outside of the emit() functions. v2: Fixed gen6 IF(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
81a0b2166991a3015f8336e184c34cf6a92adfe0 |
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23-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix GL_FIXED setup when a writemask is present. By emitting code before generate_code(), we ended up in align1 mode where writemasks don't exist, so we rescaled gl_Vertex.w and things went badly. By moving GL_FIXED support to the visitor, we end up with normal codegen, and as a bonus the GL_FIXED setup ends up getting printed appropriately in debug output. Fixes gtf/GL2Tests/fixed_data_type Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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72cfc6f3778d8297e52c254a5861a88eb62e4d67 |
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23-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Pack live uniform vectors together in the push constant upload. At some point we need to also move uniform accesses out to pull constants when there are just too many in use, but we lack tests for that at the moment. Fixes glsl-vs-large-uniform-array. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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7c84b9d303345fa5075dba8c4ea7af449d93b0f8 |
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23-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Track uniforms as separate vectors once we've done array access. This will make it easier to figure out which elements are totally unused and not upload them. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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483f5b348b0f3c0ca7082fd2047c354e8af285e7 |
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22-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for pull constant loads for uniform arrays. v2: reworked the instruction emit and made use of gen6_resolve_implied_move, from Ken's review
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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88e08de8017b69591b37dafde9afd15f796fb404 |
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27-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Restructure emit() functions around a vec4_instruction constructor. We sometimes want to put an instruction somewhere besides the end of the instruction stream, and we also want per-opcode instruction generation to enable compile-time checking of operands.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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55b7fbb70ffc1f4def5c3ded63c3ef569e693731 |
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19-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use native integer uniforms when the new VS backend is in use. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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3dadc1e3cceac80a1b63cad2e10f0e0f8904531b |
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17-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Copy the live intervals calculation over from the FS. This is a rather pessimistic calculation, since it doesn't distinguish individual channels of a vec4, or elements of an array, but should be a minimum start for register allocation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
0ddf0f1c3451eef8a7c7f46afca623dc4f7c5af6 |
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16-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix multiplies to actually do 32-bit multiplies. Fixes vs-op-mult-int-int and friends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
7bf70c29adf175f51d0347d0187aecc0e9bbbcb8 |
|
16-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for conversion of FIXED_HW_REG src_reg to/from dst_reg. This was quietly occurring in some emit code I produced, and failed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
e9a86ae3370948acb1276e80fbbc421d7025db36 |
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16-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix memory leak of ralloc context for the visitor.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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feff7c62ce446f4e3bb755a2f40dcbd0e70155e4 |
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16-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix condition code for scalar expression all_equals. Fixes vs-op-eq-bool-bool.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
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8a649277cb57cc13fb38f8e8daf07e8a2b96223c |
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12-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Don't assertion fail on vertex texturing. The linker will reject the program, but we need to survive until then. Fixes abort in glsl1-2D Texture lookup with explicit lod (Vertex shader)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
905f3d03090c7b86e410959c5640054f5f6894ef |
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12-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Remove remaining use of foreach_iter.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
7642c1de6b65b7dfd9e39904291cc9737cd54b56 |
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11-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Avoid generating a MOV for most ir_assignment handling. Removes an average of 11.5% of instructions in 54% of vertex shaders in shader-db.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
7fbe7fe13359d3f349664410ec73d7bd48824ed6 |
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11-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Run the shader backend at link time and return compile failures. Link failure is something that shouldn't happen, but we sometimes want it during development. The precompile also allows analysis of shader codegen with shader-db.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
193a9a209d5121e2c20f1d20c61587b1e3d0603d |
|
10-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for if(any(bvec)) on gen6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
aed5e353e95f47773864c6e61c506b9ddad0e2e9 |
|
10-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Clamp vertex color outputs when required by ARB_color_buffer_float. Fixes glsl-vs-vertex-color.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
fea7d34b3545878ce00914f388e1eeebf55f7748 |
|
09-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix builtin uniform setup. I want to intelligently pack them at some point, but for now we have the params set up in groups of 4. Fixes glsl-vs-normalscale.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
0b359e3ea015576d0e75bf5ec19aceef337311a3 |
|
09-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for loops. This is copied from brw_fs.cpp, instead of doing the temporary IR generation that ir_to_mesa does. Fixes glsl-vs-loop and friends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
abf843a797876b5e3c5c91dbec25b6553d2cc281 |
|
09-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for ir_binop_pow. Fixes vs-pow-float-float.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
250770b74d33bb8625c780a74a89477af033d13a |
|
09-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Respect the gen6 limitation that math opcodes can't be align16. Fixes vs-acos-vec3 and friends.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
6408b0295f5c8be6fea891a025d79752484721b6 |
|
09-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix implementation of ir_unop_any. We were inheriting whatever previous predicate existed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
d0e4d71070cd7fa197ed98612782484ec1f27123 |
|
07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Move virtual GRFs with array accesses to them to scratch space.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
758c3c2b4588f235def48b2f28c0479a70f7c194 |
|
08-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Reserve MRF 14/15 for array loads/register unspilling.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
1ff4f11dd94711a498cde0330101c58636ef2741 |
|
07-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Track the variable index of array accesses. This isn't used currently, as we lower all array accesses.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
160a5a3ff0fc826a2978c6bea6de21b445f612e9 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for VUEs larger than a single URB write. Fixes glsl-max-varyings.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
31ef2e3ec2f5837eea0899b4bda5ea15e335a6a2 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Avoid generating extra moves when setting up large ir_constants. We were also screwing up the types in the process, and just not emitting moves was easier.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
aba9801996f2f524a765df378c234a7645b3a5d1 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix types of varying outputs. For structs/arrays/matrices, they were ending up as uint because we forgot to set them. All varyings in GLSL 1.20 are of base type float, so just force the matter here (which gets inherited at emit_urb_writes() time). Fixes vs-varying-array-mat2-col-rd.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
979072613139870f12e329e4b483c7f688b40560 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Handle assignment of structures/arrays/matrices better. This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
930afd1774bdcd013bccbd7b5717ae0bb8e3dea3 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Don't forget to set up assignment condition code for arrays/structs. Fixes vs-uniform-array-mat2-index-col-rd.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
cda28bca0d789c328d19bf90afd35a5ff74cfb77 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Apply the gen6 math workaround for math1 instructions. Fixes glsl-vs-masked-cos.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
2b7632aeaa5f8b4ab3da7d33a3c71c71023a072a |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Add support for if(any_nequal()) and if(all_equal()) on gen6. Fixes vs-temp-array-mat2-col-rd.shader_test.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
8e947c2546c25c0dfa93b538e54113af1bf582df |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix the types of array/struct dereferences. Fixes glsl-vs-arrays-3.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
e5363c7fd2ed6318e86ba4a62adc0c2377e51eef |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Use an appropriate swizzle on src regs from variables. Fixes glsl-vs-if-bool.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
164ccd27787e0df4ae6f85a7178aff0720d56ac9 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix support for "IF" instructions by copying brw_fs_visitor.cpp. Fixes glsl-vs-if-greater.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
aa753c5a14637ede804e8043762693122174bf8c |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Disable loops for now until rendering is generally correct.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
bb468fc1ede9b0a5231ebfaa51df444502d33654 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix ir_swizzle handling. I decided to refactor it a bit in adapting ir_to_mesa.cpp code, and mangled it. Fixes glsl-vs-cross-2.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
78fac1892a3a7a90eb7baf78903d70649028d27a |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Allocate storage for "auto" variables just like temps. Fixes segfault in glsl-vs-cross-2.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
82aa9299fbfe92d2526fa9f7ffd2a1ebc7827ee9 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Allow scalar values in assignments, too. Fixes glsl-vs-all-02 and many other tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
c0f334a3ed3c6645abd1812e39cd52f1dfa32fa1 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Don't emit an extra copy of the vertex position. Fixes glsl-vs-abs-neg, glsl-vs-all-01, and probably many other tests.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
4a4857246c79c42d918a84d7e28e9afff3a9ef6d |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Port the fix for clip plane writemasks from brw_vs_emit.c.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
83d5850518388202c5589d3181b84fb54c213fb1 |
|
06-Aug-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Fix constant vector construction. Fixes some issues noticed in glsl-vs-all-01.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
a070d5f363e99b0f846d555e9ca3a74ec807fdc0 |
|
04-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/vs: Start adding support for uniforms There's no clever packing here, no pull constants, and no array support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|
af3c9803d818fd33139f1247a387d64b967b8992 |
|
02-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Start adding the VS visitor and codegen. The low-level IR is a mashup of brw_fs.cpp and ir_to_mesa.cpp. It's currently controlled by the INTEL_NEW_VS=1 environment variable, and only tested for the trivial "gl_Position = gl_Vertex;" shader so far.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
|