| e87174cf4b499c8e9558438e70b0da5f0f38f54a |
|
16-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().
Previously, when performing a blit using the blorp engine, we failed
to account for the level and layer of the source and destination. As
a result, all blits would occur between miplevel 0 and layer 0 of the
corresponding textures, regardless of which level/layer was bound to
the framebuffer.
This patch passes the correct level and layer through
brw_blorp_miptrees() into the brw_blorp_blit_params data structure.
Further patches in the series will adapt
gen{6,7}_blorp_emit_surface_state to make use of these parameters.
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 3123f0621561549c4566248100661ef77cab2834)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 5db1deab5118a986167ea6e8f8c7c196c74457c1 |
|
04-Sep-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Adjust stencil buffer size after computing miptree layout.
Since Gen6+ stencil buffers use W-tiling (a tiling arrangement which
drm and the kernel are not aware of) we need to round up the width and
height of a stencil buffer to multiples of the W-tile size (64x64)
before allocating a stencil buffer. Previously, we rounded up the
size of the base miplevel, and then computed the miptree layout based
on the rounded up size. This was incorrect, because it meant that the
total size of the miptree would not be properly W-tile aligned, and
therefore we would not always allocate enough pages.
(Note: even though the GL API doesn't allow creation of mipmapped
stencil textures, it does allow mipmapping of a combined depth/stencil
texture, and on Gen6+, a combined depth/stencil texture is internally
implemented as a pair of separate depth and stencil buffers.)
For example, on Sandy Bridge, when allocating a mipmapped stencil
texture of size 128x128, we would first round up to the nearest
multiple of 64x64 (causing no change to the size), and then compute
the miptree layout (whose size worked out to 128x196). Then we would
request an allocation of 128*196 bytes (6.125 pages), causing 7 pages
to be allocated to the texture. However, the texture needs 8 pages,
since each W-tile occupies a page, and it takes 2 W-tiles to cover a
width of 128 and 4 W-tiles to cover a height of 196.
This patch changes the order of operations so that the miptree layout
is computed first and then the total size of the miptree is rounded up
to be W-tile aligned.
NOTE: This is a candidate for the 8.0 release branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit bde833c9d014ad8aebfab0d2285184d7e6d5896d)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 6cb9e99a757bd5a9d908ed6c5515a9ae5fb041ba |
|
09-Aug-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Always downsample in intel_miptree_map_multisample
Always downsample before mapping, even if the map mode contains
GL_MAP_INVALIDATE_RANGE_BIT. If we neglect to downsample when only
a subrect is mapped then the upsample in intel_miptree_unmap_multisample
may write garbage to the region outside the subrect.
(Eric gave my patch e88cfbb a conditional reviewed-by with the condition
that it always downsample before mapping. I forgot to make that change
before pushing the patch.)
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| e88cfbb95f631ca1275a5cef4ccc5aaffb70aaba |
|
28-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Support mapping multisample miptrees
Add two new functions: intel_miptree_{map,unmap}_multisample, to which
intel_miptree_{map,unmap} dispatch. Only mapping flat, renderbuffer-like
miptrees are supported.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 4c0ccc13bd3ec149c4a51c4937811894fbe713f0 |
|
28-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor use of intel_miptree_map
Move the opencoded construction and destruction of intel_miptree_map into
new functions, intel_miptree_attach_map and intel_miptree_release_map.
This patch prevents code duplication in a future commit that adds support
for mapping multisample miptrees.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 81980958d0d3def26741cfe78b7c23f6635f826a |
|
28-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor intel_miptree_map/unmap
Move the body of intel_miptree_map into a new function,
intel_miptree_map_singlesample. Now intel_miptree_map dispatches to the
new function. A future commit adds a multisample variant.
Ditto for intel_miptree_unmap.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| d3746354fbfadf821dc108e072d86b5329737444 |
|
12-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Define functions for up/downsampling on miptrees
Flesh out the stub functions intel_miptree_{up,down}sample.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| f4873babdc27f697df9f4642209eca21a02ac476 |
|
19-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Allocate miptree for multisample DRI2 buffers
Immediately after obtaining, with DRI2GetBuffersWithFormat, the DRM buffer
handle for a DRI2 buffer, we wrap that DRM buffer handle with a region and
a miptree. This patch additionally allocates an accompanying multisample
miptree if the DRI2 buffer is multisampled.
Since we do not yet advertise multisample GL configs, the code for
allocating the multisample miptree is currently inactive.
This patch adds the following fields to intel_mipmap_tree:
singlesample_mt
needs_downsample
and the following function stubs:
intel_miptree_downsample
intel_miptree_upsample
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 4eba67285fb6b5d2dd4927e8dc4b3e2945435309 |
|
20-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor creation of hiz and mcs miptrees
Move the logic for creating the ancillary hiz and mcs miptress for winsys
and non-texture renderbuffers from intel_alloc_renderbuffer_storage to
intel_miptree_create_for_renderbuffer. Let's try to isolate complex
miptree logic to intel_mipmap_tree.c.
Without this refactor, code duplication would be required along the
intel_process_dri2_buffer codepath in order to create the mcs miptree.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 97fc89c6cbaa3b5ef7f678d2dc2c7d5bbba05315 |
|
27-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Treat GL_SAMPLES=1 as equivalent to GL_SAMPLES=0.
EXT_framebuffer_multisample is a required subpart of
ARB_framebuffer_object, which means that we must support it even on
platforms that don't support MSAA. Fortunately
EXT_framebuffer_multisample allows for this by allowing GL_MAX_SAMPLES
to be set to 1.
This leads to a tricky quirk in the GL spec: since
GlRenderbufferStorageMultisamples() accepts any value for its
"samples" parameter up to and including GL_MAX_SAMPLES, that means
that on platforms that don't support MSAA, GL_SAMPLES is allowed to be
set to either 0 or 1. On platforms that do support MSAA, GL_SAMPLES=1
is not used; 0 means no MSAA, and 2 or higher means MSAA.
In other words, GL_SAMPLES needs to be interpreted as follows:
=0 no MSAA (possible on all platforms)
=1 no MSAA (only possible on platforms where MSAA unsupported)
>1 MSAA (only possible on platforms where MSAA supported)
This patch modifies all MSAA-related code to choose between
multisampling and single-sampling based on the condition (GL_SAMPLES >
1) instead of (GL_SAMPLES > 0) so that GL_SAMPLES=1 will be treated as
"no MSAA".
Note that since GL_SAMPLES=1 implies GL_SAMPLE_BUFFERS=1, we can no
longer use GL_SAMPLE_BUFFERS to distinguish between MSAA and non-MSAA
rendering.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| ee9f6a34ccf7f51111b21bba8d8f9d03cc0a2c74 |
|
26-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Use MESA_FORMAT_R8 for MCS buffer.
No functional change. This patch modifies intel_miptree_alloc_mcs to
allocate the 4x MCS buffer using MESA_FORMAT_R8 instead of
MESA_FORMAT_A8. In principle it doesn't matter, since we only access
the buffer using MCS-specific hardware mechanisms, so all that's
important is to use a format with the correct size. However,
MESA_FORMAT_A8 has enough unusual behaviours that it seems prudent to
avoid it.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 728561271303baa6aaeb5bdd953e62b117feba4d |
|
18-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Adjust MCS buffer allocation for 8x MSAA.
MCS buffers use 32 bits per pixel in 8x MSAA, and 8 bits per pixel in
4x MSAA. This patch adjusts the format we use to allocate the buffer
so that enough memory is set aside for 8x MSAA.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 8b762ebd72c1bb1a9827a667ad55ba9516505adf |
|
22-Jul-2012 |
Brian Paul <brianp@vmware.com> |
mesa: move some format helper functions to glformats.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| a5a34b153d494ad4374e7b2c8ea13b1073a887e2 |
|
19-Jun-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Enable GL_OES_compressed_ETC1_RGB8_texture
Enable it for all hardware.
No current hardware supports ETC1, so this patch implements it by
translating the ETC1 data to RGBX data during the call to
glCompressedTexImage2D(). For details, see the doxygen for
intel_mipmap_tree::wraps_etc1.
Passes the Piglit test spec/OES_compressed_ETC1_RGB8_texture/miptree and
the ETC1 test in the GLES2 conformance suite.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 33202b4876a88b6f54ca7022eadd2875a2d3508a |
|
06-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Enable CMS layout on Gen7 for the formats that support it.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| ccae1b1cd7b89102a9d9bfc29eb1e7e48aad8969 |
|
03-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Allocate MCS buffer when CMS MSAA is in use.
To implement Gen7's CMS MSAA layout, we need an extra buffer, the MCS
(Multisample Control Surface) buffer. This patch introduces code for
allocating and deallocating the buffer, and storing a pointer to it in
the intel_mipmap_tree struct.
No functional change, since the CMS layout is not enabled yet.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 1bd4d456cdecf7bea55f4e3dac574af54efad994 |
|
04-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Add an enum to describe MSAA layout.
From the Ivy Bridge PRM, Vol 1 Part 1, p112:
There are three types of multisampled surface layouts designated
as follows:
- IMS Interleaved Multisampled Surface
- CMS Compressed Mulitsampled Surface
- UMS Uncompressed Multisampled Surface
Previously, the i965 driver only used IMS and UMS formats, and
distinguished beetween them using the boolean
intel_mipmap_tree::msaa_is_interleaved. To facilitate adding support
for the CMS format, this patch replaces that boolean (and other
booleans derived from it) with an enum
INTEL_MSAA_LAYOUT_{IMS,CMS,UMS}. It also updates the terminology used
in comments throughout the driver to match the IMS/CMS/UMS terminology
used in the PRM. CMS layout is not yet used.
The enum has a fourth possible value, INTEL_MSAA_LAYOUT_NONE, which is
used for non-multisampled surfaces.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 02ebad900db4ef1ac42cbfb41b433919a4c857a2 |
|
05-Jul-2012 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Add offset field to miptree
This lets us specify an offset into the bo where the miptree starts,
which will let us set up a texture for a single plane in a planar buffer.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 455ac562722f60ac9fb0c3d3c697fa339fa011ad |
|
08-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Properly handle sliced layout for Gen7.
Starting in Gen7, there are two possible layouts for MSAA surfaces:
- Interleaved, in which additional samples are accommodated by scaling
up the width and height of the surface. This is the only layout
available in Gen6. On Gen7 it is used for depth and stencil
surfaces only.
- Sliced, in which the surface is stored as a 2D array, with array
slice n containing all pixel data for sample n. On Gen7 this layout
is used for color surfaces.
The "Sliced" layout has an additional requirement: it must be used in
ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra
room between array slices for miplevels other than 0.
This patch modifies the surface allocation functions to use the
correct layout when allocating MSAA surfaces in Gen7, and to set the
array offsets properly when using ARYSPC_LOD0 mode. It also modifies
the code that populates SURFACE_STATE structures to ensure that
ARYSPC_LOD0 mode is selected in the appropriate circumstances.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 52fcc36f11b12236eb4f960b65b17b047cf32efa |
|
11-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern.
Gen6 MSAA buffers (and Gen7 MSAA depth/stencil buffers) interleave
MSAA samples in a complex pattern that repeats every 2x2 pixel block.
Therefore, when allocating an MSAA buffer, we need to make sure to
allocate an integer number of 2x2 blocks; if we don't, then some of
the samples in the last row and column will be cut off.
Fixes piglit tests "EXT_framebuffer_multisample/unaligned-blit {2,4}
color msaa" on i965/Gen6.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 54308f78a2f8675bfd854761f9cd8a6b71e119d0 |
|
21-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: Drop a layer of indirection in doing HiZ resolves.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 072634da4a6ee5eafb5f5df26ca5f988209e6d40 |
|
21-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: Replace intel_need_resolve with the hiz ops it maps to.
Having this enum separate caused us to need a bunch of helper
functions to translate to the op to be executed.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 19e9b24626c2b9d7abef054d57bb2a52106c545b |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.
MSAA support is still fairly preliminary. In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.
v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
of samples to the next higher sample count supported by the
hardware. This ensures that a query of GL_SAMPLES will return the
correct value. It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
so that we won't try to read from a nonexistent sample.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| a27c7d80afc3160a0face4b8781bf921229bc3cc |
|
06-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Stop lying about cpp and height of a stencil buffer.
When using a separate stencil buffer, i965 requires that the pitch of
the buffer (in the 3DSTATE_STENCIL_BUFFER command) be specified as 2x
the actual pitch.
Previously this was accomplished by doubling the "cpp" and "pitch"
values stored in the intel_region data structure, and halving the
height. However, this was confusing, and it led to a subtle (but
benign) bug: since a stencil buffer is W-tiled, its true height must
be aligned to a multiple of 64; we were accidentally aligning its faux
height to a multiple of 64, causing memory to be wasted.
Note that for window system stencil buffers, the DDX also doubles the
cpp and pitch values. To facilitate fixing this DDX server bug in the
future, we fix the cpp and pitch values we receive from the X server
only if cpp has the "incorrect" value of 2.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
v2: Clarify comments about the DDX.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| cdcfd5d1d60179e60e3a0a47dda71bfe91083105 |
|
27-Feb-2012 |
Anuj Phogat <anuj.phogat@gmail.com> |
intel: Fix a case when mapping large texture fails
This patch handles a case when mapping a large texture fails
in drm_intel_gem_bo_map_gtt(). These changes avoid assertion
failure later in the driver as reported in following bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=44970
https://bugs.freedesktop.org/show_bug.cgi?id=46303
Testing: No regressions in piglit quick.tests
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| f172eae8b23d0612865895c52af745021ae20a4c |
|
02-Mar-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
i965: fixup W-tile offset computation to take swizzling into account
There's even a comment in the code containing the right swizzling
computations!
Previously this has not been noticed because we need to manually
enabled swizzling on snb/ivb (kernel 3.4 will do that) and we
don't use the separate stencil on ilk (where the bios enables
swizzling). This fixes
piglit ./bin/fbo-stencil readpixels GL_DEPTH32F_STENCIL8 -auto
on recent drm-intel-next kernels.
Also remove the comment about ivb, it's stale now.
Swizzling detection is done by allocating a temporary x-tiled
buffer object. Unfortunately kernels before v3.2 lie on snb/ivb
because they claim that swizzling is enable, but it isn't. The
kernel commit that fixes this for backport to pre-v3.2 is
commit acc83eb5a1e0ae7dbbf89ca2a1a943ade224bb84
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Mon Sep 12 20:49:16 2011 +0200
drm/i915: fix swizzling on gen6+
But if the kernel doesn't lie, this now works on swizzling and
not swizzling machines.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 84e5f1c635899c657da58ca51d5e841354e9de9c |
|
01-Feb-2012 |
Eugeni Dodonov <eugeni.dodonov@intel.com> |
intel: check for LLC support when reading maps
This checks for advertised LLC support by the GPU instead of relying on
the GPU generation for detection.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 7e08bf08d13228001f6306800b5bd69b89b1bb6f |
|
27-Dec-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Fix gen6,gen7 when used with a non-HiZ capable DDX
Nothing works if HiZ is enabled and the DDX is incapable of HiZ (that is,
the DDX version is < 2.16).
The problem is that the refactoring that eliminated
intel_renderbuffer::stencil_rb broke the recovery path in
intel_verify_dri2_has_hiz(). Specifically, it broke line
intel_context.c:1445, which allocates the region for
DRI_BUFFER_DEPTH_STENCIL. That allocation was creating a separate stencil
miptree, despite the buffer being a packed depthstencil buffer. Havoc
ensued.
This patch introduces a bool flag that prevents allocation of that stencil
miptree.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44103
Tested-by: Ian Romanick <idr@freedesktop.org>
Note: This is a candidate for the 8.0 branch.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| a0a0a909f21acfcddaab603079ba98266e8daf0e |
|
05-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix infinite loop regression in intel_miptree_all_slices_resolve.
Commit 0ed11e333147e280208d9d0b3ff3f39970547643 fixed a "use after free"
bug by getting the next pointer before deleting the current node.
Unfortunately, it also made "next" never get updated if i->need != need.
Fixes infinite loops in piglit tests fbo-depth-array and fbo-depthtex.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 0ed11e333147e280208d9d0b3ff3f39970547643 |
|
04-Jan-2012 |
Anuj Phogat <anuj.phogat@gmail.com> |
Fix read from pointer after free
Coverity reported a read from pointer after free defect in
src/mesa/drivers/dri/intel/intel_mipmap_tree.c. Bug# 44205
In intel_miptree_all_slices_resolve() function, i = i->next was
executing after freeing i. I have defined a temporary variable
(next) to store the value of i->next before freeing i
Reported-by: Vinson Lee <vlee@vmware.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 747f0307626ef5bcf2f889ab66bcc95ab8eda2c8 |
|
27-Dec-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Fix memory leak in intel_miptree_create()
On failure, intel_miptree_create() needs to *release* the miptree, not
just free it, so that the stencil_mt gets released too.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 7f854a5028ef00a0e041e78a770456204dc58eef |
|
16-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Fix performance regression in Lightsmark since HiZ changes.
Since the refactor in d7b33309fe160212f2eb73f471f3aedcb5d0b5c1, depth
in the miptree changed from 1 to 6, so we always decided it didn't
match, and we would relayout to something that would still not
"match".
Improves performance 23.8% (+/- 1.1%, n=4)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43329
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| ab7794cada02f3b3b5e3a642c20eeedeb17b65a6 |
|
22-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Don't consider miptrees for other texture targets to match.
We would have done a relayout at validate time, but it's senseless to
store into a miptree if it's going to force relayout.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 4790c4ae2489b8c72e6d98f3f80b5a9e7f799203 |
|
07-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add separate stencil/HiZ setup for MESA_FORMAT_Z32_FLOAT_X24S8.
This is a little more unusual than the separate MESA_FORMAT_S8_Z24
support, because in addition to storing the real stencil data in a
MESA_FORMAT_S8 miptree, we also make the Z miptree be
MESA_FORMAT_Z32_FLOAT instead of the requested format.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 353f7ba4abbfd15d1e4e4b7a38f88e64ce85f6a2 |
|
03-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for mapping Z32_FLOAT_X24S8 fake packed depth/stencil.
The format handling here is tricky, because we're not actually
generating a Z32_FLOAT_X24S8 miptree, so we're guessing the format
that GL wants based on seeing Z32_FLOAT with a separate stencil.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| fdf18b323156098ba5fb2881aa1a7888d2e0667f |
|
15-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Properly demote the depth mt format for fake packed depth/stencil.
gen7 only supports the non-packed formats, even if you associate a
real separate stencil buffer -- otherwise it's as if the depth test
always fails.
This requires a little bit of care in the match_texture_image case,
since the miptree format no longer matches the texture image format.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| f22068d5be7c829d3768154845ef3c5a2986fed4 |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move S8 width/height alignment to miptree creation.
We were doing it in the caller in the renderbuffer code, but it was
missed in the separate stencil creation for textures. Apparently our
testing was using renderbuffers or pre-aligned sizes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 5655ebf4664b2e9a50b976612f8a1aeb26275311 |
|
30-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for LLC-cached reads of X-tiled miptrees using a blit.
This mimics the MapRenderbuffer code, and should improve the
performance of glGetTexImage().
v2: Fix broken error handling.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| ed3aeb56ec3fde24c2fc69515c0b5d348b41caf3 |
|
30-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make the fake packed depth/stencil mappings use a cached temporary.
Before, we had an uncached read of S8 to untile, then a RMW (so
uncached penalty) of the packed S8Z24 to store the value, then the
consumer would uncached read that once per pixel. If data was written
to the map, we would then have to uncached read the written data back
out and do the scatter to the tiled S8 buffer (also uncached access
penalties, since WC couldn't actually combine). So 3 or 5 uncached
accesses per pixel in the ROI (and we we were ignoring the ROI, so it
was the whole image).
Now we get an uncached read of S8 to untile, and an uncached read of
Z. The consumer gets to do cached accesses. Then if data was
written, we do streaming Z writes (WC success), and scattered S8
tiling writes (uncached penalty). So 2 or 3 uncached accesses per
pixel in the ROI.
This should be a performance win, to the extent that anybody is doing
software accesses of packed depth/stencil buffers.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| b48c3bca87b30003f9e117d299011380e743aec9 |
|
29-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move separate-stencil s8 mapping logic to intel_miptree_map.
We're going to want to reuse this logic in mapping of fake packed
miptrees wrapping separate depth/stencil miptrees.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| baeaa062e92afbec47fad73fd3d464a1e7d1fe08 |
|
29-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move the gtt-particular texture mapping logic to a helper function.
This code will be incrementally moving to a model like intel_fbo.c's
renderbuffer mapping with helper functions, as I move that code here.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 221a36514b4ecffdaa3be5c43e67c75cc8c30ab8 |
|
28-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make mapping of texture slices track the region of interest.
This will be used for things like packed depth/stencil temporaries and
making LLC-cached temporary mappings using blits.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| b75291c61c40a3a690b08f8aa013ad2d3d2deda8 |
|
28-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move the teximage mapping logic to a miptree level/slice mapping.
This will let us share teximage mapping logic with renderbuffer
mapping, which has an intel_mipmap_tree but not a gl_texture_image.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 5c9a55665d78b96bfb8ce8eab43b5558dd656a6d |
|
30-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Only prefer separate stencil when we can do HiZ.
This required is_hiz_depth_format to start returning true on S8_Z24 as
well, since that's the format we have here. The two previous callers
are only calling it on non-depthstencil formats.
This avoids us needing to have HiZ working on a new Z format
immediately upon exposing the format (particularly painful for
Z32_FLOAT_X24S8, which means all the fake packed depth/stencil paths).
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| b18875d441ca4b7b1a4098659fb4298a4bf265f6 |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Use separate stencil whenever possible
For depthstencil renderbuffers, we were using separate stencil only if the
hardware required it. Since the performance gains from HiZ is so high, we
should always use separate stencil if the hardware supports it.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| e7e81714f3ecf67a975d35e74bdb7fd15d924e4d |
|
08-Nov-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Implement the actual tables for texture alignment units [v2]
I implemented functions for horizontal/vertical alignment units separately
because I find it easier to read that way...especially with all the
corner-cases.
[chad] Corrected the vertical alignment calculation by checking for
depthstencil formats.
v2:
- Fix typos in intel_horizontal_texture_alignment_unit():
s/height/width/ and s/VALIGN/HALIGN.
- Remove special case for compressed formats in
intel_get_texture_alignment unit(). Compressed formats are already
handled in the halign and valign functions.
- Replace check ``_mesa_is_depth_format(...) ||
_mesa_is_depthstencil_format(...)`` with explcitit checks against
GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 017c13d55b5b086774d6afea2ca754482c624c6a |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Store miptree alignment units in the miptree
This allows us to replace all the calls to
intel_get_texture_alignment_unit() with a single call at miptree creation.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 3d760664e6349c72624aa6d54d40df0233995c8e |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Mark needed resolves when first enabling HiZ on a miptree
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 2945abea338031cbe90665df60152982bfca6177 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Add resolve functions for miptrees
Add functions that
- set a miptree slice as needing a resolve
- resolve a single slice of a miptree
- resolve all slices of a miptree
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| a2e44b0813e956440c451c107cf5564b56cbe98e |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]
This is required to correctly implement HiZ for mipmapped and
multi-layered textures.
v2: Accomodate refcount fixes in intel_process_dri2_buffer_*() that were
introduced in v2 of commit
intel: Replace intel_renderbuffer::region with a miptree [v2]
Reviewed-by: Eric Anholt <eric@anholt>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 3eb12dfaeed03f77e31943eea164acb03e86bbc9 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stencil_mt [v3]
For depthstencil textures using separate stencil, we embedded a stencil
buffer in intel_texture_image. The intention was that the embedded stencil
buffer would be the golden copy of the texture's stencil bits. When
necessary, we scattered/gathered the stencil bits between the texture
miptree and the embedded stencil buffer.
This approach had a serious deficiency for mipmapped or multi-layer
textures. Any given moment the embedded stencil buffer was consistent with
exactly one miptree slice, the most recent one to be scattered. This
permitted tests of type A to pass, but broke tests of type B.
Test A:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Read and test stencil data at (level=x1, layer=y1).
4. Upload data into (level=x2,layer=y2).
5. Read and test stencil data at (level=x2, layer=y2).
Test B:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Upload data into (level=x2,layer=y2).
4. Read and test stencil data at (level=x1, layer=y1).
5. Read and test stencil data at (level=x2, layer=y2).
v2:
Only allocate stencil miptree if intel->must_use_separate_stencil,
because we don't make the conversion from must_use_separate_stencil to
has_separate_stencil until commit
intel: Use separate stencil whenever possible
v3:
Don't call ChooseNewTexture in intel_renderbuffer_wrap_miptree() in
order to determine the renderbuffer format. Instead, pass the format as
a param to that function.
CC: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| d7b33309fe160212f2eb73f471f3aedcb5d0b5c1 |
|
15-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Kill intel_mipmap_level::nr_images [v4]
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its
value, like width and height, varies with miplevel.
- For other texture types, depth is 1.
As a consequence, parameters were removed from the following function
signatures:
intel_miptree_set_level_info
Remove 'nr_images'.
i945_miptree_layout
brw_miptree_layout_texture
brw_miptree_layout_texture_array
Remove 'slices'.
v2:
- Replace "It's" with "Its".
- Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked
in during a rebase.
- Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was
a little refactor of the for-loop's upper bound.
v4:
In intel_miptree_get_image_offset(), document the conditions under
which different if-branches are taken.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 278e77a1192d5251c5b70a555e676f72b446e8e1 |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor intel_miptree_copy_teximage()
Extract the body of the inner loop into a new function,
intel_miptree_copy_slice().
This is in preparation for adding support for separate stencil and HiZ to
intel_miptree_copy_teximage(). When copying a slice of a depthstencil
miptree that uses separate stencil, we will also need to copy the
corresponding slice of the stencil miptree. The easiest way to do this
will be to call intel_miptree_copy_slice() recursively. Analogous
reasoning applies to copying a slice of a depth miptree with HiZ.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| c2ddde70daece24d1eb7185946032158993a9e4d |
|
14-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor intel_mipmap_level offsets
Add a new field, intel_mipmap_level::slice, and move the offset fields
into it. Also add some much needed documentation for these fields.
Before this patch, a separate array was allocated for the
intel_mipmap_level::{x,y}_offsets. This was just silly; it incurred an
extra call to malloc and diminished memory locality.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 005149d5860ad55c5e58e2de8a138e3a763f2036 |
|
14-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Define intel_miptree_create_for_renderbuffer()
This function creates a miptree that is suitable as storage for
a non-texture renderbuffer.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 4ad8a0adec588b4c2c5a8f93265ed46cee5d3ff6 |
|
17-Oct-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop texture border support code.
Now that texture borders are gone, we never need to allocate our
textures through non-miptrees, which simplifies some irritating paths.
v2: Remove the !mt support case from intel_map_texture_image()
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 882c83377da57d41c62eb38484305523c3d19dd7 |
|
24-Oct-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Kill dead code in intel_miptree_copy_teximage()
Kill the code paths taken when src_mt is null. It is never null, otherwise
there would be a segfault on line 4 of this function:
GLuint width = src_mt->level[level].width;
(Some interleaved lines in the diff make the real diff non-obvious. All
I did was delete some code and then left-shifted what remained to correct
the indentation.)
Reviewed-by: Eric Anholt <eric@aholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 66681b4c8cb1ef16f42c1591298cb30c83bca09b |
|
23-Oct-2011 |
Brian Paul <brianp@vmware.com> |
mesa: remove _mesa_alloc_texmemory(), _mesa_free_texmemory()
Core Mesa no longer does any texture memory allocation.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 6e0f9001fe3fb191c2928bd09aa9e9d05ddf4ea9 |
|
23-Oct-2011 |
Brian Paul <brianp@vmware.com> |
mesa: move gl_texture_image::Data, RowStride, ImageOffsets to swrast
Only swrast and the drivers that fall back to swrast need these fields now.
This removes the last of the fields related to software rendering from
gl_texture_image.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| f8377b411dfe3c879eaab11bb86f509178796bd1 |
|
22-Sep-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add 'mode' param to intel_region_map
The 'mode' param is a bitset of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT.
A future commit will perform buffer resolves in intel_region_map(). So,
even though the access mode is irrelevant to the GTT, the extra
information allows us to intelligently avoid unneccessary buffer resolves.
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 669f1822d2a60865514faf37f9fde21e4567b3d2 |
|
06-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_EXT_texture_array and GL_MESA_texture_array.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| fd99cd0e10849205749aad580fea8c970fb46a31 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add a helper function for getting miptree size from a texture image.
With 1D array textures, we no longer agree between the GL information
about width/height/depth of a texture and how we lay out a miptree.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| b07c78bfe94c17e6fccba70923b03a29c751fde1 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Consolidate texture validation copy code, and reuse it correctly.
The path for ->Data was failing to be called for the FBO draw offset
fallback, and also had mismatched compressed texture support code.
This drops the intel_prepare_render() in the blit path. We aren't
copying to/from a GL_FRONT buffer, so it doesn't matter.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 055995abc4e2f4a73122bd008a0e6f0558300d82 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Clean up the function chain for mapping texture images for swrast.
Too many separate functions each called from one location (in
different files). This code should all die soon when swrast starts
using MapTextureImage.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 32fe506ae14efa055f4773f422e2edd9fd1cffee |
|
22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Allow src == NULL and *dst != NULL in intel_miptree_reference().
This makes this API consistent with intel_region_reference, and the
consumers wanted it this way.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| db3ada6055814a4bd5aa95fc9505fc101864391d |
|
22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the "intel" argument to intel_miptree_release().
We don't have it in the other refcounting functions, and it was
totally unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| d7cdbc3c5415d2dd5eee58834b13714a89eacf2b |
|
24-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Remove pointless boolean return value from *_miptree_layout.
i915_miptree_layout, i945_miptree_layout, and brw_miptree_layout always
just return GL_TRUE, so there's really no point to it. Change them to
void functions and remove the (dead) error checking code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 1a662e7c18cab98f1b122f6766faf338725de673 |
|
23-Sep-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
intel: fix the wrong code to detect null texture.
There is already comments show how to detect a null texture. Fix the
code to match the comments.
This would fix the oglc divzero(basic.texQOrWEqualsZero) and
divzero(basic.texTrivialPrim) test case fail.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| fa2c886863492cc3eeee6d2059ae24edc1cb2bff |
|
17-Sep-2011 |
Brian Paul <brianp@vmware.com> |
intel: make intel_texture_image a subclass of swrast_texture_image
We need to subclass swrast_texture_image because if we use swrast for
fallback rendering, we'll need to have swrast_texture_image objects.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 6f23d9b637602d9997896c6ca5cba0dfe36a092e |
|
26-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Silence "warning: unused parameter ‘depth0’"
The depth0 parameter was not used in intel_miptree_create_for_region,
so remove it. All of the places that call this function, pass 1 for
that parameter, and the place where it looks like it should have been
used (the call to intel_miptree_create_internal) also had 1 hard
coded.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 36a91e45f755af164232ef908419bc4cb64ba45b |
|
26-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Silence several "warning: unused parameter"
The intel_context and tiling parameters were not used by any if the
i9[14]5_miptree_layout or the functions they call, and the tiling parameter was
not used by brw_miptree_layout. Remove the unnecessary parameters.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 7dae1aaf142999e3cfeafb13d30abda667d66d87 |
|
15-Jul-2011 |
Brian Paul <brianp@vmware.com> |
intel: use new gl_texture_image:Face, Level fields
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| f94fef83db10f0c9327bd3dd43510ad31c94d82a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the cpp argument to intel_miptree_create().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 6dcc398ac0837025cf60b4d6a056fa3b0a16466f |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Calculate compress_byte in intel_miptree_create.
One less argument and thing to get wrong.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 9c5fdbb721147f7304faaa8960f5b64e25a8f673 |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Use the gl_format to get the base_format for miptree create.
One less argument to this insanely long function call.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 9a523a48af05118424714f0a34ca3dda6861186a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the internal_format field of the mipmap tree.
This has been replaced with the gl_format now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 0fac09a87c07d09dcd915c02b831505a53b02153 |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make the intel_miptree_match_image format check more specific.
We don't care just about the internalFormat/cpp/compressed, but about
the specific format chosen. We have no support for format
translations as part of texture validation, and furthermore it has
restrictions in the GL specification. However, we should be making
consistent decisions for this check anyway.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 4a60b0c8d2e4890038e1c6a72a7dac3b4cdf996e |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add block alignment for RGTC textures.
We were using the default 4x2 alignment instead of the 4x4 required
for RGTC textures.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| d5809115b568d8b74f47316607dce0730964517a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add the MESA_FORMAT as a field of the miptree.
We only had internal_format before, which is way more irritating to
work with.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 51ce86b7811871896d3b838888ab4adbfb77413d |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Fix 2x2 and 1x1 compressed teximages from _mesa_generate_mipmap()
Generally image uploads to a the region occur at TexImage time, but
that's not the case for fallback _mesa_generate_mipmap(), and in this
path we were forgetting to align the width when dividing height. We
were just leaving out parts of the compressed block at 2x2 and 1x1
levels.
Fixes gen-compressed-teximage.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| c270f1a628a625ccc9f6d931f2921e3d92c31818 |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add hiz_region to intel_mipmap_tree
When a texture is attached to multiple FBO's, a separate renderbuffer
wrapper is created for each attachment. This necessitates storing the hiz
region for these renderbuffers in the texture itself instead of the
renderbuffer wrapper.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 5b3eb7538cd9ceb967b6e9e765896183e7c2c4d4 |
|
10-Jan-2011 |
Eric Anholt <eric@anholt.net> |
Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."
This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663.
This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa.
I was wrong about which generations supported baselevel adjustment --
it's just gen4, nothing earlier. This meant that i915 would have
never used the mag filter when baselevel != 0. Not a severe bug, but
not an intentional regression. I think we can fix the performance
issue another way.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 7ce6517f3ac41bf770ab39aba4509d4f535ef663 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Always allocate miptrees from level 0, not tObj->BaseLevel.
BaseLevel/MaxLevel are mostly used for two things: clamping texture
access for FBO rendering, and limiting the used mipmap levels when
incrementally loading textures. By restricting our mipmap trees to
just the current BaseLevel/MaxLevel, we caused reallocation thrashing
in the common case, for a theoretical win if someone really did want
just levels 2..4 or whatever of their texture object.
Bug #30366
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 01b70c06284f3a0ab2de61228b73c78ed00a1a14 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop unused first/lastlevel args to miptree_create_for_region.
We're always making a single-level, 0-baselevel miptree.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| b917691bc015ec4a148a67bf3a1cdca0248400a7 |
|
25-Sep-2010 |
Eric Anholt <eric@anholt.net> |
intel: Improve some of the miptree debugging.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 9087ba128089ed0dc00e6eb38f37126fb7557d3b |
|
04-Jun-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Take an intel_screen pointer in intel_alloc_region_* functions
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| c374487a54aca2dd1053645092367c1cf0414ef7 |
|
11-Aug-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove include of texmem.h, since we haven't used it in ages.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 84178547dfaa27ca298ad1755d1ce686036a8550 |
|
17-Jun-2010 |
Vinson Lee <vlee@vmware.com> |
intel: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 178414eba402f9087ea505e7ef19f1becdd7a36d |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove caching of surface state objects.
It turns out that computing a 56 byte key to look up a 20-byte object
out of a hash table was some sort of a bad idea. Whoops.
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 37.799 38.203 0.39% 6/6
after:
[ 0] gl firefox-talos-gfx 34.761 34.784 0.17% 5/6
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 453f0b1f243b26e02b371293e9c8bbf09362c14a |
|
05-May-2010 |
Eric Anholt <eric@anholt.net> |
intel: Don't tile textures so small that size is blown up by over 2x.
Noted on the mailing list for an app that puts each glyph for its text
into a separate texture.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 6422cf387baef75df9e5dbbed5cea4c0f495fe41 |
|
22-Mar-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Call intel_prepare_render() before looking up regions.
Fixes #27213.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 362c1bf75eb74de5b4655c481b74f79718ed4a34 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Replace mt->pitch with mt->region->pitch.
The pitch is not really an inherent part of the miptree, since it's
not part of any of the layout calculations, and it's dictated by the
libdrm-allocated region pitch now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| da011faf48155a5c02ebc1fe1fa20a4f54b8c657 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Rely on allocated region pitch for the miptree pitch.
Bug #26966: 945 miptree pitch disagreement with libdrm.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 0c51390e4b5e04b992e50fcbed751024e6c329de |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove level_offset now that it's unused.
This is the last pitch-dependent part of miptree setup.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| a589da14dee0c2a32e6e529f1a390b01a3ee4001 |
|
16-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix inversion for glCopyPixels to/from FBOs.
fixes piglit fbo-copypix.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| bb35000b4b6dfe60048b2f5d60bc102c4a7fd791 |
|
05-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-kernel-exec-fencing support.
Shaves 60k off the driver from removing the broken spans code. This
means we now require 2.6.29, which seems fair given that it's a year
old and we've removed support for non-KMS already in the last release
of 2D.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 07439cf61717a3bde82745aa2acc878d7fd0133f |
|
03-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i915: Don't do the pitch expansion for tiled buffers.
The weirdness that led to the bumping of pitch for those 512/1024
pixels is that in taking a 2x2 subspan or bilinear filtering we'd end
up hitting the same channel in 2 different pages, leading to lower
performance. With tiling, that doesn't occur, so we don't need to
waste the memory.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| c6e26d76c7f59b51be00c960112c85ad4b3d2334 |
|
31-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
intel: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| f67748038935e609aa85450b20d550b4813c9429 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace some gen3 IS_* checks with context structure usage.
Shaves 400 bytes or so from i915_dri.so.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-GEM support.
This really isn't supported at this point. GEM's been in the kernel for
a year, and the fake bufmgr never really worked.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 1166294d1dd253da63620235100a11f1981aa86d |
|
05-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Finish removing the fallback code for bug #16697.
I fixed it properly as of 7216679c1998b49ff5b08e6b43f8d5779415bf54.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 8f30ceaaefc33401b08739a16ce1c5638d6432fa |
|
04-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove duplicated arguments from intel_miptree_match_image().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| caf3038123d6d29afd7d1f0cd6db98a2282c3ca1 |
|
26-Oct-2009 |
Eric Anholt <eric@anholt.net> |
Make a convenient int for what chipset generation we're on.
gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc",
and compares on generation are often easier than stringing together a bunch
of chipset checks.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 1f196b786d6bd0c6a5dbdc638574ff716cc3d4de |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'texformat-rework'
Conflicts:
src/mesa/drivers/dri/radeon/radeon_fbo.c
src/mesa/drivers/dri/s3v/s3v_tex.c
src/mesa/drivers/dri/s3v/s3v_xmesa.c
src/mesa/drivers/dri/trident/trident_context.c
src/mesa/main/debug.c
src/mesa/main/mipmap.c
src/mesa/main/texformat.c
src/mesa/main/texgetimage.c
|
| 7d56caabe45e91a67096804c7e341d04d01db7aa |
|
28-Oct-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
Conflicts:
src/mesa/shader/lex.yy.c
src/mesa/shader/program_lexer.l
|
| a7d0665c00053839065592c339bfb298187a82be |
|
28-Oct-2009 |
Vinson Lee <vlee@vmware.com> |
intel: Fix memory leak in event of mip tree allocation failure
Signed-off-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 49d402e275cdaf46de8db5a475dfe00509141195 |
|
23-Oct-2009 |
Eric Anholt <eric@anholt.net> |
Merge remote branch 'origin/mesa_7_6_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_fbo.c
src/mesa/drivers/dri/intel/intel_mipmap_tree.c
src/mesa/drivers/dri/intel/intel_mipmap_tree.h
src/mesa/drivers/dri/intel/intel_tex_copy.c
src/mesa/drivers/dri/intel/intel_tex_image.c
|
| 2d17dbfb5346b6d75e87c839148cbe125bf5cd6d |
|
09-Jul-2009 |
Eric Anholt <eric@anholt.net> |
intel: Keep track of x,y offsets in miptrees and use them for blitting.
By just using offsets, we confused the hardware's tiling calculations,
resulting in failures in miptree validation and blit clears.
Fixes piglit fbo-clearmipmap.
Bug #23552. (automatic mipmap generation)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 47a7535f413d6467082de224f64eecc046227406 |
|
13-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: whitespace/formatting clean-up
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 3732d0a77d2cbae50874f5a4ebdb3d8f06021a57 |
|
13-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: replace extern decl with #include
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| c932e21fa848562325f666dce5db3b09bc61bffa |
|
13-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: code clean-ups
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| e6594a22f298833eeb6881795b24d03d2fd8e898 |
|
13-Oct-2009 |
Brian Paul <brianp@vmware.com> |
intel: pass zslice to intel_miptree_image_offset()
This lets us get rid of intel_miptree_depth_offsets() and simplify all
of the calling code.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| b6bdafdf2cf1110b4a5ca7cf9e1c3dcb124b800f |
|
02-Oct-2009 |
Brian Paul <brianp@vmware.com> |
mesa: remove gl_texture_image::IsCompressed field
Use _mesa_is_format_compressed() instead.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 1f7c914ad0beea8a29c1a171c7cd1a12f2efe0fa |
|
01-Oct-2009 |
Brian Paul <brianp@vmware.com> |
mesa: replace gl_texture_format with gl_format
Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum.
ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x.
gl_texture_format will go away next.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 49fbdd18ed738feaf73b7faba4d3577cd9cc3e59 |
|
12-Feb-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix massive memory allocation for streaming texture usage.
Once we've freed a miptree, we won't see any more state cache requests
that would hit the things that pointed at it until we've let the miptree
get released back into the BO cache to be reused. By leaving those
surface state and binding table pointers that pointed at it around, we
would end up with up to (500 * texture size) in memory uselessly consumed
by the state cache.
Bug #20057
Bug #23530
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 9fbb8884f034e0d691fed0e099d4d796f3b42848 |
|
28-Sep-2009 |
Brian Paul <brianp@vmware.com> |
mesa/drivers: use _mesa_get_format_bytes()
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 5e6b593d35156a0068dc0eb3e55dec086f1cadd3 |
|
01-Jul-2009 |
Eric Anholt <eric@anholt.net> |
intel: Avoid pointer arithmetic on void *.
Bug #22000.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 9c0ba017c8ff7caafc3ff94da3c035e687231596 |
|
23-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix depth-texture Y-tiling detection for sized internal formats.
Fixes assertion failure on norsetto shadow mapping demo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| e0a4e25f938953201fef2bf702e2e709451200f4 |
|
23-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix packed depth/stencil textures to be Y-tiled as well.
Fixes shadowtex.c. And an assert is added to catch this sooner next time.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 8f81a6468fdbc7320800ea497791e3e1b8f782ca |
|
22-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Avoid trying to do blits to Y tiled regions.
This is somewhat nasty, but we need to do Y-tiled depth for FBO support.
May help with corruption and hangs since enabling texture tiling, and
since switching depth textures to Y tiled.
Fixes piglit depthtex.c on 965.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 246d59c29e3e5a57dcf2f60ad429eb1606193ef0 |
|
22-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Fix some potential writes to zero-copy PBOs when used as regions.
I was in the midst of fixing some blitting-with-Y-tiled issues when I
noticed this. Hopefully PBO usage will be a little more robust, as a
result.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| bd10f0e84f1491363d76d92dcbd410ab5cc43dbe |
|
12-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix tiling for FBO depth attachments by making DEPTH_COMPONENT Y tiled.
This may hurt if miptree relayout occurs, since we can't blit Y tiled
objects. But it corrects depth tests on FBOs using textures.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e |
|
03-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 1d112207716774b32c0cc846304c2c50bf40e812 |
|
08-May-2009 |
Robert Ellison <papillo@vmware.com> |
i965: improve debug logging
Looking for memory leaks that were causing crashes in my environment
in a situation where valgrind would not work, I ended up improving
the i965 debug traces so I could better see where the memory was
being allocated and where it was going, in the regions and miptrees
code, and in the state caches. These traces were specific enough
that external scripts could determine what elements were not being
released, and where the memory leaks were.
I also ended up creating my own backtrace code in intel_regions.c,
to determine exactly where regions were being allocated and for what,
since valgrind wasn't working. Because it was useful, I left it in,
but disabled and compiled out. It can be activated by changing a flag
at the top of the file.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 40dd024be618d805b3744e15d25e115018641324 |
|
18-Feb-2009 |
Eric Anholt <eric@anholt.net> |
intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.
This lets us avoid allocing new buffers for renderbuffers, finalized miptrees,
and PBO-uploaded textures when there's an unreferenced but still active one
cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded
textures. The size of BOs allocated for a desktop running current GL
cairogears on i915 is cut in half with this.
Note that this means we require libdrm 2.4.5.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| e72a44215312ae1f3c812ba28e47b4aec3589de9 |
|
12-Dec-2008 |
Pierre Willenbrock <pierre@pirsoft.de> |
intel: Don't steal renderbuffer from caller in intel_miptree_create_for_region
Fixes double-frees of some regions, once from the renderbuffer code and
once from the miptree itself.
Bug #19062
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 8b69c42b356d51c3a37bc0af41738b016c2adc5b |
|
12-Dec-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
intel: check for null texture. (fix #13902)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 8db761409dadc2e899d4e7107eff3aa07b07aa11 |
|
13-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Add a width field to regions, and use it for making miptrees in TFP.
Otherwise, we would use the pitch as width of the texture, and compiz would
render the pitch padding on the right hand side.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| e438827dec5a3aafa04e13caf5988f359c004249 |
|
18-Aug-2008 |
Henri Verbeet <hverbeet@gmail.com> |
fix byte vs. pixel offset bug for 3D textures (see bug 17170)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| b4b7326717d3253656f9702fc04f06f8d210a6aa |
|
18-Jul-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
intel: fix texture border issue. (bug #16697)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| d12fa3511da23d8285f3ea1a51a1f328cdbb1462 |
|
30-Apr-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
intel: test cpp to ensure mipmap tree matches texture image.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| e5f50f2fa32c50807da3a8f13733f0fbc7868f94 |
|
19-Mar-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Clarify miptree layout by using byte offsets to images.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 4a556bcb17b8b0dd9ba4ef6eccbb3cfb2ad6a025 |
|
17-Mar-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
intel: fix the error in commit 7ed1fd5d8438e55fe24091844cdfccb0881306bc
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 7ed1fd5d8438e55fe24091844cdfccb0881306bc |
|
17-Mar-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
intel: Remove an assertion from intel_miptree_create. TexImage
call with zero width/height/depth matches GL spec.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 36c26d321b5d17902f0e8f531654dfb2fe2bdd2d |
|
04-Mar-2008 |
Kristian Høgsberg <krh@redhat.com> |
[intel] Silence unused variable warning when compiling for i965.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 0da03c0aa9ed120fe5ff781a365b503b8ed70e0c |
|
28-Feb-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[intel] fix compressed image height
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 9bd2cb7f90ac434ec5be7d388f899976bf902dc1 |
|
26-Feb-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i915] fix texture size exceed limit case when running celestia
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 1d14da9a89e8d7f49b754ca1f24cb062a261a7e7 |
|
25-Feb-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[intel] fix random ut2004 crash on some machine, for cubemap textures,
image offset is already considered when map, add it again in
StoreImage may lead to wrong result and crash.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 6d48779c7e5c9002d1bec4b1266ca05a474218ef |
|
15-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
Add TTM buffer object based texture from pixmap implementation.
Currently only implemented for intel hw.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 3956597962dcf6c8082541199ebac58e0d84f6bc |
|
29-Dec-2007 |
Roland Scheidegger <sroland@tungstengraphics.com> |
Bug #13839: Fix 3D texture offset miscalculation with pixels versus bytes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 101abee6c4fc2c9284ff2ba6f9f9138327d6963d |
|
19-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Fix and reenable (software) SGIS_generate_mipmap
The core problem was that _mesa_generate_mipmap was not respecting RowStride
of the source image. Additionally, the intel private data associated with the
images (level and face) was not being initialized for the
_mesa_generate_mipmap-generated images.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| a183efc132c8db1bb42525ac177ffff96f69a59b |
|
18-Dec-2007 |
Keith Packard <keithp@keithp.com> |
[Intel] Centralize mipmap pitch computations.
mipmap pitches must account for the device alignment requirements, which
used to be fairly simple; just align to a 4-byte boundary. However, to allow
textures to be drawn to under TTM, they now need to be aligned to a 64-byte
boundary. Placing all of the alignment constraints in a single function
allows this new constraint to be applied uniformly.
There was some pitch constraining code in intel_miptree_create, but that was
modifying the pitch long after the miptree had been layed out, so it only
served to wreck the mipmap and cause rendering errors.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| d913a15898fc8edc68ee673e2ae038cf2d7e8af9 |
|
16-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[i915] Fix missing symbol from 965 changes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| c0b4257aa9ba783674ccf7162799385734dff211 |
|
16-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Move to using shared texture management code.
This removes the delayed texture upload optimization from 965, in exchange for
bringing us closer to PBO support. It also disables SGIS_generate_mipmap,
which didn't seem to be working before anyway, according to the lodbias demo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 659baa3f25275b622dad626992af60f3c9ea6d66 |
|
15-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Whitespace and comment changes to bring intel_mipmap_tree.c closer.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 7c71ef3a3d0cf2620525f468960cdc76a0fb0d33 |
|
12-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|
| 77a5bcaff43df8d54e0e0ef833726e4b41d7eb36 |
|
07-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move over files that will be shared with 965-fbo work.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
|