| d796955a5f4639769cd919935f8773def641d66f |
|
24-Jul-2015 |
hding3 <haitao.ding@intel.com> |
psb_video[VPP]: Use aligned height for YUV image height parameter
Bug: 22618392
Read YUV data align with decoder output.
This means UV data are stored at the offset of alight height instead of video height.
Change-Id: I80b54adc23096bc6eade86807db01c1fb1ec6c4c
Signed-off-by: hding3 <haitao.ding@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 51886a2b03b20de77dac773a69bc280064e5543f |
|
27-Jan-2015 |
Elliott Hughes <enh@google.com> |
am 5526ee63: <string.h>? No, <strings.h>.
* commit '5526ee6314de2723fa8f651dec2ff337e4c7a7da':
<string.h>? No, <strings.h>.
|
| 5526ee6314de2723fa8f651dec2ff337e4c7a7da |
|
27-Jan-2015 |
Elliott Hughes <enh@google.com> |
<string.h>? No, <strings.h>.
Who still uses bzero anyway?
Change-Id: Ia6f3c406c18b01c44881686b807b04f9bf62abe5
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| f67eadb89cf8bea6b2871766ae3560958d98bc0b |
|
27-Jan-2015 |
Elliott Hughes <enh@google.com> |
am 7d8048d2: Add missing <string.h> include.
* commit '7d8048d2853335f06ddd71539830cfc2a270585e':
Add missing <string.h> include.
|
| 7d8048d2853335f06ddd71539830cfc2a270585e |
|
27-Jan-2015 |
Elliott Hughes <enh@google.com> |
Add missing <string.h> include.
Change-Id: Ie6ba07b09a2f357370a2aa1195762e7b48bdc10d
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| d640886ce44885e2a70f4d31187d17f4ce08d52d |
|
22-Nov-2014 |
Xigui Wang <xigui.wang@intel.com> |
Fix share info initialization issue when enabling VPP/FRC
add a flag to indicate share_info initilization state
Bug: 18629797
BZ: 230329
Change-Id: Ifd452233049a26d00742f59e0af9f624295fbdcb
Signed-off-by: Jason Hu <jason.hu@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 02f3955632048eb112d521f9c8e80ab2c911598a |
|
14-Nov-2014 |
Xigui Wang <xigui.wang@intel.com> |
Support YV12 format for ISV functions
In current design, all YUV420 surface will be handled with VA_FOURCC_NV12.
The correct pixel format will be saved in extra_info[8].
VSP driver will indentify YV12 format with extra_info[8].
BZ: 229811
Bug: 17383204
Change-Id: I405b37bbac273e611b7415781b6dc586808b78ba
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| d50cf45fbdb02245b8d45b14935fc5f2f4575653 |
|
14-Nov-2014 |
Thierry Strudel <thierry.strudel@intel.com> |
Enable VSP driver
1. builds VSP vpp files.
2. remove dependency on libvpp
3. Remove the limitation of va surface can't be NULL when vaCreateContext
4. Fix a multiple thread issue when vaCreateSurfaces
When try to invoke gralloc_lock for the same native handle from different
thread, will return lock err.
Add a interface lock to protect the access to native handle.
5. Remove the compiling warning for VPP/VP8.
Update the data structure for parameters
Add "unused" attribute for unused function parameter.
7. Add flag in vaCreateSurfaces2 to explicit set NOT initialized share info
when creating surfaces.
8. Copy VPP input share info to output
Bug: 17383204
BZ: 227971
Change-Id: I6cfe01494d12f8704145294d391f4241801b05f6
Signed-off-by: Xigui Wang <xigui.wang@intel.com>
Signed-off-by: pingshix <pingx.shi@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| b35344f5c0b8568df0630efe9fce076e810de8d3 |
|
10-Oct-2014 |
ywan171 <yi.a.wang@intel.com> |
add vsp vp8 encoder into build
Bug: 17783054
BZ: 225951
Change-Id: Ic0883ff983c2b34ac7c7c104ce312d5bf33bf405
Signed-off-by: ywan171 <yi.a.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| e982f1e85b688d56a63c7e352281a182753f1e7b |
|
06-May-2014 |
Wang Kun <kun.k.wang@intel.com> |
Support VSP Security Compose
BZ: 192662
Support WIDI Security Compose feature.
Change-Id: Id2cd8eb649c13a3919fccb876d145feb67c33023
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| e577a6436873cb07cdbd9e98b7ceccf3a558cf5f |
|
21-Mar-2014 |
Wang Kun <kun.k.wang@intel.com> |
Compile the VPP rotation codes only for MRFLD.
BZ: 180839
In current codes, the VPP rotation codes are shared by MRFLD and MOFLD.
Use the macro to make sure these codes just be used by MRFLD.
Change-Id: I596459cd10d91d56515ab6a095b822d927c7fdad
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 208fdf0dfa4973738828afe4c0fee995d1c5079c |
|
07-Jan-2014 |
Wang Kun <kun.k.wang@intel.com> |
Use VSP to do rotation for 1080P while vpp playback
BZ: 145877
In current design, GPU will do rotation for VPP output data.
To reduce the power, VPP will do rotation for 1080P.
Change-Id: Ic44e2aa7b801d89400a9f5e9e4c9a86e73c5d723
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| d8c30d116941527fe7c43c89052741ec6ee913eb |
|
19-Dec-2013 |
Wang Kun <kun.k.wang@intel.com> |
Update the VPP/FRC codes to match VIED 2.11 release
BZ: 158236
Remove the VSP Context allocation. VSP will use IMR memory.
Send the InitContext command to VSP before the first command.
Send the DestoryContext command after the last command.
Change-Id: Ic4ede1c6c9766a8727c0b240f7af154e3073aaa2
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 3702abf72fd9b97c7432c53e5bbf70429ed3b511 |
|
26-Dec-2013 |
Shi, PingX <pingx.shi@intel.com> |
Revert "Update the VPP/FRC codes to match VIED 2.11 release"
BZ: 158236
This reverts commit daca8d90a8dd026ab235bc5e31e9ca2f46f63cf4.
Change-Id: I4dbd97816b4a30106edb3441a0d18e3a0b96406b
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 1ec3ea79d9ca6b7e0d31865dc264db870bcf7f8a |
|
19-Dec-2013 |
Wang Kun <kun.k.wang@intel.com> |
Update the VPP/FRC codes to match VIED 2.11 release
BZ: 158236
Remove the VSP Context allocation. VSP will use IMR memory.
Send the InitContext command to VSP before the first command.
Send the DestoryContext command after the last command.
Change-Id: I0bb3069f16573e43c8bef94803ae563bb6ec8f0c
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 3a06cac9739f834b59d88bbcfb9c95229117a204 |
|
19-Nov-2013 |
Wang Kun <kun.k.wang@intel.com> |
Update the VSP codes to match VIED 2.10 release
BZ: 152881
Set the intermediate buffer addr/size on Pipeline command.
Update the context buffer to 60KB
Change-Id: I37a237825cc147cbb8c261d464809e5c72e3158e
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 0e1ed1e239c04f2c34edd6252ed1b16f11980aab |
|
29-Nov-2013 |
Yu, Linda <linda.yu@intel.com> |
Revert "Support FRC2.5X 25fps to 62fps"
BZ: 153934
Do 2.5X FRC for 25fps input causes stuttering issue, change to do 2X FRC
for 25fps input.
Change-Id: I8f84b6bae643c46b3540f0ddfafabb10a7cd8aed
Signed-off-by: Yu, Linda <linda.yu@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| e6042d7a5abe6944724bc103e8fbf85082debdee |
|
21-Nov-2013 |
Wang Kun <kun.k.wang@intel.com> |
Get the tiling flag from input surface for VSP
BZ: 151363
Set the VSP tiling through input surface's tiling flag instead of surface's width
Change-Id: I3d496991b4f06de87db39262e412594e57bcc00b
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| cc8aa4f7024f27e95efcf5c082b3c8246e163003 |
|
31-Oct-2013 |
Wang Kun <kun.k.wang@intel.com> |
Support FRC2.5x 25fps to 62 fps
BZ: 147482
For FRC filter, 25->62 for FRC2.5x should be supported.
Change-Id: I9f0ecc5c667316d4a2e0f947a3e431042ccc9b46
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| c8e206f338238963120ea9f3f0515329cb791d11 |
|
19-Aug-2013 |
Wang Kun <kun.k.wang@intel.com> |
Use the HighQuality option for VPP FRC filter parameter.
BZ: 131567
Set the FRC quality to VssFrcHighQuality.
Change-Id: I7142736df3520fb5460475b8a8db0eba9489328e
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/126144
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: cactus <cactus@intel.com>
Tested-by: cactus <cactus@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 76777b6108cd39192cba113f96b04b98eee39c73 |
|
14-Aug-2013 |
Wang Kun <kun.k.wang@intel.com> |
Update the width of output frame to multiple of 16 for VPP
BZ: 124876
adjust the VPP output width to multiple of 16.
Update the max height to 1088 to support 1080P tiling.
Change-Id: I98a432a8eeff02f7ccac34d4b3f06d4d54277db9
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/125865
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: cactus <cactus@intel.com>
Tested-by: cactus <cactus@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 8672be7b10df4af6bd6e0902f6588ab4f7599176 |
|
19-Jun-2013 |
Sun, Mingruo <mingruo.sun@intel.com> |
set context_id=1 for vp8 enc to support context switch with VPP
BZ: 117413
set context_id=1 and then pass its value to firmware
Change-Id: I300babdf7104171d34617714a4626c3b571de035
Signed-off-by: Sun, Mingruo <mingruo.sun@intel.com>
Reviewed-on: http://android.intel.com:8080/115746
Reviewed-by: cactus <cactus@intel.com>
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 46a74932d7ffe581e724385891c0aa26df9b48a9 |
|
08-Jun-2013 |
Li Zeng <li.zeng@intel.com> |
VSP: use different macro to define VSP tiling support
BZ: 104287
use different macro to define VSP tiling support
Change-Id: Ic4ebec8243cd71733370cb6dacff54dcfbfe8c07
Signed-off-by: Li Zeng <li.zeng@intel.com>
Reviewed-on: http://android.intel.com:8080/112500
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 0b79338c7b34af6f2baade29264bcf27cab80e83 |
|
03-May-2013 |
Wang Kun <kun.k.wang@intel.com> |
Fix the VSP clock work issues.
BZ: 105405
Fix the VSP clock work issues.
Change-Id: Ib2215bcdf644162dadaa17be9f228fc8a0412a77
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/106250
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: cactus <cactus@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 7009de6747301310514dcdb7c286d0d0790a0ae5 |
|
19-Apr-2013 |
Wang Kun <kun.k.wang@intel.com> |
VSP support tiling feature for 1080P on MRFL.
BZ: 101907
The vsp tiling codes are added by marco PSBVIDEO_MSVDX_DEC_TILING
It's disabled by default, because Decode hasn't support it yet.
Change-Id: Ib2d3a19cda724871152289e3162f17573e4eb1cb
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/103744
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: cactus <cactus@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 5d69fca537b4dd301c586b988129305fa60f1c06 |
|
08-Mar-2013 |
Wang Kun <kun.k.wang@intel.com> |
Update the VSP codes to match VIED 1.10 release.
BZ: 91558
Support VSP tiling and FRC 1.25x support.
Update the Deblock parameters tables.
Change-Id: I6b46748e21077a4f5a24723e74beb3e13321d82d
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/95748
Reviewed-by: cactus <cactus@intel.com>
Reviewed-by: Wang, Lili A <lili.a.wang@intel.com>
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 4b8982ecb6744203ae0b5381942d72a518539661 |
|
28-Dec-2012 |
Wang Kun <kun.k.wang@intel.com> |
Update the VSP to match the VIED 1.7 version[Video-MRFLD]
BZ: 77426
The new function is rotation.
It's disabled in our vsp code because the final solution is discussing.
Change-Id: Ibfd8659d8b0244c38a32e12d2cd519de1abe6c2a
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/84189
Reviewed-by: Wang, Lili A <lili.a.wang@intel.com>
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: cactus <cactus@intel.com>
Tested-by: cactus <cactus@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 36b2fec53dda9155f2a93eb75f7fe2b7c63d3941 |
|
05-Dec-2012 |
Wang Kun <kun.k.wang@intel.com> |
[PORT FROM MAIN]Remove the VPP filter pipeline check.[MRFLD-VIDEO]
BZ: 72833
After discussed with architecture, the psb_video VPP driver should expose the individual filters.
Change-Id: Ieac032ccd4851059308acd054bf3088451a28769
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/81247
Reviewed-by: Ding, Haitao <haitao.ding@intel.com>
Tested-by: Ding, Haitao <haitao.ding@intel.com>
Reviewed-by: cactus <cactus@intel.com>
Tested-by: cactus <cactus@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 66304487373cf4ed335ba2614f00102dca837832 |
|
30-Oct-2012 |
Wang Kun <kun.k.wang@intel.com> |
Update the codes to support VIED 20121005 version[MRFLD-VIDEO]
BZ: 64638
Update the VIED filter parameters value.
Change-Id: I6029287eb1f0b80cd5a50ac94a25a15ffe6c7dd3
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/72115
Reviewed-by: Wang, Lili A <lili.a.wang@intel.com>
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| d9dce27af5a91d19aaf1f2113a4a8ac4a9f9540b |
|
29-Sep-2012 |
Wang Kun <kun.k.wang@intel.com> |
[MRFLD-VIDEO] Check the array size for VSP function parameters.
BZ: 59972
Add codes to check the array size to avoid overflow.
Add more comments for some functions.
Change-Id: Ia34e94d8549e80ffb82dc8695ff23cc6e17d0761
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/68468
Reviewed-by: Wang, Lili A <lili.a.wang@intel.com>
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 55e0621b21e3aba148d9f959f8a3da329308431a |
|
20-Sep-2012 |
Wang Kun <kun.k.wang@intel.com> |
[MRFL-Video]Use the frame height as the condition for VPP command pipeline
BZ: 58274
We should use the height as the condition to classify the frame type.
Change-Id: Idaa5e5c4facc8ded42238766fae02d6fcbefcbdb
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/67165
Reviewed-by: Wang, Lili A <lili.a.wang@intel.com>
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 38cd6d452193ef0f00bc831464af672aa8fed3b9 |
|
05-Sep-2012 |
Wang Kun <kun.k.wang@intel.com> |
Return the correct ERROR value for VSP functions [MRFLD-VIDEO].
BZ: 55642
Return the correct ERROR value for different parameters checking
Change-Id: I20a2f7db85c14223802e40f02aacf03626860058
Signed-off-by: Wang Kun <kun.k.wang@intel.com>
Reviewed-on: http://android.intel.com:8080/64521
Reviewed-by: Feng, Wei <wei.feng@intel.com>
Reviewed-by: Tang, Richard <richard.tang@intel.com>
Reviewed-by: Wang, Elaine <elaine.wang@intel.com>
Reviewed-by: Wang, Lili A <lili.a.wang@intel.com>
Reviewed-by: Shi, PingX <pingx.shi@intel.com>
Tested-by: Shi, PingX <pingx.shi@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| c7434a3fdc05f13a1817b6f32f499c9c7fee0045 |
|
13-Sep-2012 |
hding3 <haitao.ding@intel.com> |
Update the VSP to VIED 0711 release [MRFLD-VIDEO].
BZ: 51921
VAProfileNone was updated to -1 on libva, so we need to add a new vpp_profile for only VSP.
Add the support to query the filters capability for different frame.
Change-Id: I1604e9d6dea66b48cb6e123b970f16f7efe3c24b
Signed-off-by: hding3 <haitao.ding@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| fc84bd8b6852aff0a3f70c4f21533ce36e1937be |
|
09-Sep-2012 |
hding3 <haitao.ding@intel.com> |
merrifiled code checkin for h264 encoder, vp8 decoder features [MRFLD-VIDEO].
BZ: 45158 45385 45609 42748 45878
(1) BZ45158 updated Merrifield video encoder user space driver
(2) modify the stride assignment, widi needed
(3) modify CMD_DMA_DMA_TYPE_SHIFT according to 1366FW and some errors after refine VP8 code
(4) BZ45385 Video: Enable VP8 decode with msvdx fw 1366ss on FPGA
(5) BZ45609 added the check for array's boundary
(6) BZ42748 The reconstructed frame is not supported well
(7) Support the Deblock filter while do capability check
(8) BZ45878 Merrifield H264 encoder does not support changing bitrate dynamically under VCM mode
Change-Id: Ib2c5d66dcd4cc741ec25c3632f37aa241cd52e2a
Signed-off-by: hding3 <haitao.ding@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|
| 8e9a21e730449c10cac6e6f69d255611c93f63c2 |
|
13-Sep-2012 |
hding3 <haitao.ding@intel.com> |
porting MRFL branch to ICS mainline [MRFLD-VIDEO].
BZ: 35390
porting MRFL branch to ICS mainline.update version r7.
Change-Id: Ia48689ead949f44d32817d062accab06b1ecd3a6
Signed-off-by: hding3 <haitao.ding@intel.com>
/hardware/intel/img/psb_video/src/vsp_VPP.c
|