/external/llvm/lib/CodeGen/ |
H A D | AntiDepBreaker.h | 57 /// other machine instruction to use NewReg. 58 void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) { argument 61 MI->getOperand(0).setReg(NewReg);
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H A D | CriticalAntiDepBreaker.cpp | 319 // be replaced by NewReg. Return true if any of their parent instructions may 324 // the two-address instruction also defines NewReg, as may happen with 328 // both NewReg and AntiDepReg covers it. 332 unsigned NewReg) 338 // operands, in case they may be assigned to NewReg. In this case antidep 343 // Handle cases in which this instruction defines NewReg. 348 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) 352 CheckOper.getReg() != NewReg) 355 // Don't allow the instruction to define NewReg and AntiDepReg. 361 // NewReg 330 isNewRegClobberedByRefs(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned NewReg) argument 384 unsigned NewReg = Order[i]; local [all...] |
H A D | MachineCSE.cpp | 541 unsigned NewReg = CSMI->getOperand(i).getReg(); local 550 if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg) 553 if (OldReg == NewReg) { 559 TargetRegisterInfo::isVirtualRegister(NewReg) && 562 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) { 571 if (!MRI->constrainRegClass(NewReg, OldRC)) { 577 CSEPairs.push_back(std::make_pair(OldReg, NewReg)); 585 unsigned NewReg = CSEPairs[i].second; local 587 MachineInstr *Def = MRI->getUniqueVRegDef(NewReg); 589 Def->clearRegisterDeads(NewReg); [all...] |
H A D | TailDuplication.cpp | 89 void AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, 379 void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, argument 383 LI->second.push_back(std::make_pair(BB, NewReg)); 386 Vals.push_back(std::make_pair(BB, NewReg)); 441 unsigned NewReg = MRI->createVirtualRegister(RC); local 442 MO.setReg(NewReg); 443 LocalVRMap.insert(std::make_pair(Reg, NewReg)); 445 AddSSAUpdateEntry(Reg, NewReg, PredBB);
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H A D | PeepholeOptimizer.cpp | 801 /// \brief Rewrite the current source with \p NewReg and \p NewSubReg 804 virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) { argument 808 MOSrc.setReg(NewReg); 1005 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override { 1010 MO.setReg(NewReg); 1054 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override { 1059 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg); variable 1133 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override { 1140 MO.setReg(NewReg);
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H A D | TwoAddressInstructionPass.cpp | 738 unsigned NewReg = 0; local 741 NewReg, IsDstPhys)) { 751 VirtRegPairs.push_back(NewReg); 754 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second; 756 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!"); 757 VirtRegPairs.push_back(NewReg); 758 Reg = NewReg;
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H A D | RegisterCoalescer.cpp | 681 unsigned NewReg = NewDstMO.getReg(); local 682 if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill()) 746 UseMO.setReg(NewReg); 756 if (TargetRegisterInfo::isPhysicalRegister(NewReg)) 757 UseMO.substPhysReg(NewReg, *TRI); 759 UseMO.setReg(NewReg);
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/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyPeephole.cpp | 76 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local 77 MO.setReg(NewReg); 79 MFI.stackifyVReg(NewReg); 80 MFI.addWAReg(NewReg, WebAssemblyFunctionInfo::UnusedReg);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64DeadRegisterDefinitionsPass.cpp | 110 unsigned NewReg; local 116 NewReg = AArch64::WZR; 119 NewReg = AArch64::XZR; 123 MO.setReg(NewReg);
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/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 282 MCOperand NewReg; local 287 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( 289 NewMI.addOperand(NewReg);
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/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 658 unsigned NewReg = optimizeSDPattern(MI); local 660 if (NewReg != 0) { 666 // reference into a plain DPR, and that will end poorly. NewReg is 669 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg())); 673 << PrintReg(NewReg) << "\n"); 674 (*I)->substVirtReg(NewReg, 0, *TRI); 677 Replacements[MI] = NewReg;
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H A D | ARMBaseRegisterInfo.cpp | 279 ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg, argument 294 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 295 if (TargetRegisterInfo::isVirtualRegister(NewReg)) 296 MRI->setRegAllocationHint(NewReg,
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H A D | ARMBaseInstrInfo.cpp | 2738 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg)); local 2741 get(NewUseOpc), NewReg) 2745 UseMI->getOperand(1).setReg(NewReg);
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/external/v8/test/unittests/compiler/ |
H A D | instruction-sequence-unittest.h | 185 VReg NewReg() { return VReg(sequence()->NextVirtualRegister()); } function in class:v8::internal::compiler::InstructionSequenceTest
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngineCXX.cpp | 491 const MemRegion *NewReg = symVal.castAs<loc::MemRegionVal>().getRegion(); local 494 getStoreManager().GetElementZeroRegion(NewReg, ObjTy);
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/external/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 1578 unsigned NewReg = ScratchFPReg; local 1579 duplicateToTop(FirstFPRegOp, NewReg, MI); 1580 FirstFPRegOp = NewReg;
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 586 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords()); variable 587 Elts.insert(NewReg); 593 NewReg->addSuperClass(Supers[i], Ranges[i]); 600 if (NewReg->getValue(RV.getNameInit())) 624 NewReg->addValue(*Def->getValue(Field)); 633 NewReg->addValue(*DefRV); 638 NewReg->addValue(RV);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 1445 unsigned NewReg = MRI.createVirtualRegister(TRC); local 1446 return NewReg;
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 5912 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0, local 5915 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
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