Searched defs:VReg (Results 1 - 25 of 39) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegNumbering.cpp91 unsigned VReg = TargetRegisterInfo::index2VirtReg(VRegIdx); local
93 if (MFI.isVRegStackified(VReg)) {
94 MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++);
98 if (MRI.use_empty(VReg))
100 if (MFI.getWAReg(VReg) == WebAssemblyFunctionInfo::UnusedReg)
101 MFI.setWAReg(VReg, NumArgRegs + CurReg++);
H A DWebAssemblyMachineFunctionInfo.h56 void stackifyVReg(unsigned VReg) { argument
57 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
58 VRegStackified.resize(TargetRegisterInfo::virtReg2Index(VReg) + 1);
59 VRegStackified.set(TargetRegisterInfo::virtReg2Index(VReg));
61 bool isVRegStackified(unsigned VReg) const {
62 if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
64 return VRegStackified.test(TargetRegisterInfo::virtReg2Index(VReg));
68 void setWAReg(unsigned VReg, unsigned WAReg) { argument
70 assert(TargetRegisterInfo::virtReg2Index(VReg) < WARegs.size());
71 WARegs[TargetRegisterInfo::virtReg2Index(VReg)]
82 addWAReg(unsigned VReg, unsigned WAReg) argument
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H A DWebAssemblyRegColoring.cpp62 // Compute the total spill weight for VReg.
65 unsigned VReg) {
67 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg))
99 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); local
100 if (MFI.isVRegStackified(VReg))
103 if (MRI->use_empty(VReg))
106 LiveInterval *LI = &Liveness->getInterval(VReg);
108 LI->weight = computeWeight(MRI, MBFI, VReg);
63 computeWeight(const MachineRegisterInfo *MRI, const MachineBlockFrequencyInfo *MBFI, unsigned VReg) argument
H A DWebAssemblyRegStackify.cpp240 unsigned VReg = MO.getReg(); local
243 if (!TargetRegisterInfo::isVirtualRegister(VReg))
246 if (MFI.isVRegStackified(VReg)) {
248 Stack.push_back(VReg);
250 assert(Stack.pop_back_val() == VReg);
H A DWebAssemblyAsmPrinter.cpp173 unsigned VReg = TargetRegisterInfo::index2VirtReg(Idx); local
174 unsigned WAReg = MFI->getWAReg(VReg);
184 Local.addOperand(MCOperand::createImm(getRegType(VReg).SimpleTy));
/external/llvm/lib/CodeGen/
H A DLiveIntervalUnion.cpp150 LiveInterval *VReg = LiveUnionI.value(); local
151 if (VReg != RecentReg && !isSeenInterference(VReg)) {
152 RecentReg = VReg;
153 InterferingVRegs.push_back(VReg);
H A DCallingConvLower.cpp246 unsigned VReg = MF.addLiveIn(PReg, RC); local
247 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
H A DLiveRangeEdit.cpp35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39 LiveInterval &LI = LIS.createEmptyInterval(VReg);
44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local
46 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
48 return VReg;
352 unsigned VReg = LI->reg; local
354 TheDelegate->LRE_WillShrinkVirtReg(VReg);
364 if (VReg == RegsBeingSpilled[i]) {
379 unsigned Original = VRM ? VRM->getOriginal(VReg)
395 MRI_NoteNewVirtualRegister(unsigned VReg) argument
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H A DMIRPrinter.cpp207 yaml::VirtualRegisterDefinition VReg; local
208 VReg.ID = I;
209 VReg.Class =
213 printReg(PreferredReg, VReg.PreferredRegister, TRI);
214 MF.VirtualRegisters.push_back(VReg);
H A DTailDuplication.cpp246 unsigned VReg = SSAUpdateVRs[i]; local
247 SSAUpdate.Initialize(VReg);
251 MachineInstr *DefMI = MRI->getVRegDef(VReg);
255 SSAUpdate.AddAvailableValue(DefBB, VReg);
260 SSAUpdateVals.find(VReg);
268 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
H A DLiveIntervalAnalysis.cpp489 unsigned VReg = LI.reg; local
490 if (MRI->shouldTrackSubRegLiveness(VReg)) {
493 MI->setRegisterDefReadUndef(VReg);
510 MI->addRegisterDead(VReg, TRI);
513 // the liverange then we rewrite it to use a different VReg to not violate
H A DMachineFunction.cpp469 unsigned VReg = MRI.getLiveInVirtReg(PReg); local
470 if (VReg) {
471 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
481 return VReg;
483 VReg = MRI.createVirtualRegister(RC);
484 MRI.addLiveIn(PReg, VReg);
485 return VReg;
H A DRegAllocPBQP.cpp132 /// \brief Spill the given VReg.
133 void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
298 unsigned VReg = G.getNodeMetadata(NId).getVReg(); variable
299 LiveInterval &LI = LIS.getInterval(VReg);
566 unsigned VReg = Worklist.back(); local
569 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
570 LiveInterval &VRegLI = LIS.getInterval(VReg);
607 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
621 G.getNodeMetadata(NId).setVReg(VReg);
624 G.getMetadata().setNodeIdForVReg(VReg, NI
628 spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals, MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM, Spiller &VRegSpiller) argument
673 unsigned VReg = G.getNodeMetadata(NId).getVReg(); local
815 unsigned VReg = G.getNodeMetadata(NId).getVReg(); local
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/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp66 unsigned VReg = RegNo & 0x0FFFFFFF; local
67 OS << VReg; local
/external/llvm/include/llvm/CodeGen/
H A DLiveIntervalUnion.h125 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): argument
126 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
141 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { argument
142 assert(VReg && LIU && "Invalid arguments");
143 if (UserTag == UTag && VirtReg == VReg &&
150 VirtReg = VReg;
168 bool isSeenInterference(LiveInterval *VReg) const;
H A DScheduleDAGInstrs.h38 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) argument
39 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
50 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, argument
52 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
H A DCallingConvLower.h166 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT) argument
167 : VReg(VReg), PReg(PReg), VT(VT) {}
168 unsigned VReg; member in struct:llvm::ForwardedRegister
H A DMachineRegisterInfo.h178 bool shouldTrackSubRegLiveness(unsigned VReg) const {
179 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
180 return shouldTrackSubRegLiveness(*getRegClass(VReg));
599 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { argument
600 assert(TargetRegisterInfo::isVirtualRegister(VReg));
601 RegAllocHints[VReg].first = Type;
602 RegAllocHints[VReg].second = PrefReg;
607 void setSimpleHint(unsigned VReg, unsigned PrefReg) { argument
608 setRegAllocationHint(VReg, /*Typ
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H A DRegAllocPBQP.h154 void setNodeIdForVReg(unsigned VReg, GraphBase::NodeId NId) { argument
155 VRegToNodeId[VReg] = NId;
158 GraphBase::NodeId getNodeIdForVReg(unsigned VReg) const {
159 auto VRegItr = VRegToNodeId.find(VReg);
165 void eraseNodeIdForVReg(unsigned VReg) { argument
166 VRegToNodeId.erase(VReg);
195 VReg(0)
205 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg),
221 OptUnsafeEdges(std::move(Other.OptUnsafeEdges)), VReg(Othe
260 setVReg(unsigned VReg) argument
320 unsigned VReg; member in class:llvm::PBQP::RegAlloc::NodeMetadata
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp288 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); local
291 if (!VReg) {
294 VReg = MRI->createVirtualRegister(RC);
297 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
298 return VReg;
321 unsigned VReg = getVR(Op, VRBaseMap); local
322 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
330 // shrink VReg's register class within reason. For example, if VReg == GR32
331 // and II requires a GR32_NOSP, just constrain VReg t
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H A DFunctionLoweringInfo.cpp519 unsigned &VReg = I.first->second; local
521 VReg = MRI.createVirtualRegister(RC);
522 assert(VReg && "null vreg in exception pointer table!");
523 return VReg;
/external/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp349 for (const auto &VReg : YamlMF.VirtualRegisters) {
350 const auto *RC = getRegClass(MF, VReg.Class.Value);
352 return error(VReg.Class.SourceRange.Start,
354 VReg.Class.Value + "'");
356 if (!PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID.Value, Reg))
358 return error(VReg.ID.SourceRange.Start,
360 Twine(VReg.ID.Value) + "'");
361 if (!VReg.PreferredRegister.Value.empty()) {
364 VReg.PreferredRegister.Value, PFS,
366 return error(Error, VReg
377 unsigned VReg = 0; local
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/external/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp219 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass); local
220 RegInfo.addLiveIn(VA.getLocReg(), VReg);
221 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
/external/v8/test/unittests/compiler/
H A Dinstruction-sequence-unittest.h23 struct VReg { struct in class:v8::internal::compiler::InstructionSequenceTest
24 VReg() : value_(kNoValue) {} function in struct:v8::internal::compiler::InstructionSequenceTest::VReg
25 VReg(PhiInstruction* phi) : value_(phi->virtual_register()) {} // NOLINT function in struct:v8::internal::compiler::InstructionSequenceTest::VReg
26 explicit VReg(int value) : value_(value) {} function in struct:v8::internal::compiler::InstructionSequenceTest::VReg
30 typedef std::pair<VReg, VReg> VRegPair;
51 TestOperand(TestOperandType type, VReg vreg, int value = kNoValue)
55 VReg vreg_;
59 static TestOperand Same() { return TestOperand(kSameAsFirst, VReg()); }
63 return TestOperand(type, VReg(), inde
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/external/llvm/lib/Target/Hexagon/
H A DHexagonStoreWidening.cpp451 unsigned VReg = MF->getRegInfo().createVirtualRegister(RC); local
452 MachineInstr *TfrI = BuildMI(*MF, DL, TfrD, VReg)
466 .addReg(VReg, RegState::Kill);

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