| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypesGeneric.cpp | 382 EVT VecVT = N->getValueType(0); local
383 unsigned NumElts = VecVT.getVectorNumElements();
388 assert(OldVT == VecVT.getVectorElementType() &&
411 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
422 EVT VecVT = N->getValueType(0); local
423 unsigned NumElts = VecVT.getVectorNumElements();
430 assert(OldEVT == VecVT.getVectorElementType() &&
453 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
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| H A D | LegalizeFloatTypes.cpp | 1941 EVT VecVT = Vec->getValueType(0); local
1942 EVT EltVT = VecVT.getVectorElementType();
1946 switch (getTypeAction(VecVT)) {
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| H A D | LegalizeIntegerTypes.cpp | 1046 EVT VecVT = N->getValueType(0); local
1047 unsigned NumElts = VecVT.getVectorNumElements();
1048 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
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| H A D | LegalizeVectorTypes.cpp | 849 EVT VecVT = Vec.getValueType(); local
850 EVT SubVecVT = VecVT.getVectorElementType();
851 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
857 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
947 EVT VecVT = Vec.getValueType();
948 EVT EltVT = VecVT.getVectorElementType();
949 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
956 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1561 EVT VecVT = Vec.getValueType(); local
1565 assert(IdxVal < VecVT
[all...] |
| H A D | DAGCombiner.cpp | 12436 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
12437 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
12440 if (!isTypeLegal(VecVT)) return SDValue();
12443 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
12752 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SVT, local
12755 DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, Ops));
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 906 EVT VecVT = Vector.getValueType(); local
907 EVT EltVT = VecVT.getVectorElementType();
910 for (unsigned i = 0, e = VecVT.getVectorNumElements();
917 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2830 EVT VecVT = N->getValueType(0); local
2831 EVT EltVT = VecVT.getVectorElementType();
2832 unsigned NumElts = VecVT.getVectorNumElements();
2835 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2839 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2841 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
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| H A D | ARMISelLowering.cpp | 4179 EVT VecVT = EVT::getVectorVT( local
4182 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5505 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); local
5506 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5538 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); local
5542 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
6076 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); local
6077 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
6078 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
6089 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Op
9367 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); local
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2352 EVT VecVT = Vec0.getValueType(); local
2353 unsigned Width = VecVT.getSizeInBits();
2356 MVT ST = VecVT.getSimpleVT();
2413 EVT VecVT = Vec.getValueType(); local
2414 EVT EltVT = VecVT.getVectorElementType();
2429 MVT SVT = VecVT.getSimpleVT();
2448 } else if (VecVT.getSizeInBits() == 32) {
2469 if (VecVT.getSizeInBits() == 32) {
2488 EVT VecVT = Vec.getValueType(); local
2489 EVT EltVT = VecVT
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2155 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, argument
2160 if (VecVT.isFloatingPoint()) {
2183 if (VecVT == MVT::v4f32)
2185 else if (VecVT == MVT::v2f64)
2190 if (VecVT == MVT::v4f32)
2192 else if (VecVT == MVT::v2f64)
2197 if (VecVT == MVT::v4f32)
2199 else if (VecVT == MVT::v2f64)
2227 if (VecVT == MVT::v16i8)
2229 else if (VecVT
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2895 MVT VecVT = MVT::Other; local
2900 VecVT = MVT::v16f32;
2902 VecVT = MVT::v8f32;
2904 VecVT = MVT::v4f32;
2910 if (VecVT != MVT::Other)
2911 RegParmTypes.push_back(VecVT);
4299 MVT VecVT = N->getOperand(0).getSimpleValueType(); local
4300 MVT ElVT = VecVT.getVectorElementType();
4314 MVT VecVT = N->getSimpleValueType(0); local
4315 MVT ElVT = VecVT
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3722 EVT VecVT; local
3728 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32);
3732 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3733 DAG.getUNDEF(VecVT), In1);
3734 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3735 DAG.getUNDEF(VecVT), In2);
3737 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3738 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3742 VecVT = MVT::v2i64;
3750 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
6275 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts); local
[all...] |