/external/llvm/lib/Analysis/ |
H A D | ScalarEvolutionNormalization.cpp | 215 const SCEV *RO = X->getRHS(); local 217 const SCEV *RN = TransformSubExpr(RO, User, OperandValToReplace); 218 if (LO != LN || RO != RN)
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonEarlyIfConv.cpp | 785 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); local 787 SR = RO.getReg(), SSR = RO.getSubReg(); 789 TR = RO.getReg(), TSR = RO.getSubReg(); 791 FR = RO.getReg(), FSR = RO.getSubReg();
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H A D | HexagonGenInsert.cpp | 363 OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {} argument 485 void buildOrderingMF(RegisterOrdering &RO) const; 486 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const; 553 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const { 569 RO.insert(std::make_pair(R, Index++)); 581 RegisterOrdering &RO) const { 593 RO.insert(std::make_pair(VRs[i], i));
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H A D | HexagonExpandCondsets.cpp | 170 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR, 937 /// In the range [First, Last], rename all references to the "old" register RO 940 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, argument 954 if (!Op.isReg() || RO != RegisterRef(Op))
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H A D | HexagonInstrInfo.cpp | 542 const MachineOperand &RO = Cond[1]; local 543 unsigned Flags = getUndefRegState(RO.isUndef()); 544 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB); 565 const MachineOperand &RO = Cond[1]; local 566 unsigned Flags = getUndefRegState(RO.isUndef()); 567 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
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/external/llvm/utils/TableGen/ |
H A D | AsmWriterEmitter.cpp | 850 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; local 852 switch (RO.Kind) { 854 const Record *Rec = RO.getRecord(); 855 StringRef ROName = RO.getName(); 936 MIOpNum += RO.getMINumOperands();
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/external/llvm/tools/llvm-diff/ |
H A D | DifferenceEngine.cpp | 354 Value *LO = L->getOperand(I), *RO = R->getOperand(I); local 355 if (!equivalentAsOperands(LO, RO)) { 356 if (Complain) Engine.logf("operands %l and %r differ") << LO << RO; local
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | RegionStore.cpp | 112 const RegionOffset &RO = R->getAsOffset(); local 113 if (RO.hasSymbolicOffset()) 114 return BindingKey(cast<SubRegion>(R), cast<SubRegion>(RO.getRegion()), k); 116 return BindingKey(RO.getRegion(), RO.getOffset(), k); 1101 const RegionOffset &RO = baseR->getAsOffset(); local 1103 if (RO.hasSymbolicOffset()) { 1111 uint64_t LowerOffset = RO.getOffset();
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/external/deqp/framework/common/ |
H A D | tcuCompressedTexture.cpp | 671 const deUint8 RO = extend6To8((deUint8)getBits(src, 57, 62)); local 687 const int unclampedR = (x * ((int)RH-(int)RO) + y * ((int)RV-(int)RO) + 4*(int)RO + 2) >> 2;
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/external/selinux/policycoreutils/mcstrans/share/examples/nato/setrans.d/ |
H A D | eyes-only.conf | 558 ~c387=RO # Romania
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H A D | rel.conf | 564 ~c200,~c387=RO # Romania
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/external/webrtc/data/voice_engine/stereo_rtp_files/ |
H A D | stereo_g729_jitter.rtp | 451 < |