Searched refs:SU (Results 1 - 25 of 43) sorted by relevance

12

/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp38 /// Check if scheduling of this SU is possible
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { argument
44 if (!SU || !SU->getInstr())
49 switch (SU->getInstr()->getOpcode()) {
51 if (!ResourcesModel->canReserveResources(SU->getInstr()))
75 if (I->getSUnit() == SU)
83 bool VLIWResourceModel::reserveResources(SUnit *SU) { argument
86 if (!SU) {
92 // If this SU doe
184 SUnit *SU = SchedImpl->pickNode(IsTopNode); local
228 releaseTopNode(SUnit *SU) argument
245 releaseBottomNode(SUnit *SU) argument
277 checkHazard(SUnit *SU) argument
288 releaseNode(SUnit *SU, unsigned ReadyCycle) argument
329 bumpNode(SUnit *SU) argument
367 SUnit *SU = *(Pending.begin()+i); local
387 removeReady(SUnit *SU) argument
416 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, PressureChange P) argument
431 getSingleUnscheduledPred(SUnit *SU) argument
449 getSingleUnscheduledSucc(SUnit *SU) argument
474 SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) argument
649 SUnit *SU; local
691 schedNode(SUnit *SU, bool IsTopNode) argument
[all...]
H A DHexagonMachineScheduler.h87 bool isResourceAvailable(SUnit *SU);
88 bool reserveResources(SUnit *SU);
115 SUnit *SU; member in struct:llvm::ConvergingVLIWScheduler::SchedCandidate
123 SchedCandidate(): SU(nullptr), SCost(0) {}
176 bool checkHazard(SUnit *SU);
178 void releaseNode(SUnit *SU, unsigned ReadyCycle);
182 void bumpNode(SUnit *SU);
186 void removeReady(SUnit *SU);
214 void schedNode(SUnit *SU, bool IsTopNode) override;
216 void releaseTopNode(SUnit *SU) overrid
[all...]
/external/llvm/lib/CodeGen/
H A DLatencyPriorityQueue.cpp55 /// of SU, return it, otherwise return null.
56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument
58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
73 void LatencyPriorityQueue::push(SUnit *SU) { argument
77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
84 Queue.push_back(SU);
92 scheduledNode(SUnit *SU) argument
105 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument
134 remove(SUnit *SU) argument
[all...]
H A DScheduleDAGInstrs.cpp207 /// the exit SU to the register defs and use list. This is because we want to
245 /// MO is an operand of SU's instruction that defines a physical register. Add
246 /// data dependencies from SU to any uses of the physical register.
247 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument
248 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
259 SUnit *UseSU = I->SU;
260 if (UseSU == SU)
269 Dep = SDep(SU, SDep::Artificial);
273 SU->hasPhysRegDefs = true;
274 Dep = SDep(SU, SDe
290 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument
385 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument
494 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument
685 adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, const DataLayout &DL, SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList, unsigned LatencyToLoad) argument
760 SUnit *SU = newSUnit(MI); local
797 collectVRegUses(SUnit *SU) argument
895 SUnit *SU = MISUnitMap[MI]; local
1414 visitPreorder(const SUnit *SU) argument
1422 visitPostorderNode(const SUnit *SU) argument
1574 follow(const SUnit *SU) argument
1594 hasDataSucc(const SUnit *SU) argument
1612 const SUnit *SU = &*SI; local
[all...]
H A DMachineScheduler.cpp542 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { argument
559 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However,
561 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency())
562 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency();
569 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
570 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { argument
571 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
573 releaseSucc(SU, &*I);
581 void ScheduleDAGMI::releasePred(SUnit *SU, SDe argument
609 releasePredecessors(SUnit *SU) argument
693 SUnit *SU = SchedImpl->pickNode(IsTopNode); local
753 SUnit *SU = &(*I); local
801 updateQueues(SUnit *SU, bool IsTopNode) argument
944 updateScheduledPressure(const SUnit *SU, const std::vector<unsigned> &NewMaxPressure) argument
998 SUnit *SU = V2SU.SU; local
1068 SUnit *SU = SchedImpl->pickNode(IsTopNode); local
1191 SUnit *SU = V2SU.SU; local
1227 scheduleMI(SUnit *SU, bool IsTopNode) argument
1291 SUnit *SU; member in struct:__anon11808::LoadClusterMutation::LoadInfo
1319 SUnit *SU = Loads[Idx]; local
1367 SUnit *SU = &DAG->SUnits[Idx]; local
1641 SUnit *SU = &DAG->SUnits[Idx]; local
1731 getLatencyStallCycles(SUnit *SU) argument
1768 checkHazard(SUnit *SU) argument
1848 releaseNode(SUnit *SU, unsigned ReadyCycle) argument
1874 releaseTopNode(SUnit *SU) argument
1881 releaseBottomNode(SUnit *SU) argument
1971 bumpNode(SUnit *SU) argument
2110 SUnit *SU = *(Pending.begin()+i); local
2131 removeReady(SUnit *SU) argument
2611 getWeakLeft(const SUnit *SU, bool isTop) argument
2622 biasPhysRegCopy(const SUnit *SU, bool isTop) argument
2882 SUnit *SU; local
2922 reschedulePhysRegCopies(SUnit *SU, bool isTop) argument
2954 schedNode(SUnit *SU, bool IsTopNode) argument
3089 SUnit *SU; local
3114 schedNode(SUnit *SU, bool IsTopNode) argument
3193 SUnit *SU = ReadyQ.back(); variable
3280 SUnit *SU; variable
3367 getNodeLabel(const SUnit *SU, const ScheduleDAG *G) argument
3378 getNodeDescription(const SUnit *SU, const ScheduleDAG *G) argument
[all...]
H A DScheduleDAG.cpp183 SUnit *SU = WorkList.pop_back_val();
184 SU->isDepthCurrent = false;
185 for (SUnit::const_succ_iterator I = SU->Succs.begin(),
186 E = SU->Succs.end(); I != E; ++I) {
199 SUnit *SU = WorkList.pop_back_val();
200 SU->isHeightCurrent = false;
201 for (SUnit::const_pred_iterator I = SU->Preds.begin(),
202 E = SU->Preds.end(); I != E; ++I) {
317 dbgs() << "SU(" << NodeNum << "): ";
346 dbgs() << "SU(" <<
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H A DScoreboardHazardRecognizer.cpp119 ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
166 DEBUG(dbgs() << "SU(" << SU->NodeNum << "): ");
167 DEBUG(DAG->dumpNode(SU));
179 void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { argument
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { argument
72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, argument
110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
145 static unsigned numberCtrlDepsInSU(SUnit *SU) { argument
147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
155 static unsigned numberCtrlPredInSU(SUnit *SU) { argument
173 SUnit *SU = &(*SUnits)[i]; local
215 getSingleUnscheduledPred(SUnit *SU) argument
231 push(SUnit *SU) argument
246 isResourceAvailable(SUnit *SU) argument
289 reserveResources(SUnit *SU) argument
326 rawRegPressureDelta(SUnit *SU, unsigned RCId) argument
360 regPressureDelta(SUnit *SU, bool RawPressure) argument
401 SUSchedulingCost(SUnit *SU) argument
471 scheduledNode(SUnit *SU) argument
547 initNumRegDefsLeft(SUnit *SU) argument
579 adjustPriorityOfUnscheduledPreds(SUnit *SU) argument
632 remove(SUnit *SU) argument
[all...]
H A DScheduleDAGVLIW.cpp87 void releaseSucc(SUnit *SU, const SDep &D);
88 void releaseSuccessors(SUnit *SU);
89 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
116 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { argument
131 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
140 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { argument
142 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
147 releaseSucc(SU, *I);
154 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigne argument
[all...]
H A DScheduleDAGRRList.cpp185 /// IsReachable - Checks if SU is reachable from TargetSU.
186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument
187 return Topo.IsReachable(SU, TargetSU);
190 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument
193 return Topo.WillCreateCycle(SU, TargetSU);
196 /// AddPred - adds a predecessor edge to SUnit SU.
199 void AddPred(SUnit *SU, const SDep &D) { argument
200 Topo.AddPred(SU, D.getSUnit());
201 SU
207 RemovePred(SUnit *SU, const SDep &D) argument
213 isReady(SUnit *SU) argument
365 ReleasePred(SUnit *SU, const SDep *PredEdge) argument
525 ReleasePredecessors(SUnit *SU) argument
622 AdvancePastStalls(SUnit *SU) argument
664 EmitNode(SUnit *SU) argument
706 ScheduleNodeBottomUp(SUnit *SU) argument
805 UnscheduleNodeBottomUp(SUnit *SU) argument
903 SUnit *SU = *I; local
913 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument
935 isOperandOf(const SUnit *SU, SDNode *N) argument
946 CopyAndMoveSuccessors(SUnit *SU) argument
1144 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
1220 CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument
1242 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, ArrayRef<SUnit*> LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs) argument
1269 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument
1348 SUnit *SU = Interferences[i-1]; local
1520 SUnit *SU = PickNodeToScheduleBottomUp(); local
1809 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); variable
[all...]
H A DScheduleDAGSDNodes.cpp78 SUnit *SU = &SUnits.back(); local
83 SU->SchedulingPref = Sched::None;
85 SU->SchedulingPref = TLI.getSchedulingPreference(N);
86 return SU;
90 SUnit *SU = newSUnit(Old->getNode()); local
91 SU->OrigNode = Old->OrigNode;
92 SU->Latency = Old->Latency;
93 SU->isVRegCycle = Old->isVRegCycle;
94 SU->isCall = Old->isCall;
95 SU
[all...]
H A DScheduleDAGFast.cpp86 /// AddPred - adds a predecessor edge to SUnit SU.
88 void AddPred(SUnit *SU, const SDep &D) { argument
89 SU->addPred(D);
92 /// RemovePred - removes a predecessor edge from SUnit SU.
94 void RemovePred(SUnit *SU, const SDep &D) { argument
95 SU->removePred(D);
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
100 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
140 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { argument
161 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigne argument
183 ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) argument
213 CopyAndMoveSuccessors(SUnit *SU) argument
387 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
454 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument
475 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument
[all...]
H A DScheduleDAGSDNodes.h91 void InitNumRegDefsLeft(SUnit *SU);
95 virtual void computeLatency(SUnit *SU);
115 void dumpNode(const SUnit *SU) const override;
119 std::string getGraphNodeLabel(const SUnit *SU) const override;
135 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
175 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h31 bool isLoadAfterStore(SUnit *SU);
32 bool isBCTRAfterSet(SUnit *SU);
40 HazardType getHazardType(SUnit *SU, int Stalls) override;
41 bool ShouldPreferAnother(SUnit* SU) override;
42 unsigned PreEmitNoops(SUnit *SU) override;
43 void EmitInstruction(SUnit *SU) override;
79 HazardType getHazardType(SUnit *SU, int Stalls) override;
80 void EmitInstruction(SUnit *SU) override;
H A DPPCHazardRecognizers.cpp26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) { argument
28 if (isBCTRAfterSet(SU))
31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
38 // SU is a load; for any predecessors in this dispatch group, that are stores,
40 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
49 if (SU->Preds[i].getSUnit() == CurGroup[j])
56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { argument
141 getHazardType(SUnit *SU, int Stalls) argument
148 ShouldPreferAnother(SUnit *SU) argument
157 PreEmitNoops(SUnit *SU) argument
175 EmitInstruction(SUnit *SU) argument
325 getHazardType(SUnit *SU, int Stalls) argument
385 EmitInstruction(SUnit *SU) argument
[all...]
/external/llvm/include/llvm/CodeGen/
H A DResourcePriorityQueue.h84 void addNode(const SUnit *SU) override {
88 void updateNode(const SUnit *SU) override {}
104 /// Single cost function reflecting benefit of scheduling SU
106 signed SUSchedulingCost (SUnit *SU);
110 void initNumRegDefsLeft(SUnit *SU);
111 void updateNumRegDefsLeft(SUnit *SU);
112 signed regPressureDelta(SUnit *SU, bool RawPressure = false);
113 signed rawRegPressureDelta (SUnit *SU, unsigned RCId);
121 void remove(SUnit *SU) override;
125 bool isResourceAvailable(SUnit *SU);
[all...]
H A DScheduleDAGInstrs.h36 SUnit *SU; member in struct:llvm::VReg2SUnit
38 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) argument
39 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
51 unsigned OperandIndex, SUnit *SU)
52 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
58 SUnit *SU; member in struct:llvm::PhysRegSUOper
62 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
179 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
180 if (!SU
50 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU) argument
[all...]
H A DLatencyPriorityQueue.h57 void addNode(const SUnit *SU) override {
61 void updateNode(const SUnit *SU) override {
84 void remove(SUnit *SU) override;
93 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
94 SUnit *getSingleUnscheduledPred(SUnit *SU);
H A DMachineScheduler.h205 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
209 virtual void releaseTopNode(SUnit *SU) = 0;
212 virtual void releaseBottomNode(SUnit *SU) = 0;
290 /// \brief Add a DAG edge to the given SU with the given predecessor
334 void updateQueues(SUnit *SU, bool IsTopNode);
348 void releaseSucc(SUnit *SU, SDep *SuccEdge);
349 void releaseSuccessors(SUnit *SU);
350 void releasePred(SUnit *SU, SDep *PredEdge);
351 void releasePredecessors(SUnit *SU);
367 // Map each SU t
421 getPressureDiff(const SUnit *SU) argument
513 find(SUnit *SU) argument
517 push(SUnit *SU) argument
799 SUnit *SU; member in struct:llvm::GenericSchedulerBase::SchedCandidate
[all...]
H A DScheduleDFS.h146 unsigned getNumInstrs(const SUnit *SU) const {
147 return DFSNodeData[SU->NodeNum].InstrCount;
159 ILPValue getILP(const SUnit *SU) const {
160 return ILPValue(DFSNodeData[SU->NodeNum].InstrCount, 1 + SU->getDepth());
170 unsigned getSubtreeID(const SUnit *SU) const {
173 assert(SU->NodeNum < DFSNodeData.size() && "New Node");
174 return DFSNodeData[SU->NodeNum].SubtreeID;
/external/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp58 SUnit *SU = nullptr; local
98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
101 SU = pickAlu();
102 if (!SU && !PhysicalRegCopy.empty()) {
103 SU = PhysicalRegCopy.front();
106 if (SU) {
113 if (!SU) {
115 SU = pickOther(IDFetch);
116 if (SU)
121 if (!SU) {
144 schedNode(SUnit *SU, bool IsTopNode) argument
192 releaseTopNode(SUnit *SU) argument
196 releaseBottomNode(SUnit *SU) argument
296 getInstKind(SUnit* SU) argument
325 SUnit *SU = *It; local
435 SUnit *SU = AttemptFillSlot(3, true); local
444 SUnit *SU = AttemptFillSlot(Chan, false); local
458 SUnit *SU = nullptr; local
[all...]
H A DR600MachineScheduler.h78 void schedNode(SUnit *SU, bool IsTopNode) override;
79 void releaseTopNode(SUnit *SU) override;
80 void releaseBottomNode(SUnit *SU) override;
86 int getInstKind(SUnit *SU);
88 AluKind getAluKind(SUnit *SU) const;
/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
38 MachineInstr *MI = SU->getInstr();
74 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
83 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { argument
84 MachineInstr *MI = SU->getInstr();
90 ScoreboardHazardRecognizer::EmitInstruction(SU);
H A DARMHazardRecognizer.h40 HazardType getHazardType(SUnit *SU, int Stalls) override;
42 void EmitInstruction(SUnit *SU) override;
/external/eigen/blas/fortran/
H A Dsrotmg.f55 + SQ2,STEMP,SU,TWO,ZERO local in subroutine:SROTMG
86 SU = ONE - SH12*SH21
88 IF (.NOT.SU.LE.ZERO) GO TO 30
93 SD1 = SD1/SU
94 SD2 = SD2/SU
95 SX1 = SX1*SU
106 SU = ONE + SH11*SH22
107 STEMP = SD2/SU
108 SD2 = SD1/SU
110 SX1 = SY1*SU
[all...]

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