Searched refs:_3DSTATE_PIPE_CONTROL (Results 1 - 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_batchbuffer.c383 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
397 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
418 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
470 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
478 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
517 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
531 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) |
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dintel_batchbuffer.c383 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
397 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
418 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
470 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
478 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
517 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
531 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) |
H A Dbrw_queryobj.c62 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
70 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
81 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) |
102 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
114 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) |
H A Dgen6_vs_state.c219 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
/external/mesa3d/src/mesa/drivers/dri/intel/
H A Dintel_batchbuffer.c383 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
397 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
418 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
470 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
478 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
517 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
531 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2) |
H A Dintel_reg.h61 #define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24)) macro

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