Search

Home

Sort by

Searched refs:spill (Results 1 - 11 of 11) sorted by relevance

/external/libunwind/src/ia64/
H A D	getcontext.S	`51 st8.spill [r2] = r1, (SC_FLAGS - GR(1)) // M3 66 st8.spill [r2] = r12, (GR(4) - GR(12)) // M3 70 stf.spill [r3] = f2 // M2 71 stf.spill [r8] = f16 // M3 76 stf.spill [r9] = f24, (FR(31) - FR(24)) // M2 80 stf.spill [r9] = f31 // M2 81 st8.spill [r2] = r4, (GR(5) - GR(4)) // M3, bank 1 85 .mem.offset 0,0; st8.spill [r2] = r5, (GR(6) - GR(5)) // M4, bank 0 86 .mem.offset 8,0; st8.spill [r3] = r7, (BR(0) - GR(7)) // M3, bank 0 90 st8.spill [r [all...]`
/external/llvm/lib/CodeGen/
H A D	Spiller.h	`22 /// Implementations are utility classes which insert spill or remat code on 29 /// spill - Spill the LRE.getParent() live interval. 30 virtual void spill(LiveRangeEdit &LRE) = 0; 34 /// Create and return a spiller that will insert spill code directly instead`
H A D	RegAllocBasic.cpp	`57 /// algorithm. It prioritizes live virtual registers by spill weight and spills 203 spiller().spill(LRE); 222 // Populate a list of physical register spill candidates. 235 // Only virtual registers in the way, we may be able to spill them. 245 // Try to spill another interfering reg with less spill weight. 252 "Interference after spill."); 257 // No other spill candidates were found, so spill the current VirtReg. 262 spiller().spill(LR [all...]`
H A D	InlineSpiller.cpp	54 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden, 55 cl::desc("Disable inline spill hoisting")); 72 // Variables that are valid during spill(), but used by multiple methods. 78 // All registers to spill to StackSlot, including the main register. 92 // True when all reaching defs were reloads: No spill is necessary. 101 // The preferred register to spill. 152 void spill(LiveRangeEdit &) override; 203 // When spilling a virtual register, we also spill any snippets it is connected 209 // spill slots which can be important in tight loops. 295 DEBUG(dbgs() << "\talso spill snippe 1371 void InlineSpiller::spill(LiveRangeEdit &edit) { function in class:InlineSpiller [all...]
H A D	RegAllocPBQP.cpp	`14 // register assignment. If any variables are selected for spilling then spill 153 /// @brief Set spill costs for each node in the PBQP reg-alloc graph. 159 // A minimum spill costs, so that register constraints can can be set 635 VRegSpiller.spill(LRE); 647 assert(!LI.empty() && "Empty spill range."); 718 // All intervals have a spill weight that is mostly proportional to the number`
H A D	RegAllocGreedy.cpp	59 SplitSpillMode("split-spill-mode", cl::Hidden, 232 float MaxWeight; ///< Maximum spill weight evicted. 754 // Never evict spill products. They cannot split or spill. 758 // register for it. This is indicated by an infinite spill weight. These 869 // hints, and only evict smaller spill weights. 952 // Number of spill code instructions to insert. 975 // Accumulate the total frequency of inserted spill code. 1103 // Use the spill placer to determine the live bundles. GrowRegion pretends 1139 // We normally only need one spill instructio [all...]
/external/v8/test/mjsunit/regress/
H A D	regress-crbug-173907b.js	`36 %NeverOptimizeFunction(spill); 37 function spill() { function 45 spill(); // At this point initial values for phi1 and phi2 are spilled.`
H A D	regress-crbug-173907.js	`36 function spill() { function 45 spill(); // At this point initial values for phi1 and phi2 are spilled.`
/external/libunwind/tests/
H A D	ia64-test-nat-asm.S	`108 stf.spill [sp] = f2, -16 188 st8.spill [sp] = r4, -16 225 st8.spill [sp] = r6, -16;; 263 st8.spill [sp] = r6, -16;; 305 st8.spill [sp] = r6, -16;; 348 st8.spill [sp] = r6, -16;; 392 st8.spill [sp] = r7 // save r7 in the scratch stack space`
/external/mesa3d/src/gallium/drivers/nv50/codegen/
H A D	nv50_ir_ra.cpp	285 void spill(Instruction defi, Value slot, LValue ); 707 SpillCodeInserter& spill; member in class:nv50_ir::GCRA 993 GCRA::GCRA(Function fn, SpillCodeInserter& spill) : argument 996 spill(spill) 1153 (node->degree < node->degreeLimit) ? "" : "(spill)"); 1171 // spill candidate 1180 ERROR("no viable spill candidates left\n"); 1282 INFO_DBG(prog->dbgFlags, REG_ALLOC, "must spill: %%%i (size %u)\n", 1286 slot = spill 1436 SpillCodeInserter::spill(Instruction defi, Value slot, LValue *lval) function in class:nv50_ir::SpillCodeInserter [all...]
/external/v8/src/compiler/
H A D	register-allocator.cc	400 // We cannot spill a live range that has a use requiring a register 744 // make sure we insert the spill. 750 // Insert spill at the end to let live range connections happen at START. 1563 // This value is produced on the stack, we never need to spill it. 1628 // This value is produced on the stack, we never need to spill it. 2169 SpillRange* spill = range->HasSpillRange() local 2172 spill->set_assigned_slot(slot_id); 2242 TRACE("Live range %d:%d is defined by a spill operand.\n", 2249 // If the range already has a spill operand and it doesn't need a 2250 // register immediately, split it and spill th [all...]

Completed in 406 milliseconds