Searched refs:urb_gen5 (Results 1 - 3 of 3) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_eu_emit.c492 insn->bits3.urb_gen5.opcode = 1; /* FF_SYNC */
493 insn->bits3.urb_gen5.offset = 0; /* Not used by FF_SYNC */
494 insn->bits3.urb_gen5.swizzle_control = 0; /* Not used by FF_SYNC */
495 insn->bits3.urb_gen5.allocate = allocate;
496 insn->bits3.urb_gen5.used = 0; /* Not used by FF_SYNC */
497 insn->bits3.urb_gen5.complete = 0; /* Not used by FF_SYNC */
525 insn->bits3.urb_gen5.opcode = 0; /* URB_WRITE */
526 insn->bits3.urb_gen5.offset = offset;
527 insn->bits3.urb_gen5.swizzle_control = swizzle_control;
528 insn->bits3.urb_gen5
[all...]
H A Dbrw_disasm.c1261 format (file, " %d", inst->bits3.urb_gen5.offset);
1269 inst->bits3.urb_gen5.opcode, &space);
H A Dbrw_structs.h1369 } urb_gen5; member in union:brw_instruction::__anon14174

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