Searched refs:v2i32 (Results 1 - 25 of 25) sorted by relevance

/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp81 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
82 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
111 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
135 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
136 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
142 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
143 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
145 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
146 { ISD::FP_TO_UINT, MVT::v2i32, MV
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H A DARMISelDAGToDAG.cpp1828 case MVT::v2i32: OpcodeIndex = 2; break;
1965 case MVT::v2i32: OpcodeIndex = 2; break;
2128 case MVT::v2i32: OpcodeIndex = 2; break;
2240 case MVT::v2i32: OpcodeIndex = 2; break;
2779 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2799 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2818 case MVT::v2i32: Opc = ARM::VTRNd32; break;
H A DARMISelLowering.cpp154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
470 addDRTypeForNEON(MVT::v2i32);
580 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
588 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
598 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
632 MVT::v2i32}) {
1073 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
3993 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3995 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4247 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
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/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp215 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
218 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
249 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
252 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
256 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
259 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
263 // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
277 // Complex, from v2f64: legal type is v2i32, 1 narrowing => ~2.
278 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
281 { ISD::FP_TO_UINT, MVT::v2i32, MV
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H A DAArch64ISelDAGToDAG.cpp488 case MVT::v2i32:
2485 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2503 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2521 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2539 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2557 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2575 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2593 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2611 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2629 else if (VT == MVT::v2i32 || V
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H A DAArch64ISelLowering.cpp94 addDRTypeForNEON(MVT::v2i32);
429 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
577 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
578 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
594 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
634 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
637 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
717 addTypeForNEON(VT, MVT::v2i32);
2029 return MVT::v2i32;
3728 VecVT = (VT == MVT::v2f32 ? MVT::v2i32
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/external/clang/test/CodeGen/
H A Dsystemz-abi-vector.c22 typedef __attribute__((vector_size(8))) int v2i32; typedef
86 v2i32 pass_v2i32(v2i32 arg) { return arg; }
H A Dx86_64-arguments.c290 typedef unsigned v2i32 __attribute((__vector_size__(8))); typedef
291 v2i32 f36(v2i32 arg) { return arg; }
/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h88 v2i32 = 39, // 2 x i32 enumerator in enum:llvm::MVT::SimpleValueType
235 SimpleTy == MVT::v2i32 || SimpleTy == MVT::v1i64 ||
336 case v2i32:
407 case v2i32:
466 case v2i32:
618 if (NumElements == 2) return MVT::v2i32;
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp237 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
241 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32,
270 TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32,
284 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
H A DSparcISelLowering.cpp237 assert(VA.getLocVT() == MVT::v2i32);
238 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
424 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
476 assert(VA.getValVT() == MVT::f64 || MVT::v2i32);
841 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
861 // TODO: The f64 -> v2i32 conversion is super-inefficient for
865 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
1447 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
1452 setOperationAction(Op, MVT::v2i32, Expand);
1456 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expan
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/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp64 (int)MVT::v2i32,
92 (int)MVT::v2i32,
501 INTTY = MVT::v2i32;
649 INTTY = MVT::v2i32;
667 INTTY = MVT::v2i32;
/external/llvm/lib/IR/
H A DValueTypes.cpp166 case MVT::v2i32: return "v2i32";
244 case MVT::v2i32: return VectorType::get(Type::getInt32Ty(Context), 2);
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp242 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
406 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
1231 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1232 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1272 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1273 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1274 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1557 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1737 promoteLdStType(MVT::v2i32, MVT::i64);
1790 MVT::v2i32, MV
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/external/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp52 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
172 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
198 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
490 return MVT::v2i32;
1391 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1392 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1404 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1532 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
1533 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
1534 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale
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H A DAMDGPUISelLowering.cpp114 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
135 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
136 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
154 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
176 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
292 MVT::v2i32, MVT::v4i32
1964 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1979 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
2081 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2167 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Sr
[all...]
H A DR600ISelLowering.cpp41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
91 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
128 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
149 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
158 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
163 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
H A DAMDGPUISelDAGToDAG.cpp1439 // To simplify the TableGen patters, we replace all i64 loads with v2i32
1440 // loads. Alternatively, we could promote i64 loads to v2i32 during DAG
1457 SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SL, LD->getChain(),
1468 MVT::v2i32, ST->getValue());
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp99 case MVT::v2i32: return "MVT::v2i32";
/external/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp433 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64.
599 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 },
604 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
H A DX86ISelLowering.cpp782 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
894 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
942 // sequence to convert from v2i32 to v2f32.
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1398 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
5464 //TODO: The code below fires only for for loading the low v2i32 / v2f3
[all...]
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp434 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp67 case MVT::v2i32:
1915 case MVT::v2i32:
4292 case MVT::v2i32:
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp646 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
7538 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7539 // instructions), but for smaller types, we need to first extend up to v2i32
7543 if (ExtVT != MVT::v2i32) {
7550 DAG.getValueType(MVT::v2i32));
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp4652 EVT ShAmtVT = MVT::v2i32;
4684 // We must do this early because v2i32 is not a legal type.

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