| /art/compiler/utils/arm64/ |
| H A D | assembler_arm64.h | 112 void BuildFrame(size_t frame_size, ManagedRegister method_reg,
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| H A D | assembler_arm64.cc | 686 void Arm64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, argument
716 DCHECK(X0 == method_reg.AsArm64().AsXRegister());
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| /art/compiler/utils/ |
| H A D | assembler.h | 376 virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg,
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| /art/compiler/utils/arm/ |
| H A D | assembler_arm.cc | 389 void ArmAssembler::BuildFrame(size_t frame_size, ManagedRegister method_reg,
394 CHECK_EQ(R0, method_reg.AsArm().AsCoreRegister());
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| H A D | assembler_arm.h | 910 void BuildFrame(size_t frame_size, ManagedRegister method_reg,
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| /art/compiler/utils/x86/ |
| H A D | assembler_x86.h | 635 void BuildFrame(size_t frame_size, ManagedRegister method_reg,
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| H A D | assembler_x86.cc | 1927 void X86Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, argument
1948 pushl(method_reg.AsX86().AsCpuRegister());
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| /art/compiler/utils/x86_64/ |
| H A D | assembler_x86_64_test.cc | 1514 x86_64::X86_64ManagedRegister method_reg = ManagedFromCpu(x86_64::RDI); local
1517 assembler->BuildFrame(10 * kStackAlignment, method_reg, spill_regs, entry_spills);
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| H A D | assembler_x86_64.h | 706 void BuildFrame(size_t frame_size, ManagedRegister method_reg,
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| H A D | assembler_x86_64.cc | 2641 void X86_64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, argument
2677 movq(Address(CpuRegister(RSP), 0), method_reg.AsX86_64().AsCpuRegister());
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| /art/compiler/optimizing/ |
| H A D | code_generator_mips64.cc | 3073 GpuRegister method_reg; local
3075 method_reg = current_method.AsRegister<GpuRegister>();
3080 method_reg = reg;
3087 method_reg,
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| H A D | code_generator_arm64.cc | 3669 Register method_reg; local
3671 method_reg = XRegisterFrom(current_method);
3675 method_reg = reg;
3681 MemOperand(method_reg.X(),
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| H A D | code_generator_mips.cc | 3858 Register method_reg; local
3860 method_reg = current_method.AsRegister<Register>();
3865 method_reg = reg;
3872 method_reg,
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| H A D | code_generator_arm.cc | 6361 Register method_reg; local
6364 method_reg = current_method.AsRegister<Register>();
6368 method_reg = reg;
6374 method_reg,
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| H A D | code_generator_x86.cc | 4359 Register method_reg; local
4362 method_reg = current_method.AsRegister<Register>();
4366 method_reg = reg;
4370 __ movl(reg, Address(method_reg,
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| H A D | code_generator_x86_64.cc | 797 Register method_reg; local
800 method_reg = current_method.AsRegister<Register>();
804 method_reg = reg.AsRegister();
809 Address(CpuRegister(method_reg),
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| /art/compiler/utils/mips/ |
| H A D | assembler_mips.h | 416 ManagedRegister method_reg,
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| H A D | assembler_mips.cc | 2441 void MipsAssembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, argument
2462 StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0);
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| /art/compiler/utils/mips64/ |
| H A D | assembler_mips64.h | 368 void BuildFrame(size_t frame_size, ManagedRegister method_reg,
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| H A D | assembler_mips64.cc | 1980 void Mips64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, argument
2001 StoreToOffset(kStoreDoubleword, method_reg.AsMips64().AsGpuRegister(), SP, 0);
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