1# Copyright (c) 2014, Google Inc.
2#
3# Permission to use, copy, modify, and/or distribute this software for any
4# purpose with or without fee is hereby granted, provided that the above
5# copyright notice and this permission notice appear in all copies.
6#
7# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
10# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
12# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
13# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14
15# This file contains a pre-compiled version of chacha_vec.c for ARM. This is
16# needed to support switching on NEON code at runtime. If the whole of OpenSSL
17# were to be compiled with the needed flags to build chacha_vec.c, then it
18# wouldn't be possible to run on non-NEON systems.
19#
20# This file was generated by chacha_vec_arm_generate.go using the following
21# compiler command:
22#
23#     /opt/gcc-linaro-4.9-2014.11-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-gcc -O3 -mcpu=cortex-a8 -mfpu=neon -fpic -DASM_GEN -I ../../include -S chacha_vec.c -o -
24
25#if !defined(OPENSSL_NO_ASM)
26#if defined(__arm__)
27
28	.syntax unified
29	.cpu cortex-a8
30	.eabi_attribute 27, 3
31
32# EABI attribute 28 sets whether VFP register arguments were used to build this
33# file. If object files are inconsistent on this point, the linker will refuse
34# to link them. Thus we report whatever the compiler expects since we don't use
35# VFP arguments.
36
37#if defined(__ARM_PCS_VFP)
38	.eabi_attribute 28, 1
39#else
40	.eabi_attribute 28, 0
41#endif
42
43	.fpu neon
44	.eabi_attribute 20, 1
45	.eabi_attribute 21, 1
46	.eabi_attribute 23, 3
47	.eabi_attribute 24, 1
48	.eabi_attribute 25, 1
49	.eabi_attribute 26, 2
50	.eabi_attribute 30, 2
51	.eabi_attribute 34, 1
52	.eabi_attribute 18, 4
53	.thumb
54	.file	"chacha_vec.c"
55	.text
56	.align	2
57	.global	CRYPTO_chacha_20_neon
58	.hidden	CRYPTO_chacha_20_neon
59	.thumb
60	.thumb_func
61	.type	CRYPTO_chacha_20_neon, %function
62CRYPTO_chacha_20_neon:
63	@ args = 8, pretend = 0, frame = 160
64	@ frame_needed = 1, uses_anonymous_args = 0
65	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
66	mov	r9, r3
67	vpush.64	{d8, d9, d10, d11, d12, d13, d14, d15}
68	mov	r10, r2
69	ldr	r4, .L91+16
70	mov	fp, r1
71	mov	r8, r9
72.LPIC16:
73	add	r4, pc
74	sub	sp, sp, #164
75	add	r7, sp, #0
76	sub	sp, sp, #112
77	add	lr, r7, #148
78	str	r0, [r7, #80]
79	str	r1, [r7, #12]
80	str	r2, [r7, #8]
81	ldmia	r4, {r0, r1, r2, r3}
82	add	r4, sp, #15
83	bic	r4, r4, #15
84	ldr	r6, [r7, #264]
85	str	r4, [r7, #88]
86	mov	r5, r4
87	adds	r4, r4, #64
88	add	ip, r5, #80
89	str	r9, [r7, #56]
90	stmia	r4, {r0, r1, r2, r3}
91	movw	r4, #43691
92	ldr	r0, [r6]	@ unaligned
93	movt	r4, 43690
94	ldr	r1, [r6, #4]	@ unaligned
95	ldr	r2, [r6, #8]	@ unaligned
96	ldr	r3, [r9, #12]	@ unaligned
97	str	ip, [r7, #84]
98	stmia	lr!, {r0, r1, r2}
99	mov	lr, ip
100	ldr	r1, [r9, #4]	@ unaligned
101	ldr	r2, [r9, #8]	@ unaligned
102	ldr	r0, [r9]	@ unaligned
103	vldr	d24, [r5, #64]
104	vldr	d25, [r5, #72]
105	umull	r4, r5, r10, r4
106	stmia	ip!, {r0, r1, r2, r3}
107	ldr	r0, [r8, #16]!	@ unaligned
108	ldr	r2, [r7, #88]
109	ldr	r4, [r7, #268]
110	ldr	r1, [r8, #4]	@ unaligned
111	vldr	d26, [r2, #80]
112	vldr	d27, [r2, #88]
113	ldr	r3, [r8, #12]	@ unaligned
114	ldr	r2, [r8, #8]	@ unaligned
115	stmia	lr!, {r0, r1, r2, r3}
116	ldr	r3, [r6]
117	ldr	r1, [r6, #4]
118	ldr	r6, [r6, #8]
119	str	r3, [r7, #68]
120	str	r3, [r7, #132]
121	lsrs	r3, r5, #7
122	str	r6, [r7, #140]
123	str	r6, [r7, #60]
124	ldr	r6, [r7, #88]
125	str	r4, [r7, #128]
126	str	r1, [r7, #136]
127	str	r1, [r7, #64]
128	vldr	d28, [r6, #80]
129	vldr	d29, [r6, #88]
130	vldr	d22, [r7, #128]
131	vldr	d23, [r7, #136]
132	beq	.L26
133	mov	r5, r6
134	lsls	r2, r3, #8
135	sub	r3, r2, r3, lsl #6
136	ldr	r2, [r5, #68]
137	ldr	r6, [r6, #64]
138	vldr	d0, .L91
139	vldr	d1, .L91+8
140	str	r2, [r7, #48]
141	ldr	r2, [r5, #72]
142	str	r3, [r7, #4]
143	str	r6, [r7, #52]
144	str	r2, [r7, #44]
145	adds	r2, r4, #2
146	str	r2, [r7, #72]
147	ldr	r2, [r5, #76]
148	str	fp, [r7, #76]
149	str	r2, [r7, #40]
150	ldr	r2, [r7, #80]
151	adds	r3, r2, r3
152	str	r3, [r7, #16]
153.L4:
154	ldr	r5, [r7, #56]
155	add	r8, r7, #40
156	ldr	r4, [r7, #68]
157	vadd.i32	q3, q11, q0
158	ldmia	r8, {r8, r9, r10, fp}
159	mov	r1, r5
160	ldr	r2, [r5, #4]
161	vmov	q8, q14  @ v4si
162	ldr	r3, [r5]
163	vmov	q1, q13  @ v4si
164	ldr	r6, [r1, #28]
165	vmov	q9, q12  @ v4si
166	mov	r0, r2
167	ldr	r2, [r5, #8]
168	str	r4, [r7, #112]
169	movs	r1, #10
170	ldr	r4, [r7, #72]
171	vmov	q2, q11  @ v4si
172	ldr	lr, [r5, #20]
173	vmov	q15, q14  @ v4si
174	str	r3, [r7, #108]
175	vmov	q5, q13  @ v4si
176	str	r2, [r7, #116]
177	vmov	q10, q12  @ v4si
178	ldr	r2, [r5, #12]
179	ldr	ip, [r5, #16]
180	ldr	r3, [r7, #64]
181	ldr	r5, [r5, #24]
182	str	r6, [r7, #120]
183	str	r1, [r7, #92]
184	ldr	r6, [r7, #60]
185	str	r4, [r7, #100]
186	ldr	r1, [r7, #116]
187	ldr	r4, [r7, #108]
188	str	r8, [r7, #96]
189	mov	r8, r10
190	str	lr, [r7, #104]
191	mov	r10, r9
192	mov	lr, r3
193	mov	r9, r5
194	str	r6, [r7, #124]
195	b	.L92
196.L93:
197	.align	3
198.L91:
199	.word	1
200	.word	0
201	.word	0
202	.word	0
203	.word	.LANCHOR0-(.LPIC16+4)
204.L92:
205.L3:
206	vadd.i32	q9, q9, q1
207	add	r3, r8, r0
208	vadd.i32	q10, q10, q5
209	add	r5, fp, r4
210	veor	q3, q3, q9
211	mov	r6, r3
212	veor	q2, q2, q10
213	ldr	r3, [r7, #96]
214	str	r5, [r7, #116]
215	add	r10, r10, r1
216	vrev32.16	q3, q3
217	str	r6, [r7, #108]
218	vadd.i32	q8, q8, q3
219	vrev32.16	q2, q2
220	vadd.i32	q15, q15, q2
221	mov	fp, r3
222	ldr	r3, [r7, #100]
223	veor	q4, q8, q1
224	veor	q6, q15, q5
225	add	fp, fp, r2
226	eors	r3, r3, r5
227	mov	r5, r6
228	ldr	r6, [r7, #112]
229	vshl.i32	q1, q4, #12
230	vshl.i32	q5, q6, #12
231	ror	r3, r3, #16
232	eors	r6, r6, r5
233	eor	lr, lr, r10
234	vsri.32	q1, q4, #20
235	mov	r5, r6
236	ldr	r6, [r7, #124]
237	vsri.32	q5, q6, #20
238	str	r3, [r7, #124]
239	eor	r6, r6, fp
240	ror	r5, r5, #16
241	vadd.i32	q9, q9, q1
242	ror	lr, lr, #16
243	ror	r3, r6, #16
244	ldr	r6, [r7, #124]
245	vadd.i32	q10, q10, q5
246	add	r9, r9, lr
247	veor	q4, q9, q3
248	add	ip, ip, r6
249	ldr	r6, [r7, #104]
250	veor	q6, q10, q2
251	eor	r4, ip, r4
252	str	r3, [r7, #104]
253	vshl.i32	q3, q4, #8
254	eor	r1, r9, r1
255	mov	r8, r6
256	ldr	r6, [r7, #120]
257	vshl.i32	q2, q6, #8
258	ror	r4, r4, #20
259	add	r6, r6, r3
260	vsri.32	q3, q4, #24
261	str	r6, [r7, #100]
262	eors	r2, r2, r6
263	ldr	r6, [r7, #116]
264	vsri.32	q2, q6, #24
265	add	r8, r8, r5
266	ror	r2, r2, #20
267	adds	r6, r4, r6
268	vadd.i32	q4, q8, q3
269	eor	r0, r8, r0
270	vadd.i32	q15, q15, q2
271	mov	r3, r6
272	ldr	r6, [r7, #108]
273	veor	q6, q4, q1
274	ror	r0, r0, #20
275	str	r3, [r7, #112]
276	veor	q5, q15, q5
277	adds	r6, r0, r6
278	str	r6, [r7, #120]
279	mov	r6, r3
280	ldr	r3, [r7, #124]
281	vshl.i32	q8, q6, #7
282	add	fp, fp, r2
283	eors	r3, r3, r6
284	ldr	r6, [r7, #120]
285	vshl.i32	q1, q5, #7
286	ror	r1, r1, #20
287	eors	r5, r5, r6
288	vsri.32	q8, q6, #25
289	ldr	r6, [r7, #104]
290	ror	r3, r3, #24
291	ror	r5, r5, #24
292	vsri.32	q1, q5, #25
293	str	r5, [r7, #116]
294	eor	r6, fp, r6
295	ldr	r5, [r7, #116]
296	add	r10, r10, r1
297	add	ip, r3, ip
298	vext.32	q8, q8, q8, #1
299	str	ip, [r7, #124]
300	add	ip, r5, r8
301	ldr	r5, [r7, #100]
302	eor	lr, r10, lr
303	ror	r6, r6, #24
304	vext.32	q1, q1, q1, #1
305	add	r8, r6, r5
306	vadd.i32	q9, q9, q8
307	ldr	r5, [r7, #124]
308	vext.32	q3, q3, q3, #3
309	vadd.i32	q10, q10, q1
310	ror	lr, lr, #24
311	eor	r0, ip, r0
312	vext.32	q2, q2, q2, #3
313	add	r9, r9, lr
314	eors	r4, r4, r5
315	veor	q3, q9, q3
316	ldr	r5, [r7, #112]
317	eor	r1, r9, r1
318	ror	r0, r0, #25
319	veor	q2, q10, q2
320	adds	r5, r0, r5
321	vext.32	q4, q4, q4, #2
322	str	r5, [r7, #112]
323	ldr	r5, [r7, #120]
324	ror	r1, r1, #25
325	vrev32.16	q3, q3
326	eor	r2, r8, r2
327	vext.32	q15, q15, q15, #2
328	adds	r5, r1, r5
329	vadd.i32	q4, q4, q3
330	ror	r4, r4, #25
331	vrev32.16	q2, q2
332	str	r5, [r7, #100]
333	vadd.i32	q15, q15, q2
334	eors	r3, r3, r5
335	ldr	r5, [r7, #112]
336	add	fp, fp, r4
337	veor	q8, q4, q8
338	ror	r2, r2, #25
339	veor	q1, q15, q1
340	eor	lr, fp, lr
341	eors	r6, r6, r5
342	ror	r3, r3, #16
343	ldr	r5, [r7, #116]
344	add	r10, r10, r2
345	str	r3, [r7, #120]
346	ror	lr, lr, #16
347	ldr	r3, [r7, #120]
348	eor	r5, r10, r5
349	vshl.i32	q5, q8, #12
350	add	ip, lr, ip
351	vshl.i32	q6, q1, #12
352	str	ip, [r7, #104]
353	add	ip, r3, r8
354	str	ip, [r7, #116]
355	ldr	r3, [r7, #124]
356	ror	r5, r5, #16
357	vsri.32	q5, q8, #20
358	ror	r6, r6, #16
359	add	ip, r5, r3
360	ldr	r3, [r7, #104]
361	vsri.32	q6, q1, #20
362	add	r9, r9, r6
363	eor	r2, ip, r2
364	eors	r4, r4, r3
365	ldr	r3, [r7, #116]
366	eor	r0, r9, r0
367	vadd.i32	q9, q9, q5
368	ror	r4, r4, #20
369	eors	r1, r1, r3
370	vadd.i32	q10, q10, q6
371	ror	r3, r2, #20
372	str	r3, [r7, #108]
373	ldr	r3, [r7, #112]
374	veor	q3, q9, q3
375	ror	r0, r0, #20
376	add	r8, r4, fp
377	veor	q2, q10, q2
378	add	fp, r0, r3
379	ldr	r3, [r7, #100]
380	ror	r1, r1, #20
381	mov	r2, r8
382	vshl.i32	q8, q3, #8
383	str	r8, [r7, #96]
384	add	r8, r1, r3
385	ldr	r3, [r7, #108]
386	vmov	q1, q6  @ v4si
387	vshl.i32	q6, q2, #8
388	eor	r6, fp, r6
389	add	r10, r10, r3
390	ldr	r3, [r7, #120]
391	vsri.32	q8, q3, #24
392	eor	lr, r2, lr
393	eor	r3, r8, r3
394	ror	r2, r6, #24
395	vsri.32	q6, q2, #24
396	eor	r5, r10, r5
397	str	r2, [r7, #124]
398	ror	r2, r3, #24
399	ldr	r3, [r7, #104]
400	vmov	q3, q8  @ v4si
401	vadd.i32	q15, q15, q6
402	ror	lr, lr, #24
403	vadd.i32	q8, q4, q8
404	ror	r6, r5, #24
405	add	r5, lr, r3
406	ldr	r3, [r7, #124]
407	veor	q4, q8, q5
408	add	ip, ip, r6
409	vmov	q2, q6  @ v4si
410	add	r9, r9, r3
411	veor	q6, q15, q1
412	ldr	r3, [r7, #116]
413	vshl.i32	q1, q4, #7
414	str	r2, [r7, #100]
415	add	r3, r3, r2
416	str	r3, [r7, #120]
417	vshl.i32	q5, q6, #7
418	eors	r1, r1, r3
419	ldr	r3, [r7, #108]
420	vsri.32	q1, q4, #25
421	eors	r4, r4, r5
422	eor	r0, r9, r0
423	eor	r2, ip, r3
424	vsri.32	q5, q6, #25
425	ldr	r3, [r7, #92]
426	ror	r4, r4, #25
427	str	r6, [r7, #112]
428	ror	r0, r0, #25
429	subs	r3, r3, #1
430	str	r5, [r7, #104]
431	ror	r1, r1, #25
432	ror	r2, r2, #25
433	vext.32	q15, q15, q15, #2
434	str	r3, [r7, #92]
435	vext.32	q2, q2, q2, #1
436	vext.32	q8, q8, q8, #2
437	vext.32	q3, q3, q3, #1
438	vext.32	q5, q5, q5, #3
439	vext.32	q1, q1, q1, #3
440	bne	.L3
441	ldr	r3, [r7, #84]
442	vadd.i32	q4, q12, q10
443	str	r9, [r7, #92]
444	mov	r9, r10
445	mov	r10, r8
446	ldr	r8, [r7, #96]
447	str	lr, [r7, #96]
448	mov	lr, r5
449	ldr	r5, [r7, #52]
450	vadd.i32	q5, q13, q5
451	ldr	r6, [r7, #76]
452	vadd.i32	q15, q14, q15
453	add	fp, fp, r5
454	ldr	r5, [r7, #48]
455	str	r3, [r7, #104]
456	vadd.i32	q7, q14, q8
457	ldr	r3, [r6, #12]	@ unaligned
458	add	r10, r10, r5
459	str	r0, [r7, #36]
460	vadd.i32	q2, q11, q2
461	ldr	r0, [r6]	@ unaligned
462	vadd.i32	q6, q12, q9
463	ldr	r5, [r7, #104]
464	vadd.i32	q1, q13, q1
465	str	r1, [r7, #116]
466	vadd.i32	q11, q11, q0
467	ldr	r1, [r6, #4]	@ unaligned
468	str	r2, [r7, #32]
469	vadd.i32	q3, q11, q3
470	ldr	r2, [r6, #8]	@ unaligned
471	vadd.i32	q11, q11, q0
472	str	r4, [r7, #108]
473	ldr	r4, [r7, #100]
474	vadd.i32	q11, q11, q0
475	stmia	r5!, {r0, r1, r2, r3}
476	ldr	r2, [r7, #88]
477	ldr	r3, [r7, #44]
478	ldr	r5, [r7, #84]
479	vldr	d20, [r2, #80]
480	vldr	d21, [r2, #88]
481	add	r3, r9, r3
482	str	r3, [r7, #104]
483	veor	q10, q10, q4
484	ldr	r3, [r7, #40]
485	add	r3, r8, r3
486	str	r3, [r7, #100]
487	ldr	r3, [r7, #72]
488	vstr	d20, [r2, #80]
489	vstr	d21, [r2, #88]
490	adds	r1, r4, r3
491	str	r1, [r7, #28]
492	ldmia	r5!, {r0, r1, r2, r3}
493	ldr	r4, [r7, #68]
494	ldr	r5, [r7, #112]
495	ldr	r8, [r7, #84]
496	add	r5, r5, r4
497	ldr	r4, [r7, #96]
498	str	r5, [r7, #24]
499	ldr	r5, [r7, #64]
500	add	r4, r4, r5
501	ldr	r5, [r7, #60]
502	str	r4, [r7, #96]
503	ldr	r4, [r7, #124]
504	add	r4, r4, r5
505	str	r4, [r7, #20]
506	ldr	r4, [r7, #80]
507	mov	r5, r8
508	str	r0, [r4]	@ unaligned
509	mov	r0, r4
510	str	r1, [r4, #4]	@ unaligned
511	mov	r4, r8
512	str	r2, [r0, #8]	@ unaligned
513	mov	r8, r0
514	str	r3, [r0, #12]	@ unaligned
515	mov	r9, r4
516	ldr	r0, [r6, #16]!	@ unaligned
517	ldr	r3, [r6, #12]	@ unaligned
518	ldr	r1, [r6, #4]	@ unaligned
519	ldr	r2, [r6, #8]	@ unaligned
520	ldr	r6, [r7, #76]
521	stmia	r5!, {r0, r1, r2, r3}
522	mov	r5, r8
523	ldr	r3, [r7, #88]
524	vldr	d20, [r3, #80]
525	vldr	d21, [r3, #88]
526	veor	q10, q10, q5
527	vstr	d20, [r3, #80]
528	vstr	d21, [r3, #88]
529	ldmia	r4!, {r0, r1, r2, r3}
530	mov	r4, r9
531	str	r0, [r8, #16]	@ unaligned
532	str	r1, [r8, #20]	@ unaligned
533	str	r2, [r8, #24]	@ unaligned
534	str	r3, [r8, #28]	@ unaligned
535	mov	r8, r5
536	ldr	r0, [r6, #32]!	@ unaligned
537	mov	r5, r9
538	ldr	r1, [r6, #4]	@ unaligned
539	ldr	r2, [r6, #8]	@ unaligned
540	ldr	r3, [r6, #12]	@ unaligned
541	ldr	r6, [r7, #76]
542	stmia	r5!, {r0, r1, r2, r3}
543	mov	r5, r8
544	ldr	r1, [r7, #88]
545	vldr	d16, [r1, #80]
546	vldr	d17, [r1, #88]
547	veor	q15, q8, q15
548	vstr	d30, [r1, #80]
549	vstr	d31, [r1, #88]
550	ldmia	r4!, {r0, r1, r2, r3}
551	mov	r4, r9
552	str	r0, [r8, #32]	@ unaligned
553	str	r1, [r8, #36]	@ unaligned
554	str	r2, [r8, #40]	@ unaligned
555	str	r3, [r8, #44]	@ unaligned
556	mov	r8, r5
557	ldr	r0, [r6, #48]!	@ unaligned
558	ldr	r1, [r6, #4]	@ unaligned
559	ldr	r2, [r6, #8]	@ unaligned
560	ldr	r3, [r6, #12]	@ unaligned
561	ldr	r6, [r7, #76]
562	stmia	r4!, {r0, r1, r2, r3}
563	mov	r4, r9
564	ldr	r1, [r7, #88]
565	str	r9, [r7, #112]
566	vldr	d18, [r1, #80]
567	vldr	d19, [r1, #88]
568	veor	q9, q9, q2
569	vstr	d18, [r1, #80]
570	vstr	d19, [r1, #88]
571	ldmia	r9!, {r0, r1, r2, r3}
572	str	r0, [r5, #48]	@ unaligned
573	str	r1, [r5, #52]	@ unaligned
574	str	r2, [r5, #56]	@ unaligned
575	str	r3, [r5, #60]	@ unaligned
576	ldr	r0, [r6, #64]!	@ unaligned
577	ldr	r1, [r6, #4]	@ unaligned
578	ldr	r2, [r6, #8]	@ unaligned
579	ldr	r3, [r6, #12]	@ unaligned
580	ldr	r6, [r7, #76]
581	mov	r9, r6
582	mov	r6, r4
583	stmia	r6!, {r0, r1, r2, r3}
584	mov	r6, r4
585	ldr	r1, [r7, #88]
586	vldr	d18, [r1, #80]
587	vldr	d19, [r1, #88]
588	veor	q9, q9, q6
589	vstr	d18, [r1, #80]
590	vstr	d19, [r1, #88]
591	ldmia	r4!, {r0, r1, r2, r3}
592	mov	r4, r6
593	str	r3, [r5, #76]	@ unaligned
594	mov	r3, r9
595	str	r2, [r5, #72]	@ unaligned
596	str	r0, [r5, #64]	@ unaligned
597	str	r1, [r5, #68]	@ unaligned
598	mov	r5, r4
599	ldr	r0, [r3, #80]!	@ unaligned
600	mov	r9, r3
601	ldr	r1, [r9, #4]	@ unaligned
602	ldr	r2, [r9, #8]	@ unaligned
603	ldr	r3, [r9, #12]	@ unaligned
604	mov	r9, r4
605	ldr	r6, [r7, #76]
606	str	r9, [r7, #124]
607	stmia	r5!, {r0, r1, r2, r3}
608	mov	r5, r8
609	ldr	r1, [r7, #88]
610	vldr	d18, [r1, #80]
611	vldr	d19, [r1, #88]
612	veor	q1, q9, q1
613	vstr	d2, [r1, #80]
614	vstr	d3, [r1, #88]
615	ldmia	r4!, {r0, r1, r2, r3}
616	mov	r4, r9
617	str	r0, [r8, #80]	@ unaligned
618	str	r1, [r8, #84]	@ unaligned
619	str	r2, [r8, #88]	@ unaligned
620	str	r3, [r8, #92]	@ unaligned
621	ldr	r0, [r6, #96]!	@ unaligned
622	ldr	r3, [r6, #12]	@ unaligned
623	ldr	r1, [r6, #4]	@ unaligned
624	ldr	r2, [r6, #8]	@ unaligned
625	ldr	r6, [r7, #76]
626	stmia	r4!, {r0, r1, r2, r3}
627	mov	r4, r9
628	ldr	r3, [r7, #88]
629	vldr	d16, [r3, #80]
630	vldr	d17, [r3, #88]
631	veor	q8, q8, q7
632	vstr	d16, [r3, #80]
633	vstr	d17, [r3, #88]
634	ldmia	r9!, {r0, r1, r2, r3}
635	str	r0, [r5, #96]	@ unaligned
636	str	r1, [r5, #100]	@ unaligned
637	str	r2, [r5, #104]	@ unaligned
638	str	r3, [r5, #108]	@ unaligned
639	ldr	r0, [r6, #112]!	@ unaligned
640	ldr	r1, [r6, #4]	@ unaligned
641	ldr	r2, [r6, #8]	@ unaligned
642	ldr	r3, [r6, #12]	@ unaligned
643	mov	r6, r4
644	stmia	r6!, {r0, r1, r2, r3}
645	mov	r6, r5
646	ldr	r3, [r7, #88]
647	vldr	d16, [r3, #80]
648	vldr	d17, [r3, #88]
649	veor	q8, q8, q3
650	vstr	d16, [r3, #80]
651	vstr	d17, [r3, #88]
652	ldmia	r4!, {r0, r1, r2, r3}
653	mov	r4, r5
654	mov	r8, r4
655	str	r2, [r5, #120]	@ unaligned
656	ldr	r2, [r7, #76]
657	str	r0, [r5, #112]	@ unaligned
658	str	r1, [r5, #116]	@ unaligned
659	str	r3, [r5, #124]	@ unaligned
660	ldr	r3, [r2, #128]
661	ldr	r1, [r7, #104]
662	eor	r3, fp, r3
663	str	r3, [r5, #128]
664	ldr	r3, [r2, #132]
665	mov	r5, r2
666	eor	r3, r10, r3
667	str	r3, [r6, #132]
668	ldr	r3, [r2, #136]
669	mov	r6, r5
670	eors	r1, r1, r3
671	str	r1, [r8, #136]
672	ldr	r1, [r7, #56]
673	ldr	r3, [r2, #140]
674	ldr	r2, [r7, #100]
675	ldr	r0, [r7, #108]
676	eors	r3, r3, r2
677	str	r3, [r4, #140]
678	ldr	r3, [r1]
679	ldr	r2, [r5, #144]
680	mov	r8, r0
681	add	r8, r8, r3
682	mov	r5, r6
683	mov	r3, r8
684	eors	r2, r2, r3
685	str	r2, [r4, #144]
686	ldr	r3, [r6, #148]
687	ldr	r2, [r1, #4]
688	ldr	r6, [r7, #36]
689	add	r6, r6, r2
690	eors	r3, r3, r6
691	mov	r6, r1
692	str	r3, [r4, #148]
693	ldr	r2, [r1, #8]
694	ldr	r1, [r7, #116]
695	ldr	r3, [r5, #152]
696	mov	r8, r1
697	add	r8, r8, r2
698	ldr	r1, [r7, #32]
699	mov	r2, r8
700	eors	r3, r3, r2
701	str	r3, [r4, #152]
702	mov	r8, r4
703	ldr	r2, [r6, #12]
704	ldr	r3, [r5, #156]
705	add	r1, r1, r2
706	eors	r3, r3, r1
707	str	r3, [r4, #156]
708	ldr	r2, [r6, #16]
709	mov	r1, r4
710	ldr	r3, [r5, #160]
711	mov	r4, r5
712	add	ip, ip, r2
713	mov	r5, r6
714	eor	r3, ip, r3
715	str	r3, [r1, #160]
716	ldr	r2, [r6, #20]
717	ldr	r3, [r4, #164]
718	add	lr, lr, r2
719	ldr	r2, [r7, #92]
720	eor	r3, lr, r3
721	str	r3, [r1, #164]
722	ldr	r6, [r5, #24]
723	mov	lr, r4
724	ldr	r3, [r4, #168]
725	add	r2, r2, r6
726	ldr	r6, [r7, #120]
727	eors	r3, r3, r2
728	str	r3, [r1, #168]
729	ldr	r5, [r5, #28]
730	ldr	r3, [r4, #172]
731	add	r6, r6, r5
732	eors	r3, r3, r6
733	str	r3, [r1, #172]
734	ldr	r4, [r4, #176]
735	ldr	r0, [r7, #28]
736	ldr	r5, [r7, #24]
737	eors	r4, r4, r0
738	str	r4, [r8, #176]
739	ldr	r0, [lr, #180]
740	ldr	r2, [r7, #96]
741	eors	r0, r0, r5
742	str	r0, [r8, #180]
743	ldr	r1, [lr, #184]
744	ldr	r4, [r7, #20]
745	eors	r1, r1, r2
746	str	r1, [r8, #184]
747	ldr	r2, [lr, #188]
748	add	r1, lr, #192
749	ldr	r3, [r7, #72]
750	eors	r2, r2, r4
751	str	r2, [r8, #188]
752	ldr	r2, [r7, #16]
753	adds	r3, r3, #3
754	str	r3, [r7, #72]
755	mov	r3, r8
756	adds	r3, r3, #192
757	str	r1, [r7, #76]
758	cmp	r2, r3
759	str	r3, [r7, #80]
760	bne	.L4
761	ldr	r3, [r7, #12]
762	ldr	r2, [r7, #4]
763	add	r3, r3, r2
764	str	r3, [r7, #12]
765.L2:
766	ldr	r1, [r7, #8]
767	movw	r2, #43691
768	movt	r2, 43690
769	umull	r2, r3, r1, r2
770	lsr	fp, r3, #7
771	lsl	r3, fp, #8
772	sub	fp, r3, fp, lsl #6
773	rsb	fp, fp, r1
774	lsrs	fp, fp, #6
775	beq	.L6
776	ldr	r5, [r7, #12]
777	ldr	r4, [r7, #16]
778	ldr	r6, [r7, #88]
779	ldr	lr, [r7, #84]
780	vldr	d30, .L94
781	vldr	d31, .L94+8
782	str	fp, [r7, #120]
783	str	fp, [r7, #124]
784.L8:
785	vmov	q2, q11  @ v4si
786	movs	r3, #10
787	vmov	q8, q14  @ v4si
788	vmov	q9, q13  @ v4si
789	vmov	q10, q12  @ v4si
790.L7:
791	vadd.i32	q10, q10, q9
792	subs	r3, r3, #1
793	veor	q3, q2, q10
794	vrev32.16	q3, q3
795	vadd.i32	q8, q8, q3
796	veor	q9, q8, q9
797	vshl.i32	q2, q9, #12
798	vsri.32	q2, q9, #20
799	vadd.i32	q10, q10, q2
800	veor	q3, q10, q3
801	vshl.i32	q9, q3, #8
802	vsri.32	q9, q3, #24
803	vadd.i32	q8, q8, q9
804	vext.32	q9, q9, q9, #3
805	veor	q2, q8, q2
806	vext.32	q8, q8, q8, #2
807	vshl.i32	q3, q2, #7
808	vsri.32	q3, q2, #25
809	vext.32	q3, q3, q3, #1
810	vadd.i32	q10, q10, q3
811	veor	q9, q10, q9
812	vrev32.16	q9, q9
813	vadd.i32	q8, q8, q9
814	veor	q3, q8, q3
815	vshl.i32	q2, q3, #12
816	vsri.32	q2, q3, #20
817	vadd.i32	q10, q10, q2
818	vmov	q3, q2  @ v4si
819	veor	q9, q10, q9
820	vshl.i32	q2, q9, #8
821	vsri.32	q2, q9, #24
822	vadd.i32	q8, q8, q2
823	vext.32	q2, q2, q2, #1
824	veor	q3, q8, q3
825	vext.32	q8, q8, q8, #2
826	vshl.i32	q9, q3, #7
827	vsri.32	q9, q3, #25
828	vext.32	q9, q9, q9, #3
829	bne	.L7
830	ldr	r0, [r5]	@ unaligned
831	vadd.i32	q1, q12, q10
832	ldr	r1, [r5, #4]	@ unaligned
833	mov	ip, lr
834	ldr	r2, [r5, #8]	@ unaligned
835	mov	r9, lr
836	ldr	r3, [r5, #12]	@ unaligned
837	mov	r10, r5
838	vadd.i32	q9, q13, q9
839	mov	r8, lr
840	vadd.i32	q8, q14, q8
841	stmia	ip!, {r0, r1, r2, r3}
842	mov	ip, lr
843	vldr	d20, [r6, #80]
844	vldr	d21, [r6, #88]
845	vadd.i32	q3, q11, q2
846	veor	q10, q10, q1
847	vadd.i32	q11, q11, q15
848	vstr	d20, [r6, #80]
849	vstr	d21, [r6, #88]
850	ldmia	r9!, {r0, r1, r2, r3}
851	mov	r9, r5
852	str	r0, [r4]	@ unaligned
853	str	r1, [r4, #4]	@ unaligned
854	str	r2, [r4, #8]	@ unaligned
855	str	r3, [r4, #12]	@ unaligned
856	ldr	r0, [r10, #16]!	@ unaligned
857	ldr	r1, [r10, #4]	@ unaligned
858	ldr	r2, [r10, #8]	@ unaligned
859	ldr	r3, [r10, #12]	@ unaligned
860	add	r10, r4, #48
861	adds	r4, r4, #64
862	stmia	r8!, {r0, r1, r2, r3}
863	mov	r8, lr
864	vldr	d20, [r6, #80]
865	vldr	d21, [r6, #88]
866	veor	q10, q10, q9
867	vstr	d20, [r6, #80]
868	vstr	d21, [r6, #88]
869	ldmia	ip!, {r0, r1, r2, r3}
870	mov	ip, lr
871	str	r0, [r4, #-48]	@ unaligned
872	str	r1, [r4, #-44]	@ unaligned
873	str	r2, [r4, #-40]	@ unaligned
874	str	r3, [r4, #-36]	@ unaligned
875	ldr	r0, [r9, #32]!	@ unaligned
876	ldr	r1, [r9, #4]	@ unaligned
877	ldr	r2, [r9, #8]	@ unaligned
878	ldr	r3, [r9, #12]	@ unaligned
879	mov	r9, r5
880	adds	r5, r5, #64
881	stmia	r8!, {r0, r1, r2, r3}
882	mov	r8, lr
883	vldr	d18, [r6, #80]
884	vldr	d19, [r6, #88]
885	veor	q9, q9, q8
886	vstr	d18, [r6, #80]
887	vstr	d19, [r6, #88]
888	ldmia	ip!, {r0, r1, r2, r3}
889	mov	ip, lr
890	str	r0, [r4, #-32]	@ unaligned
891	str	r1, [r4, #-28]	@ unaligned
892	str	r2, [r4, #-24]	@ unaligned
893	str	r3, [r4, #-20]	@ unaligned
894	ldr	r0, [r9, #48]!	@ unaligned
895	ldr	r1, [r9, #4]	@ unaligned
896	ldr	r2, [r9, #8]	@ unaligned
897	ldr	r3, [r9, #12]	@ unaligned
898	stmia	r8!, {r0, r1, r2, r3}
899	vldr	d16, [r6, #80]
900	vldr	d17, [r6, #88]
901	veor	q8, q8, q3
902	vstr	d16, [r6, #80]
903	vstr	d17, [r6, #88]
904	ldmia	ip!, {r0, r1, r2, r3}
905	str	r0, [r4, #-16]	@ unaligned
906	str	r1, [r4, #-12]	@ unaligned
907	str	r3, [r10, #12]	@ unaligned
908	ldr	r3, [r7, #124]
909	str	r2, [r10, #8]	@ unaligned
910	cmp	r3, #1
911	beq	.L87
912	movs	r3, #1
913	str	r3, [r7, #124]
914	b	.L8
915.L95:
916	.align	3
917.L94:
918	.word	1
919	.word	0
920	.word	0
921	.word	0
922.L87:
923	ldr	fp, [r7, #120]
924	ldr	r3, [r7, #12]
925	lsl	fp, fp, #6
926	add	r3, r3, fp
927	str	r3, [r7, #12]
928	ldr	r3, [r7, #16]
929	add	r3, r3, fp
930	str	r3, [r7, #16]
931.L6:
932	ldr	r3, [r7, #8]
933	ands	r9, r3, #63
934	beq	.L1
935	vmov	q3, q11  @ v4si
936	movs	r3, #10
937	vmov	q8, q14  @ v4si
938	mov	r5, r9
939	vmov	q15, q13  @ v4si
940	vmov	q10, q12  @ v4si
941.L10:
942	vadd.i32	q10, q10, q15
943	subs	r3, r3, #1
944	veor	q9, q3, q10
945	vrev32.16	q9, q9
946	vadd.i32	q8, q8, q9
947	veor	q15, q8, q15
948	vshl.i32	q3, q15, #12
949	vsri.32	q3, q15, #20
950	vadd.i32	q10, q10, q3
951	veor	q15, q10, q9
952	vshl.i32	q9, q15, #8
953	vsri.32	q9, q15, #24
954	vadd.i32	q8, q8, q9
955	vext.32	q9, q9, q9, #3
956	veor	q3, q8, q3
957	vext.32	q8, q8, q8, #2
958	vshl.i32	q15, q3, #7
959	vsri.32	q15, q3, #25
960	vext.32	q15, q15, q15, #1
961	vadd.i32	q10, q10, q15
962	veor	q9, q10, q9
963	vrev32.16	q9, q9
964	vadd.i32	q8, q8, q9
965	veor	q15, q8, q15
966	vshl.i32	q3, q15, #12
967	vsri.32	q3, q15, #20
968	vadd.i32	q10, q10, q3
969	vmov	q15, q3  @ v4si
970	veor	q9, q10, q9
971	vshl.i32	q3, q9, #8
972	vsri.32	q3, q9, #24
973	vadd.i32	q8, q8, q3
974	vext.32	q3, q3, q3, #1
975	veor	q9, q8, q15
976	vext.32	q8, q8, q8, #2
977	vshl.i32	q15, q9, #7
978	vsri.32	q15, q9, #25
979	vext.32	q15, q15, q15, #3
980	bne	.L10
981	cmp	r5, #15
982	mov	r9, r5
983	bhi	.L88
984	vadd.i32	q12, q12, q10
985	ldr	r3, [r7, #88]
986	vst1.64	{d24-d25}, [r3:128]
987.L14:
988	ldr	r3, [r7, #8]
989	and	r2, r3, #48
990	cmp	r9, r2
991	bls	.L1
992	ldr	r6, [r7, #16]
993	add	r3, r2, #16
994	ldr	r1, [r7, #12]
995	rsb	ip, r2, r9
996	adds	r0, r1, r2
997	mov	r4, r6
998	add	r1, r1, r3
999	add	r4, r4, r2
1000	add	r3, r3, r6
1001	cmp	r0, r3
1002	it	cc
1003	cmpcc	r4, r1
1004	ite	cs
1005	movcs	r3, #1
1006	movcc	r3, #0
1007	cmp	ip, #18
1008	ite	ls
1009	movls	r3, #0
1010	andhi	r3, r3, #1
1011	cmp	r3, #0
1012	beq	.L16
1013	and	r1, r0, #7
1014	mov	r3, r2
1015	negs	r1, r1
1016	and	r1, r1, #15
1017	cmp	r1, ip
1018	it	cs
1019	movcs	r1, ip
1020	cmp	r1, #0
1021	beq	.L17
1022	ldr	r5, [r7, #88]
1023	cmp	r1, #1
1024	ldrb	r0, [r0]	@ zero_extendqisi2
1025	add	r3, r2, #1
1026	ldrb	lr, [r5, r2]	@ zero_extendqisi2
1027	mov	r6, r5
1028	eor	r0, lr, r0
1029	strb	r0, [r4]
1030	beq	.L17
1031	ldr	r0, [r7, #12]
1032	cmp	r1, #2
1033	ldrb	r4, [r5, r3]	@ zero_extendqisi2
1034	ldr	r5, [r7, #16]
1035	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1036	eor	r0, r0, r4
1037	strb	r0, [r5, r3]
1038	add	r3, r2, #2
1039	beq	.L17
1040	ldr	r0, [r7, #12]
1041	cmp	r1, #3
1042	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1043	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1044	eor	r0, r0, r4
1045	strb	r0, [r5, r3]
1046	add	r3, r2, #3
1047	beq	.L17
1048	ldr	r0, [r7, #12]
1049	cmp	r1, #4
1050	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1051	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1052	eor	r0, r0, r4
1053	strb	r0, [r5, r3]
1054	add	r3, r2, #4
1055	beq	.L17
1056	ldr	r0, [r7, #12]
1057	cmp	r1, #5
1058	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1059	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1060	eor	r0, r0, r4
1061	strb	r0, [r5, r3]
1062	add	r3, r2, #5
1063	beq	.L17
1064	ldr	r0, [r7, #12]
1065	cmp	r1, #6
1066	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1067	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1068	eor	r0, r0, r4
1069	strb	r0, [r5, r3]
1070	add	r3, r2, #6
1071	beq	.L17
1072	ldr	r0, [r7, #12]
1073	cmp	r1, #7
1074	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1075	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1076	eor	r0, r0, r4
1077	strb	r0, [r5, r3]
1078	add	r3, r2, #7
1079	beq	.L17
1080	ldr	r0, [r7, #12]
1081	cmp	r1, #8
1082	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1083	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1084	eor	r0, r0, r4
1085	strb	r0, [r5, r3]
1086	add	r3, r2, #8
1087	beq	.L17
1088	ldr	r0, [r7, #12]
1089	cmp	r1, #9
1090	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1091	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1092	eor	r0, r0, r4
1093	strb	r0, [r5, r3]
1094	add	r3, r2, #9
1095	beq	.L17
1096	ldr	r0, [r7, #12]
1097	cmp	r1, #10
1098	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1099	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1100	eor	r0, r0, r4
1101	strb	r0, [r5, r3]
1102	add	r3, r2, #10
1103	beq	.L17
1104	ldr	r0, [r7, #12]
1105	cmp	r1, #11
1106	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1107	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1108	eor	r0, r0, r4
1109	strb	r0, [r5, r3]
1110	add	r3, r2, #11
1111	beq	.L17
1112	ldr	r0, [r7, #12]
1113	cmp	r1, #12
1114	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1115	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1116	eor	r0, r0, r4
1117	strb	r0, [r5, r3]
1118	add	r3, r2, #12
1119	beq	.L17
1120	ldr	r0, [r7, #12]
1121	cmp	r1, #13
1122	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1123	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1124	eor	r0, r0, r4
1125	strb	r0, [r5, r3]
1126	add	r3, r2, #13
1127	beq	.L17
1128	ldr	r0, [r7, #12]
1129	cmp	r1, #15
1130	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1131	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1132	eor	r0, r0, r4
1133	strb	r0, [r5, r3]
1134	add	r3, r2, #14
1135	bne	.L17
1136	ldr	r0, [r7, #12]
1137	ldrb	r4, [r6, r3]	@ zero_extendqisi2
1138	ldrb	r0, [r0, r3]	@ zero_extendqisi2
1139	eors	r0, r0, r4
1140	strb	r0, [r5, r3]
1141	add	r3, r2, #15
1142.L17:
1143	rsb	r4, r1, ip
1144	add	r0, ip, #-1
1145	sub	r6, r4, #16
1146	subs	r0, r0, r1
1147	cmp	r0, #14
1148	lsr	r6, r6, #4
1149	add	r6, r6, #1
1150	lsl	lr, r6, #4
1151	bls	.L19
1152	add	r2, r2, r1
1153	ldr	r1, [r7, #12]
1154	ldr	r5, [r7, #16]
1155	cmp	r6, #1
1156	add	r0, r1, r2
1157	ldr	r1, [r7, #88]
1158	add	r1, r1, r2
1159	vld1.64	{d18-d19}, [r0:64]
1160	add	r2, r2, r5
1161	vld1.8	{q8}, [r1]
1162	veor	q8, q8, q9
1163	vst1.8	{q8}, [r2]
1164	beq	.L20
1165	add	r8, r1, #16
1166	add	ip, r2, #16
1167	vldr	d18, [r0, #16]
1168	vldr	d19, [r0, #24]
1169	cmp	r6, #2
1170	vld1.8	{q8}, [r8]
1171	veor	q8, q8, q9
1172	vst1.8	{q8}, [ip]
1173	beq	.L20
1174	add	r8, r1, #32
1175	add	ip, r2, #32
1176	vldr	d18, [r0, #32]
1177	vldr	d19, [r0, #40]
1178	cmp	r6, #3
1179	vld1.8	{q8}, [r8]
1180	veor	q8, q8, q9
1181	vst1.8	{q8}, [ip]
1182	beq	.L20
1183	adds	r1, r1, #48
1184	adds	r2, r2, #48
1185	vldr	d18, [r0, #48]
1186	vldr	d19, [r0, #56]
1187	vld1.8	{q8}, [r1]
1188	veor	q8, q8, q9
1189	vst1.8	{q8}, [r2]
1190.L20:
1191	cmp	lr, r4
1192	add	r3, r3, lr
1193	beq	.L1
1194.L19:
1195	ldr	r4, [r7, #88]
1196	adds	r2, r3, #1
1197	ldr	r1, [r7, #12]
1198	cmp	r2, r9
1199	ldr	r5, [r7, #16]
1200	ldrb	r0, [r4, r3]	@ zero_extendqisi2
1201	ldrb	r1, [r1, r3]	@ zero_extendqisi2
1202	eor	r1, r1, r0
1203	strb	r1, [r5, r3]
1204	bcs	.L1
1205	ldr	r0, [r7, #12]
1206	adds	r1, r3, #2
1207	mov	r6, r4
1208	cmp	r9, r1
1209	ldrb	r4, [r4, r2]	@ zero_extendqisi2
1210	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1211	eor	r0, r0, r4
1212	strb	r0, [r5, r2]
1213	bls	.L1
1214	ldr	r0, [r7, #12]
1215	adds	r2, r3, #3
1216	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1217	cmp	r9, r2
1218	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1219	eor	r0, r0, r4
1220	strb	r0, [r5, r1]
1221	bls	.L1
1222	ldr	r0, [r7, #12]
1223	adds	r1, r3, #4
1224	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1225	cmp	r9, r1
1226	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1227	eor	r0, r0, r4
1228	strb	r0, [r5, r2]
1229	bls	.L1
1230	ldr	r0, [r7, #12]
1231	adds	r2, r3, #5
1232	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1233	cmp	r9, r2
1234	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1235	eor	r0, r0, r4
1236	strb	r0, [r5, r1]
1237	bls	.L1
1238	ldr	r0, [r7, #12]
1239	adds	r1, r3, #6
1240	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1241	cmp	r9, r1
1242	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1243	eor	r0, r0, r4
1244	strb	r0, [r5, r2]
1245	bls	.L1
1246	ldr	r0, [r7, #12]
1247	adds	r2, r3, #7
1248	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1249	cmp	r9, r2
1250	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1251	eor	r0, r0, r4
1252	strb	r0, [r5, r1]
1253	bls	.L1
1254	ldr	r0, [r7, #12]
1255	add	r1, r3, #8
1256	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1257	cmp	r9, r1
1258	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1259	eor	r0, r0, r4
1260	strb	r0, [r5, r2]
1261	bls	.L1
1262	ldr	r0, [r7, #12]
1263	add	r2, r3, #9
1264	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1265	cmp	r9, r2
1266	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1267	eor	r0, r0, r4
1268	strb	r0, [r5, r1]
1269	bls	.L1
1270	ldr	r0, [r7, #12]
1271	add	r1, r3, #10
1272	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1273	cmp	r9, r1
1274	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1275	eor	r0, r0, r4
1276	strb	r0, [r5, r2]
1277	bls	.L1
1278	ldr	r0, [r7, #12]
1279	add	r2, r3, #11
1280	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1281	cmp	r9, r2
1282	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1283	eor	r0, r0, r4
1284	strb	r0, [r5, r1]
1285	bls	.L1
1286	ldr	r0, [r7, #12]
1287	add	r1, r3, #12
1288	ldrb	r4, [r6, r2]	@ zero_extendqisi2
1289	cmp	r9, r1
1290	ldrb	r0, [r0, r2]	@ zero_extendqisi2
1291	eor	r0, r0, r4
1292	strb	r0, [r5, r2]
1293	bls	.L1
1294	ldr	r0, [r7, #12]
1295	add	r2, r3, #13
1296	ldrb	r4, [r6, r1]	@ zero_extendqisi2
1297	cmp	r9, r2
1298	ldrb	r0, [r0, r1]	@ zero_extendqisi2
1299	eor	r0, r0, r4
1300	strb	r0, [r5, r1]
1301	bls	.L1
1302	ldr	r1, [r7, #12]
1303	adds	r3, r3, #14
1304	ldrb	r0, [r6, r2]	@ zero_extendqisi2
1305	cmp	r9, r3
1306	ldrb	r1, [r1, r2]	@ zero_extendqisi2
1307	eor	r1, r1, r0
1308	strb	r1, [r5, r2]
1309	bls	.L1
1310	ldr	r2, [r7, #88]
1311	ldrb	r1, [r2, r3]	@ zero_extendqisi2
1312	ldr	r2, [r7, #12]
1313	ldrb	r2, [r2, r3]	@ zero_extendqisi2
1314	eors	r2, r2, r1
1315	ldr	r1, [r7, #16]
1316	strb	r2, [r1, r3]
1317.L1:
1318	adds	r7, r7, #164
1319	mov	sp, r7
1320	@ sp needed
1321	vldm	sp!, {d8-d15}
1322	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
1323.L88:
1324	ldr	r5, [r7, #12]
1325	vadd.i32	q12, q12, q10
1326	ldr	r4, [r7, #84]
1327	cmp	r9, #31
1328	ldr	r0, [r5]	@ unaligned
1329	ldr	r1, [r5, #4]	@ unaligned
1330	mov	r6, r4
1331	ldr	r2, [r5, #8]	@ unaligned
1332	ldr	r3, [r5, #12]	@ unaligned
1333	stmia	r6!, {r0, r1, r2, r3}
1334	ldr	r2, [r7, #88]
1335	ldr	r6, [r7, #16]
1336	vldr	d18, [r2, #80]
1337	vldr	d19, [r2, #88]
1338	veor	q9, q9, q12
1339	vstr	d18, [r2, #80]
1340	vstr	d19, [r2, #88]
1341	ldmia	r4!, {r0, r1, r2, r3}
1342	str	r1, [r6, #4]	@ unaligned
1343	mov	r1, r6
1344	str	r0, [r6]	@ unaligned
1345	str	r2, [r6, #8]	@ unaligned
1346	str	r3, [r6, #12]	@ unaligned
1347	bhi	.L89
1348	vadd.i32	q13, q13, q15
1349	ldr	r3, [r7, #88]
1350	vstr	d26, [r3, #16]
1351	vstr	d27, [r3, #24]
1352	b	.L14
1353.L16:
1354	subs	r3, r2, #1
1355	ldr	r2, [r7, #12]
1356	add	r2, r2, r9
1357	mov	r5, r2
1358	ldr	r2, [r7, #88]
1359	add	r2, r2, r3
1360	mov	r3, r2
1361.L24:
1362	ldrb	r1, [r0], #1	@ zero_extendqisi2
1363	ldrb	r2, [r3, #1]!	@ zero_extendqisi2
1364	cmp	r0, r5
1365	eor	r2, r2, r1
1366	strb	r2, [r4], #1
1367	bne	.L24
1368	adds	r7, r7, #164
1369	mov	sp, r7
1370	@ sp needed
1371	vldm	sp!, {d8-d15}
1372	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
1373.L26:
1374	ldr	r3, [r7, #80]
1375	str	r3, [r7, #16]
1376	b	.L2
1377.L89:
1378	mov	r3, r5
1379	ldr	r4, [r7, #84]
1380	ldr	r0, [r3, #16]!	@ unaligned
1381	add	lr, r1, #16
1382	mov	r5, r1
1383	vadd.i32	q13, q13, q15
1384	mov	r6, r4
1385	cmp	r9, #47
1386	ldr	r1, [r3, #4]	@ unaligned
1387	ldr	r2, [r3, #8]	@ unaligned
1388	ldr	r3, [r3, #12]	@ unaligned
1389	stmia	r6!, {r0, r1, r2, r3}
1390	ldr	r2, [r7, #88]
1391	vldr	d18, [r2, #80]
1392	vldr	d19, [r2, #88]
1393	veor	q13, q9, q13
1394	vstr	d26, [r2, #80]
1395	vstr	d27, [r2, #88]
1396	ldmia	r4!, {r0, r1, r2, r3}
1397	str	r0, [r5, #16]	@ unaligned
1398	str	r1, [lr, #4]	@ unaligned
1399	str	r2, [lr, #8]	@ unaligned
1400	str	r3, [lr, #12]	@ unaligned
1401	bhi	.L90
1402	vadd.i32	q8, q14, q8
1403	ldr	r3, [r7, #88]
1404	vstr	d16, [r3, #32]
1405	vstr	d17, [r3, #40]
1406	b	.L14
1407.L90:
1408	ldr	r3, [r7, #12]
1409	add	lr, r5, #32
1410	ldr	r4, [r7, #84]
1411	vadd.i32	q8, q14, q8
1412	ldr	r5, [r7, #88]
1413	vadd.i32	q11, q11, q3
1414	ldr	r0, [r3, #32]!	@ unaligned
1415	mov	r6, r4
1416	vstr	d22, [r5, #48]
1417	vstr	d23, [r5, #56]
1418	ldr	r1, [r3, #4]	@ unaligned
1419	ldr	r2, [r3, #8]	@ unaligned
1420	ldr	r3, [r3, #12]	@ unaligned
1421	stmia	r4!, {r0, r1, r2, r3}
1422	vldr	d18, [r5, #80]
1423	vldr	d19, [r5, #88]
1424	veor	q9, q9, q8
1425	ldr	r4, [r7, #16]
1426	vstr	d18, [r5, #80]
1427	vstr	d19, [r5, #88]
1428	ldmia	r6!, {r0, r1, r2, r3}
1429	str	r0, [r4, #32]	@ unaligned
1430	str	r1, [lr, #4]	@ unaligned
1431	str	r2, [lr, #8]	@ unaligned
1432	str	r3, [lr, #12]	@ unaligned
1433	b	.L14
1434	.size	CRYPTO_chacha_20_neon, .-CRYPTO_chacha_20_neon
1435	.section	.rodata
1436	.align	2
1437.LANCHOR0 = . + 0
1438.LC0:
1439	.word	1634760805
1440	.word	857760878
1441	.word	2036477234
1442	.word	1797285236
1443	.ident	"GCC: (Linaro GCC 2014.11) 4.9.3 20141031 (prerelease)"
1444	.section	.note.GNU-stack,"",%progbits
1445
1446#endif  /* __arm__ */
1447#endif  /* !OPENSSL_NO_ASM */
1448