1/* 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2015 Intel Corporation. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2015 Intel Corporation. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 27 * - Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * - Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in 31 * the documentation and/or other materials provided with the 32 * distribution. 33 * - Neither the name of Intel Corporation nor the names of its 34 * contributors may be used to endorse or promote products derived 35 * from this software without specific prior written permission. 36 * 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 * 49 */ 50 51/* 52 * This file contains defines, structures, etc. that are used 53 * to communicate between kernel and user code. 54 */ 55 56#ifndef _LINUX__HFI1_USER_H 57#define _LINUX__HFI1_USER_H 58 59#include <linux/types.h> 60 61/* 62 * This version number is given to the driver by the user code during 63 * initialization in the spu_userversion field of hfi1_user_info, so 64 * the driver can check for compatibility with user code. 65 * 66 * The major version changes when data structures change in an incompatible 67 * way. The driver must be the same for initialization to succeed. 68 */ 69#define HFI1_USER_SWMAJOR 4 70 71/* 72 * Minor version differences are always compatible 73 * a within a major version, however if user software is larger 74 * than driver software, some new features and/or structure fields 75 * may not be implemented; the user code must deal with this if it 76 * cares, or it must abort after initialization reports the difference. 77 */ 78#define HFI1_USER_SWMINOR 0 79 80/* 81 * Set of HW and driver capability/feature bits. 82 * These bit values are used to configure enabled/disabled HW and 83 * driver features. The same set of bits are communicated to user 84 * space. 85 */ 86#define HFI1_CAP_DMA_RTAIL (1UL << 0) /* Use DMA'ed RTail value */ 87#define HFI1_CAP_SDMA (1UL << 1) /* Enable SDMA support */ 88#define HFI1_CAP_SDMA_AHG (1UL << 2) /* Enable SDMA AHG support */ 89#define HFI1_CAP_EXTENDED_PSN (1UL << 3) /* Enable Extended PSN support */ 90#define HFI1_CAP_HDRSUPP (1UL << 4) /* Enable Header Suppression */ 91/* 1UL << 5 unused */ 92#define HFI1_CAP_USE_SDMA_HEAD (1UL << 6) /* DMA Hdr Q tail vs. use CSR */ 93#define HFI1_CAP_MULTI_PKT_EGR (1UL << 7) /* Enable multi-packet Egr buffs*/ 94#define HFI1_CAP_NODROP_RHQ_FULL (1UL << 8) /* Don't drop on Hdr Q full */ 95#define HFI1_CAP_NODROP_EGR_FULL (1UL << 9) /* Don't drop on EGR buffs full */ 96#define HFI1_CAP_TID_UNMAP (1UL << 10) /* Enable Expected TID caching */ 97#define HFI1_CAP_PRINT_UNIMPL (1UL << 11) /* Show for unimplemented feats */ 98#define HFI1_CAP_ALLOW_PERM_JKEY (1UL << 12) /* Allow use of permissive JKEY */ 99#define HFI1_CAP_NO_INTEGRITY (1UL << 13) /* Enable ctxt integrity checks */ 100#define HFI1_CAP_PKEY_CHECK (1UL << 14) /* Enable ctxt PKey checking */ 101#define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */ 102/* 1UL << 16 unused */ 103#define HFI1_CAP_SDMA_HEAD_CHECK (1UL << 17) /* SDMA head checking */ 104#define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */ 105 106#define HFI1_RCVHDR_ENTSIZE_2 (1UL << 0) 107#define HFI1_RCVHDR_ENTSIZE_16 (1UL << 1) 108#define HFI1_RCVDHR_ENTSIZE_32 (1UL << 2) 109 110/* 111 * If the unit is specified via open, HFI choice is fixed. If port is 112 * specified, it's also fixed. Otherwise we try to spread contexts 113 * across ports and HFIs, using different algorithms. WITHIN is 114 * the old default, prior to this mechanism. 115 */ 116#define HFI1_ALG_ACROSS 0 /* round robin contexts across HFIs, then 117 * ports; this is the default */ 118#define HFI1_ALG_WITHIN 1 /* use all contexts on an HFI (round robin 119 * active ports within), then next HFI */ 120#define HFI1_ALG_COUNT 2 /* number of algorithm choices */ 121 122 123/* User commands. */ 124#define HFI1_CMD_ASSIGN_CTXT 1 /* allocate HFI and context */ 125#define HFI1_CMD_CTXT_INFO 2 /* find out what resources we got */ 126#define HFI1_CMD_USER_INFO 3 /* set up userspace */ 127#define HFI1_CMD_TID_UPDATE 4 /* update expected TID entries */ 128#define HFI1_CMD_TID_FREE 5 /* free expected TID entries */ 129#define HFI1_CMD_CREDIT_UPD 6 /* force an update of PIO credit */ 130#define HFI1_CMD_SDMA_STATUS_UPD 7 /* force update of SDMA status ring */ 131 132#define HFI1_CMD_RECV_CTRL 8 /* control receipt of packets */ 133#define HFI1_CMD_POLL_TYPE 9 /* set the kind of polling we want */ 134#define HFI1_CMD_ACK_EVENT 10 /* ack & clear user status bits */ 135#define HFI1_CMD_SET_PKEY 11 /* set context's pkey */ 136#define HFI1_CMD_CTXT_RESET 12 /* reset context's HW send context */ 137/* separate EPROM commands from normal PSM commands */ 138#define HFI1_CMD_EP_INFO 64 /* read EPROM device ID */ 139#define HFI1_CMD_EP_ERASE_CHIP 65 /* erase whole EPROM */ 140#define HFI1_CMD_EP_ERASE_P0 66 /* erase EPROM partition 0 */ 141#define HFI1_CMD_EP_ERASE_P1 67 /* erase EPROM partition 1 */ 142#define HFI1_CMD_EP_READ_P0 68 /* read EPROM partition 0 */ 143#define HFI1_CMD_EP_READ_P1 69 /* read EPROM partition 1 */ 144#define HFI1_CMD_EP_WRITE_P0 70 /* write EPROM partition 0 */ 145#define HFI1_CMD_EP_WRITE_P1 71 /* write EPROM partition 1 */ 146 147#define _HFI1_EVENT_FROZEN_BIT 0 148#define _HFI1_EVENT_LINKDOWN_BIT 1 149#define _HFI1_EVENT_LID_CHANGE_BIT 2 150#define _HFI1_EVENT_LMC_CHANGE_BIT 3 151#define _HFI1_EVENT_SL2VL_CHANGE_BIT 4 152#define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_SL2VL_CHANGE_BIT 153 154#define HFI1_EVENT_FROZEN (1UL << _HFI1_EVENT_FROZEN_BIT) 155#define HFI1_EVENT_LINKDOWN_BIT (1UL << _HFI1_EVENT_LINKDOWN_BIT) 156#define HFI1_EVENT_LID_CHANGE_BIT (1UL << _HFI1_EVENT_LID_CHANGE_BIT) 157#define HFI1_EVENT_LMC_CHANGE_BIT (1UL << _HFI1_EVENT_LMC_CHANGE_BIT) 158#define HFI1_EVENT_SL2VL_CHANGE_BIT (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT) 159 160/* 161 * These are the status bits readable (in ASCII form, 64bit value) 162 * from the "status" sysfs file. For binary compatibility, values 163 * must remain as is; removed states can be reused for different 164 * purposes. 165 */ 166#define HFI1_STATUS_INITTED 0x1 /* basic initialization done */ 167/* Chip has been found and initialized */ 168#define HFI1_STATUS_CHIP_PRESENT 0x20 169/* IB link is at ACTIVE, usable for data traffic */ 170#define HFI1_STATUS_IB_READY 0x40 171/* link is configured, LID, MTU, etc. have been set */ 172#define HFI1_STATUS_IB_CONF 0x80 173/* A Fatal hardware error has occurred. */ 174#define HFI1_STATUS_HWERROR 0x200 175 176/* 177 * Number of supported shared contexts. 178 * This is the maximum number of software contexts that can share 179 * a hardware send/receive context. 180 */ 181#define HFI1_MAX_SHARED_CTXTS 8 182 183/* 184 * Poll types 185 */ 186#define HFI1_POLL_TYPE_ANYRCV 0x0 187#define HFI1_POLL_TYPE_URGENT 0x1 188 189/* 190 * This structure is passed to the driver to tell it where 191 * user code buffers are, sizes, etc. The offsets and sizes of the 192 * fields must remain unchanged, for binary compatibility. It can 193 * be extended, if userversion is changed so user code can tell, if needed 194 */ 195struct hfi1_user_info { 196 /* 197 * version of user software, to detect compatibility issues. 198 * Should be set to HFI1_USER_SWVERSION. 199 */ 200 __u32 userversion; 201 __u16 pad; 202 /* HFI selection algorithm, if unit has not selected */ 203 __u16 hfi1_alg; 204 /* 205 * If two or more processes wish to share a context, each process 206 * must set the subcontext_cnt and subcontext_id to the same 207 * values. The only restriction on the subcontext_id is that 208 * it be unique for a given node. 209 */ 210 __u16 subctxt_cnt; 211 __u16 subctxt_id; 212 /* 128bit UUID passed in by PSM. */ 213 __u8 uuid[16]; 214}; 215 216struct hfi1_ctxt_info { 217 __u64 runtime_flags; /* chip/drv runtime flags (HFI1_CAP_*) */ 218 __u32 rcvegr_size; /* size of each eager buffer */ 219 __u16 num_active; /* number of active units */ 220 __u16 unit; /* unit (chip) assigned to caller */ 221 __u16 ctxt; /* ctxt on unit assigned to caller */ 222 __u16 subctxt; /* subctxt on unit assigned to caller */ 223 __u16 rcvtids; /* number of Rcv TIDs for this context */ 224 __u16 credits; /* number of PIO credits for this context */ 225 __u16 numa_node; /* NUMA node of the assigned device */ 226 __u16 rec_cpu; /* cpu # for affinity (0xffff if none) */ 227 __u16 send_ctxt; /* send context in use by this user context */ 228 __u16 egrtids; /* number of RcvArray entries for Eager Rcvs */ 229 __u16 rcvhdrq_cnt; /* number of RcvHdrQ entries */ 230 __u16 rcvhdrq_entsize; /* size (in bytes) for each RcvHdrQ entry */ 231 __u16 sdma_ring_size; /* number of entries in SDMA request ring */ 232}; 233 234struct hfi1_tid_info { 235 /* virtual address of first page in transfer */ 236 __u64 vaddr; 237 /* pointer to tid array. this array is big enough */ 238 __u64 tidlist; 239 /* number of tids programmed by this request */ 240 __u32 tidcnt; 241 /* length of transfer buffer programmed by this request */ 242 __u32 length; 243 /* 244 * pointer to bitmap of TIDs used for this call; 245 * checked for being large enough at open 246 */ 247 __u64 tidmap; 248}; 249 250struct hfi1_cmd { 251 __u32 type; /* command type */ 252 __u32 len; /* length of struct pointed to by add */ 253 __u64 addr; /* pointer to user structure */ 254}; 255 256enum hfi1_sdma_comp_state { 257 FREE = 0, 258 QUEUED, 259 COMPLETE, 260 ERROR 261}; 262 263/* 264 * SDMA completion ring entry 265 */ 266struct hfi1_sdma_comp_entry { 267 __u32 status; 268 __u32 errcode; 269}; 270 271/* 272 * Device status and notifications from driver to user-space. 273 */ 274struct hfi1_status { 275 __u64 dev; /* device/hw status bits */ 276 __u64 port; /* port state and status bits */ 277 char freezemsg[0]; 278}; 279 280/* 281 * This structure is returned by the driver immediately after 282 * open to get implementation-specific info, and info specific to this 283 * instance. 284 * 285 * This struct must have explicit pad fields where type sizes 286 * may result in different alignments between 32 and 64 bit 287 * programs, since the 64 bit * bit kernel requires the user code 288 * to have matching offsets 289 */ 290struct hfi1_base_info { 291 /* version of hardware, for feature checking. */ 292 __u32 hw_version; 293 /* version of software, for feature checking. */ 294 __u32 sw_version; 295 /* Job key */ 296 __u16 jkey; 297 __u16 padding1; 298 /* 299 * The special QP (queue pair) value that identifies PSM 300 * protocol packet from standard IB packets. 301 */ 302 __u32 bthqp; 303 /* PIO credit return address, */ 304 __u64 sc_credits_addr; 305 /* 306 * Base address of write-only pio buffers for this process. 307 * Each buffer has sendpio_credits*64 bytes. 308 */ 309 __u64 pio_bufbase_sop; 310 /* 311 * Base address of write-only pio buffers for this process. 312 * Each buffer has sendpio_credits*64 bytes. 313 */ 314 __u64 pio_bufbase; 315 /* address where receive buffer queue is mapped into */ 316 __u64 rcvhdr_bufbase; 317 /* base address of Eager receive buffers. */ 318 __u64 rcvegr_bufbase; 319 /* base address of SDMA completion ring */ 320 __u64 sdma_comp_bufbase; 321 /* 322 * User register base for init code, not to be used directly by 323 * protocol or applications. Always maps real chip register space. 324 * the register addresses are: 325 * ur_rcvhdrhead, ur_rcvhdrtail, ur_rcvegrhead, ur_rcvegrtail, 326 * ur_rcvtidflow 327 */ 328 __u64 user_regbase; 329 /* notification events */ 330 __u64 events_bufbase; 331 /* status page */ 332 __u64 status_bufbase; 333 /* rcvhdrtail update */ 334 __u64 rcvhdrtail_base; 335 /* 336 * shared memory pages for subctxts if ctxt is shared; these cover 337 * all the processes in the group sharing a single context. 338 * all have enough space for the num_subcontexts value on this job. 339 */ 340 __u64 subctxt_uregbase; 341 __u64 subctxt_rcvegrbuf; 342 __u64 subctxt_rcvhdrbuf; 343}; 344 345enum sdma_req_opcode { 346 EXPECTED = 0, 347 EAGER 348}; 349 350#define HFI1_SDMA_REQ_VERSION_MASK 0xF 351#define HFI1_SDMA_REQ_VERSION_SHIFT 0x0 352#define HFI1_SDMA_REQ_OPCODE_MASK 0xF 353#define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4 354#define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF 355#define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8 356 357struct sdma_req_info { 358 /* 359 * bits 0-3 - version (currently unused) 360 * bits 4-7 - opcode (enum sdma_req_opcode) 361 * bits 8-15 - io vector count 362 */ 363 __u16 ctrl; 364 /* 365 * Number of fragments contained in this request. 366 * User-space has already computed how many 367 * fragment-sized packet the user buffer will be 368 * split into. 369 */ 370 __u16 npkts; 371 /* 372 * Size of each fragment the user buffer will be 373 * split into. 374 */ 375 __u16 fragsize; 376 /* 377 * Index of the slot in the SDMA completion ring 378 * this request should be using. User-space is 379 * in charge of managing its own ring. 380 */ 381 __u16 comp_idx; 382} __packed; 383 384/* 385 * SW KDETH header. 386 * swdata is SW defined portion. 387 */ 388struct hfi1_kdeth_header { 389 __le32 ver_tid_offset; 390 __le16 jkey; 391 __le16 hcrc; 392 __le32 swdata[7]; 393} __packed; 394 395/* 396 * Structure describing the headers that User space uses. The 397 * structure above is a subset of this one. 398 */ 399struct hfi1_pkt_header { 400 __le16 pbc[4]; 401 __be16 lrh[4]; 402 __be32 bth[3]; 403 struct hfi1_kdeth_header kdeth; 404} __packed; 405 406 407/* 408 * The list of usermode accessible registers. 409 */ 410enum hfi1_ureg { 411 /* (RO) DMA RcvHdr to be used next. */ 412 ur_rcvhdrtail = 0, 413 /* (RW) RcvHdr entry to be processed next by host. */ 414 ur_rcvhdrhead = 1, 415 /* (RO) Index of next Eager index to use. */ 416 ur_rcvegrindextail = 2, 417 /* (RW) Eager TID to be processed next */ 418 ur_rcvegrindexhead = 3, 419 /* (RO) Receive Eager Offset Tail */ 420 ur_rcvegroffsettail = 4, 421 /* For internal use only; max register number. */ 422 ur_maxreg, 423 /* (RW) Receive TID flow table */ 424 ur_rcvtidflowtable = 256 425}; 426 427#endif /* _LINIUX__HFI1_USER_H */ 428