MachineInstr.h revision b27087f5aa574f875598f4a309b7dd687c64a455
1//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MachineInstr class, which is the 11// basic representation for all target dependent machine instructions used by 12// the back end. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_CODEGEN_MACHINEINSTR_H 17#define LLVM_CODEGEN_MACHINEINSTR_H 18 19#include "llvm/CodeGen/MachineOperand.h" 20#include "llvm/CodeGen/MemOperand.h" 21 22namespace llvm { 23 24class TargetInstrDesc; 25class TargetInstrInfo; 26class TargetRegisterInfo; 27 28template <typename T> struct ilist_traits; 29template <typename T> struct ilist; 30 31//===----------------------------------------------------------------------===// 32/// MachineInstr - Representation of each machine instruction. 33/// 34class MachineInstr { 35 const TargetInstrDesc *TID; // Instruction descriptor. 36 unsigned short NumImplicitOps; // Number of implicit operands (which 37 // are determined at construction time). 38 39 std::vector<MachineOperand> Operands; // the operands 40 std::vector<MemOperand> MemOperands; // information on memory references 41 MachineInstr *Prev, *Next; // Links for MBB's intrusive list. 42 MachineBasicBlock *Parent; // Pointer to the owning basic block. 43 44 // OperandComplete - Return true if it's illegal to add a new operand 45 bool OperandsComplete() const; 46 47 MachineInstr(const MachineInstr&); 48 void operator=(const MachineInstr&); // DO NOT IMPLEMENT 49 50 // Intrusive list support 51 friend struct ilist_traits<MachineInstr>; 52 friend struct ilist_traits<MachineBasicBlock>; 53 void setParent(MachineBasicBlock *P) { Parent = P; } 54public: 55 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with 56 /// TID NULL and no operands. 57 MachineInstr(); 58 59 /// MachineInstr ctor - This constructor create a MachineInstr and add the 60 /// implicit operands. It reserves space for number of operands specified by 61 /// TargetInstrDesc. 62 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false); 63 64 /// MachineInstr ctor - Work exactly the same as the ctor above, except that 65 /// the MachineInstr is created and added to the end of the specified basic 66 /// block. 67 /// 68 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID); 69 70 ~MachineInstr(); 71 72 const MachineBasicBlock* getParent() const { return Parent; } 73 MachineBasicBlock* getParent() { return Parent; } 74 75 /// getDesc - Returns the target instruction descriptor of this 76 /// MachineInstr. 77 const TargetInstrDesc &getDesc() const { return *TID; } 78 79 /// getOpcode - Returns the opcode of this MachineInstr. 80 /// 81 int getOpcode() const; 82 83 /// Access to explicit operands of the instruction. 84 /// 85 unsigned getNumOperands() const { return Operands.size(); } 86 87 const MachineOperand& getOperand(unsigned i) const { 88 assert(i < getNumOperands() && "getOperand() out of range!"); 89 return Operands[i]; 90 } 91 MachineOperand& getOperand(unsigned i) { 92 assert(i < getNumOperands() && "getOperand() out of range!"); 93 return Operands[i]; 94 } 95 96 /// getNumExplicitOperands - Returns the number of non-implicit operands. 97 /// 98 unsigned getNumExplicitOperands() const; 99 100 /// Access to memory operands of the instruction 101 unsigned getNumMemOperands() const { return MemOperands.size(); } 102 103 const MemOperand& getMemOperand(unsigned i) const { 104 assert(i < getNumMemOperands() && "getMemOperand() out of range!"); 105 return MemOperands[i]; 106 } 107 MemOperand& getMemOperand(unsigned i) { 108 assert(i < getNumMemOperands() && "getMemOperand() out of range!"); 109 return MemOperands[i]; 110 } 111 112 /// isIdenticalTo - Return true if this instruction is identical to (same 113 /// opcode and same operands as) the specified instruction. 114 bool isIdenticalTo(const MachineInstr *Other) const { 115 if (Other->getOpcode() != getOpcode() || 116 Other->getNumOperands() != getNumOperands()) 117 return false; 118 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 119 if (!getOperand(i).isIdenticalTo(Other->getOperand(i))) 120 return false; 121 return true; 122 } 123 124 /// clone - Create a copy of 'this' instruction that is identical in 125 /// all ways except the the instruction has no parent, prev, or next. 126 MachineInstr* clone() const { return new MachineInstr(*this); } 127 128 /// removeFromParent - This method unlinks 'this' from the containing basic 129 /// block, and returns it, but does not delete it. 130 MachineInstr *removeFromParent(); 131 132 /// eraseFromParent - This method unlinks 'this' from the containing basic 133 /// block and deletes it. 134 void eraseFromParent() { 135 delete removeFromParent(); 136 } 137 138 /// isDebugLabel - Returns true if the MachineInstr represents a debug label. 139 /// 140 bool isDebugLabel() const; 141 142 /// readsRegister - Return true if the MachineInstr reads the specified 143 /// register. If TargetRegisterInfo is passed, then it also checks if there 144 /// is a read of a super-register. 145 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 146 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 147 } 148 149 /// killsRegister - Return true if the MachineInstr kills the specified 150 /// register. If TargetRegisterInfo is passed, then it also checks if there is 151 /// a kill of a super-register. 152 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { 153 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 154 } 155 156 /// modifiesRegister - Return true if the MachineInstr modifies the 157 /// specified register. If TargetRegisterInfo is passed, then it also checks 158 /// if there is a def of a super-register. 159 bool modifiesRegister(unsigned Reg, 160 const TargetRegisterInfo *TRI = NULL) const { 161 return findRegisterDefOperandIdx(Reg, false, TRI) != -1; 162 } 163 164 /// registerDefIsDead - Returns true if the register is dead in this machine 165 /// instruction. If TargetRegisterInfo is passed, then it also checks 166 /// if there is a dead def of a super-register. 167 bool registerDefIsDead(unsigned Reg, 168 const TargetRegisterInfo *TRI = NULL) const { 169 return findRegisterDefOperandIdx(Reg, true, TRI) != -1; 170 } 171 172 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of 173 /// the specific register or -1 if it is not found. It further tightening 174 /// the search criteria to a use that kills the register if isKill is true. 175 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, 176 const TargetRegisterInfo *TRI = NULL) const; 177 178 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns 179 /// a pointer to the MachineOperand rather than an index. 180 MachineOperand *findRegisterUseOperand(unsigned Reg,bool isKill = false, 181 const TargetRegisterInfo *TRI = NULL) { 182 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); 183 return (Idx == -1) ? NULL : &getOperand(Idx); 184 } 185 186 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of 187 /// the specific register or -1 if it is not found. It further tightening 188 /// the search criteria to a def that is dead the register if isDead is true. 189 /// If TargetRegisterInfo is passed, then it also checks if there is a def of 190 /// a super-register. 191 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false, 192 const TargetRegisterInfo *TRI = NULL) const; 193 194 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns 195 /// a pointer to the MachineOperand rather than an index. 196 MachineOperand *findRegisterDefOperand(unsigned Reg,bool isDead = false, 197 const TargetRegisterInfo *TRI = NULL) { 198 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI); 199 return (Idx == -1) ? NULL : &getOperand(Idx); 200 } 201 202 /// findFirstPredOperandIdx() - Find the index of the first operand in the 203 /// operand list that is used to represent the predicate. It returns -1 if 204 /// none is found. 205 int findFirstPredOperandIdx() const; 206 207 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due 208 /// to two addr elimination. 209 bool isRegReDefinedByTwoAddr(unsigned Reg) const; 210 211 /// copyKillDeadInfo - Copies kill / dead operand properties from MI. 212 /// 213 void copyKillDeadInfo(const MachineInstr *MI); 214 215 /// copyPredicates - Copies predicate operand(s) from MI. 216 void copyPredicates(const MachineInstr *MI); 217 218 /// addRegisterKilled - We have determined MI kills a register. Look for the 219 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, 220 /// add a implicit operand if it's not found. Returns true if the operand 221 /// exists / is added. 222 bool addRegisterKilled(unsigned IncomingReg, 223 const TargetRegisterInfo *RegInfo, 224 bool AddIfNotFound = false); 225 226 /// addRegisterDead - We have determined MI defined a register without a use. 227 /// Look for the operand that defines it and mark it as IsDead. If 228 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns 229 /// true if the operand exists / is added. 230 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, 231 bool AddIfNotFound = false); 232 233 /// copyKillDeadInfo - Copies killed/dead information from one instr to another 234 void copyKillDeadInfo(MachineInstr *OldMI, 235 const TargetRegisterInfo *RegInfo); 236 237 /// isSafeToMove - Return true if it is safe to this instruction. If SawStore 238 /// true, it means there is a store (or call) between the instruction the 239 /// localtion and its intended destination. 240 bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore); 241 242 // 243 // Debugging support 244 // 245 void print(std::ostream *OS, const TargetMachine *TM) const { 246 if (OS) print(*OS, TM); 247 } 248 void print(std::ostream &OS, const TargetMachine *TM = 0) const; 249 void print(std::ostream *OS) const { if (OS) print(*OS); } 250 void dump() const; 251 252 //===--------------------------------------------------------------------===// 253 // Accessors used to build up machine instructions. 254 255 /// addOperand - Add the specified operand to the instruction. If it is an 256 /// implicit operand, it is added to the end of the operand list. If it is 257 /// an explicit operand it is added at the end of the explicit operand list 258 /// (before the first implicit operand). 259 void addOperand(const MachineOperand &Op); 260 261 /// setDesc - Replace the instruction descriptor (thus opcode) of 262 /// the current instruction with a new one. 263 /// 264 void setDesc(const TargetInstrDesc &tid) { TID = &tid; } 265 266 /// RemoveOperand - Erase an operand from an instruction, leaving it with one 267 /// fewer operand than it started with. 268 /// 269 void RemoveOperand(unsigned i); 270 271 /// addMemOperand - Add a MemOperand to the machine instruction, referencing 272 /// arbitrary storage. 273 void addMemOperand(const MemOperand &MO) { 274 MemOperands.push_back(MO); 275 } 276 277private: 278 /// getRegInfo - If this instruction is embedded into a MachineFunction, 279 /// return the MachineRegisterInfo object for the current function, otherwise 280 /// return null. 281 MachineRegisterInfo *getRegInfo(); 282 283 /// addImplicitDefUseOperands - Add all implicit def and use operands to 284 /// this instruction. 285 void addImplicitDefUseOperands(); 286 287 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 288 /// this instruction from their respective use lists. This requires that the 289 /// operands already be on their use lists. 290 void RemoveRegOperandsFromUseLists(); 291 292 /// AddRegOperandsToUseLists - Add all of the register operands in 293 /// this instruction from their respective use lists. This requires that the 294 /// operands not be on their use lists yet. 295 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo); 296}; 297 298//===----------------------------------------------------------------------===// 299// Debugging Support 300 301inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) { 302 MI.print(OS); 303 return OS; 304} 305 306} // End llvm namespace 307 308#endif 309