1//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief TargetRegisterInfo interface that is implemented by all hw codegen
12/// targets.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_R600_AMDGPUREGISTERINFO_H
17#define LLVM_LIB_TARGET_R600_AMDGPUREGISTERINFO_H
18
19#include "llvm/ADT/BitVector.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21
22#define GET_REGINFO_HEADER
23#define GET_REGINFO_ENUM
24#include "AMDGPUGenRegisterInfo.inc"
25
26namespace llvm {
27
28class AMDGPUSubtarget;
29class TargetInstrInfo;
30
31struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
32  static const MCPhysReg CalleeSavedReg;
33
34  AMDGPURegisterInfo();
35
36  BitVector getReservedRegs(const MachineFunction &MF) const override {
37    assert(!"Unimplemented");  return BitVector();
38  }
39
40  virtual unsigned getHWRegIndex(unsigned Reg) const {
41    assert(!"Unimplemented"); return 0;
42  }
43
44  /// \returns the sub reg enum value for the given \p Channel
45  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
46  unsigned getSubRegFromChannel(unsigned Channel) const;
47
48  const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
49  void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
50                           unsigned FIOperandNum,
51                           RegScavenger *RS) const override;
52  unsigned getFrameRegister(const MachineFunction &MF) const override;
53
54  unsigned getIndirectSubReg(unsigned IndirectIndex) const;
55
56};
57
58} // End namespace llvm
59
60#endif
61