1//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief R600 implementation of the TargetRegisterInfo class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "R600RegisterInfo.h"
16#include "AMDGPUTargetMachine.h"
17#include "R600Defines.h"
18#include "R600InstrInfo.h"
19#include "R600MachineFunctionInfo.h"
20
21using namespace llvm;
22
23R600RegisterInfo::R600RegisterInfo() : AMDGPURegisterInfo() {
24  RCW.RegWeight = 0;
25  RCW.WeightLimit = 0;
26}
27
28BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
29  BitVector Reserved(getNumRegs());
30
31  const R600InstrInfo *TII =
32      static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo());
33
34  Reserved.set(AMDGPU::ZERO);
35  Reserved.set(AMDGPU::HALF);
36  Reserved.set(AMDGPU::ONE);
37  Reserved.set(AMDGPU::ONE_INT);
38  Reserved.set(AMDGPU::NEG_HALF);
39  Reserved.set(AMDGPU::NEG_ONE);
40  Reserved.set(AMDGPU::PV_X);
41  Reserved.set(AMDGPU::ALU_LITERAL_X);
42  Reserved.set(AMDGPU::ALU_CONST);
43  Reserved.set(AMDGPU::PREDICATE_BIT);
44  Reserved.set(AMDGPU::PRED_SEL_OFF);
45  Reserved.set(AMDGPU::PRED_SEL_ZERO);
46  Reserved.set(AMDGPU::PRED_SEL_ONE);
47  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
48
49  for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
50                        E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
51    Reserved.set(*I);
52  }
53
54  TII->reserveIndirectRegisters(Reserved, MF);
55
56  return Reserved;
57}
58
59unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
60  return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
61}
62
63unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
64  return GET_REG_INDEX(getEncodingValue(Reg));
65}
66
67const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
68                                                                   MVT VT) const {
69  switch(VT.SimpleTy) {
70  default:
71  case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
72  }
73}
74
75const RegClassWeight &R600RegisterInfo::getRegClassWeight(
76  const TargetRegisterClass *RC) const {
77  return RCW;
78}
79
80bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
81  assert(!TargetRegisterInfo::isVirtualRegister(Reg));
82
83  switch (Reg) {
84  case AMDGPU::OQAP:
85  case AMDGPU::OQBP:
86  case AMDGPU::AR_X:
87    return false;
88  default:
89    return true;
90  }
91}
92