1//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains small standalone helper functions and enum definitions for
11// the Hexagon target useful for the compiler back-end and the MC libraries.
12// As such, it deliberately does not include references to LLVM core
13// code gen types, passes, etc..
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
18#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
19
20#include "HexagonMCTargetDesc.h"
21#include "llvm/Support/ErrorHandling.h"
22#include <stdint.h>
23
24namespace llvm {
25
26/// HexagonII - This namespace holds all of the target specific flags that
27/// instruction info tracks.
28///
29namespace HexagonII {
30  // *** The code below must match HexagonInstrFormat*.td *** //
31
32  // Insn types.
33  // *** Must match HexagonInstrFormat*.td ***
34  enum Type {
35    TypePSEUDO  = 0,
36    TypeALU32   = 1,
37    TypeCR      = 2,
38    TypeJR      = 3,
39    TypeJ       = 4,
40    TypeLD      = 5,
41    TypeST      = 6,
42    TypeSYSTEM  = 7,
43    TypeXTYPE   = 8,
44    TypeMEMOP   = 9,
45    TypeNV      = 10,
46    TypeDUPLEX  = 11,
47    TypeCOMPOUND = 12,
48    TypeCVI_FIRST     = 13,
49    TypeCVI_VA        = TypeCVI_FIRST,
50    TypeCVI_VA_DV     = 14,
51    TypeCVI_VX        = 15,
52    TypeCVI_VX_DV     = 16,
53    TypeCVI_VP        = 17,
54    TypeCVI_VP_VS     = 18,
55    TypeCVI_VS        = 19,
56    TypeCVI_VINLANESAT= 20,
57    TypeCVI_VM_LD     = 21,
58    TypeCVI_VM_TMP_LD = 22,
59    TypeCVI_VM_CUR_LD = 23,
60    TypeCVI_VM_VP_LDU = 24,
61    TypeCVI_VM_ST     = 25,
62    TypeCVI_VM_NEW_ST = 26,
63    TypeCVI_VM_STU    = 27,
64    TypeCVI_HIST      = 28,
65    TypeCVI_LAST      = TypeCVI_HIST,
66    TypePREFIX  = 30, // Such as extenders.
67    TypeENDLOOP = 31  // Such as end of a HW loop.
68  };
69
70  enum SubTarget {
71    HasV2SubT     = 0xf,
72    HasV2SubTOnly = 0x1,
73    NoV2SubT      = 0x0,
74    HasV3SubT     = 0xe,
75    HasV3SubTOnly = 0x2,
76    NoV3SubT      = 0x1,
77    HasV4SubT     = 0xc,
78    NoV4SubT      = 0x3,
79    HasV5SubT     = 0x8,
80    NoV5SubT      = 0x7
81  };
82
83  enum AddrMode {
84    NoAddrMode     = 0,  // No addressing mode
85    Absolute       = 1,  // Absolute addressing mode
86    AbsoluteSet    = 2,  // Absolute set addressing mode
87    BaseImmOffset  = 3,  // Indirect with offset
88    BaseLongOffset = 4,  // Indirect with long offset
89    BaseRegOffset  = 5,  // Indirect with register offset
90    PostInc        = 6   // Post increment addressing mode
91  };
92
93  // MemAccessSize is represented as 1+log2(N) where N is size in bits.
94  enum class MemAccessSize {
95    NoMemAccess = 0,            // Not a memory acces instruction.
96    ByteAccess = 1,             // Byte access instruction (memb).
97    HalfWordAccess = 2,         // Half word access instruction (memh).
98    WordAccess = 3,             // Word access instruction (memw).
99    DoubleWordAccess = 4,       // Double word access instruction (memd)
100                    // 5,       // We do not have a 16 byte vector access.
101    Vector64Access = 7,         // 64 Byte vector access instruction (vmem).
102    Vector128Access = 8         // 128 Byte vector access instruction (vmem).
103  };
104
105  // MCInstrDesc TSFlags
106  // *** Must match HexagonInstrFormat*.td ***
107  enum {
108    // This 5-bit field describes the insn type.
109    TypePos  = 0,
110    TypeMask = 0x1f,
111
112    // Solo instructions.
113    SoloPos  = 5,
114    SoloMask = 0x1,
115    // Packed only with A or X-type instructions.
116    SoloAXPos  = 6,
117    SoloAXMask = 0x1,
118    // Only A-type instruction in first slot or nothing.
119    SoloAin1Pos  = 7,
120    SoloAin1Mask = 0x1,
121
122    // Predicated instructions.
123    PredicatedPos  = 8,
124    PredicatedMask = 0x1,
125    PredicatedFalsePos  = 9,
126    PredicatedFalseMask = 0x1,
127    PredicatedNewPos  = 10,
128    PredicatedNewMask = 0x1,
129    PredicateLatePos  = 11,
130    PredicateLateMask = 0x1,
131
132    // New-Value consumer instructions.
133    NewValuePos  = 12,
134    NewValueMask = 0x1,
135    // New-Value producer instructions.
136    hasNewValuePos  = 13,
137    hasNewValueMask = 0x1,
138    // Which operand consumes or produces a new value.
139    NewValueOpPos  = 14,
140    NewValueOpMask = 0x7,
141    // Stores that can become new-value stores.
142    mayNVStorePos  = 17,
143    mayNVStoreMask = 0x1,
144    // New-value store instructions.
145    NVStorePos  = 18,
146    NVStoreMask = 0x1,
147    // Loads that can become current-value loads.
148    mayCVLoadPos  = 19,
149    mayCVLoadMask = 0x1,
150    // Current-value load instructions.
151    CVLoadPos  = 20,
152    CVLoadMask = 0x1,
153
154    // Extendable insns.
155    ExtendablePos  = 21,
156    ExtendableMask = 0x1,
157    // Insns must be extended.
158    ExtendedPos  = 22,
159    ExtendedMask = 0x1,
160    // Which operand may be extended.
161    ExtendableOpPos  = 23,
162    ExtendableOpMask = 0x7,
163    // Signed or unsigned range.
164    ExtentSignedPos  = 26,
165    ExtentSignedMask = 0x1,
166    // Number of bits of range before extending operand.
167    ExtentBitsPos  = 27,
168    ExtentBitsMask = 0x1f,
169    // Alignment power-of-two before extending operand.
170    ExtentAlignPos  = 32,
171    ExtentAlignMask = 0x3,
172
173    // Valid subtargets
174    validSubTargetPos  = 34,
175    validSubTargetMask = 0xf,
176
177    // Addressing mode for load/store instructions.
178    AddrModePos  = 40,
179    AddrModeMask = 0x7,
180    // Access size for load/store instructions.
181    MemAccessSizePos = 43,
182    MemAccesSizeMask = 0xf,
183
184    // Branch predicted taken.
185    TakenPos = 47,
186    TakenMask = 0x1,
187
188    // Floating-point instructions.
189    FPPos  = 48,
190    FPMask = 0x1,
191
192    // New-Value producer-2 instructions.
193    hasNewValuePos2  = 50,
194    hasNewValueMask2 = 0x1,
195
196    // Which operand consumes or produces a new value.
197    NewValueOpPos2  = 51,
198    NewValueOpMask2 = 0x7,
199
200    // Accumulator instructions.
201    AccumulatorPos = 54,
202    AccumulatorMask = 0x1,
203
204    // Complex XU, prevent xu competition by prefering slot3
205    PrefersSlot3Pos = 55,
206    PrefersSlot3Mask = 0x1,
207  };
208
209  // *** The code above must match HexagonInstrFormat*.td *** //
210
211  // Hexagon specific MO operand flag mask.
212  enum HexagonMOTargetFlagVal {
213    //===------------------------------------------------------------------===//
214    // Hexagon Specific MachineOperand flags.
215    MO_NO_FLAG,
216
217    HMOTF_ConstExtended = 1,
218
219    /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
220    /// Used for computing a global address for PIC compilations
221    MO_PCREL,
222
223    /// MO_GOT - Indicates a GOT-relative relocation
224    MO_GOT,
225
226    // Low or high part of a symbol.
227    MO_LO16, MO_HI16,
228
229    // Offset from the base of the SDA.
230    MO_GPREL
231  };
232
233  // Hexagon Sub-instruction classes.
234  enum SubInstructionGroup {
235    HSIG_None = 0,
236    HSIG_L1,
237    HSIG_L2,
238    HSIG_S1,
239    HSIG_S2,
240    HSIG_A,
241    HSIG_Compound
242  };
243
244  // Hexagon Compound classes.
245  enum CompoundGroup {
246    HCG_None = 0,
247    HCG_A,
248    HCG_B,
249    HCG_C
250  };
251
252  enum InstParseBits {
253    INST_PARSE_MASK       = 0x0000c000,
254    INST_PARSE_PACKET_END = 0x0000c000,
255    INST_PARSE_LOOP_END   = 0x00008000,
256    INST_PARSE_NOT_END    = 0x00004000,
257    INST_PARSE_DUPLEX     = 0x00000000,
258    INST_PARSE_EXTENDER   = 0x00000000
259  };
260
261  enum InstIClassBits : unsigned {
262    INST_ICLASS_MASK      = 0xf0000000,
263    INST_ICLASS_EXTENDER  = 0x00000000,
264    INST_ICLASS_J_1       = 0x10000000,
265    INST_ICLASS_J_2       = 0x20000000,
266    INST_ICLASS_LD_ST_1   = 0x30000000,
267    INST_ICLASS_LD_ST_2   = 0x40000000,
268    INST_ICLASS_J_3       = 0x50000000,
269    INST_ICLASS_CR        = 0x60000000,
270    INST_ICLASS_ALU32_1   = 0x70000000,
271    INST_ICLASS_XTYPE_1   = 0x80000000,
272    INST_ICLASS_LD        = 0x90000000,
273    INST_ICLASS_ST        = 0xa0000000,
274    INST_ICLASS_ALU32_2   = 0xb0000000,
275    INST_ICLASS_XTYPE_2   = 0xc0000000,
276    INST_ICLASS_XTYPE_3   = 0xd0000000,
277    INST_ICLASS_XTYPE_4   = 0xe0000000,
278    INST_ICLASS_ALU32_3   = 0xf0000000
279  };
280
281} // End namespace HexagonII.
282
283} // End namespace llvm.
284
285#endif
286