1//===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "SystemZFrameLowering.h"
11#include "SystemZCallingConv.h"
12#include "SystemZInstrBuilder.h"
13#include "SystemZInstrInfo.h"
14#include "SystemZMachineFunctionInfo.h"
15#include "SystemZRegisterInfo.h"
16#include "SystemZSubtarget.h"
17#include "llvm/CodeGen/MachineModuleInfo.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/RegisterScavenging.h"
20#include "llvm/IR/Function.h"
21
22using namespace llvm;
23
24namespace {
25// The ABI-defined register save slots, relative to the incoming stack
26// pointer.
27static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
28  { SystemZ::R2D,  0x10 },
29  { SystemZ::R3D,  0x18 },
30  { SystemZ::R4D,  0x20 },
31  { SystemZ::R5D,  0x28 },
32  { SystemZ::R6D,  0x30 },
33  { SystemZ::R7D,  0x38 },
34  { SystemZ::R8D,  0x40 },
35  { SystemZ::R9D,  0x48 },
36  { SystemZ::R10D, 0x50 },
37  { SystemZ::R11D, 0x58 },
38  { SystemZ::R12D, 0x60 },
39  { SystemZ::R13D, 0x68 },
40  { SystemZ::R14D, 0x70 },
41  { SystemZ::R15D, 0x78 },
42  { SystemZ::F0D,  0x80 },
43  { SystemZ::F2D,  0x88 },
44  { SystemZ::F4D,  0x90 },
45  { SystemZ::F6D,  0x98 }
46};
47} // end anonymous namespace
48
49SystemZFrameLowering::SystemZFrameLowering()
50    : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8,
51                          -SystemZMC::CallFrameSize, 8,
52                          false /* StackRealignable */) {
53  // Create a mapping from register number to save slot offset.
54  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
55  for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; ++I)
56    RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
57}
58
59const TargetFrameLowering::SpillSlot *
60SystemZFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
61  NumEntries = array_lengthof(SpillOffsetTable);
62  return SpillOffsetTable;
63}
64
65void SystemZFrameLowering::determineCalleeSaves(MachineFunction &MF,
66                                                BitVector &SavedRegs,
67                                                RegScavenger *RS) const {
68  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
69
70  MachineFrameInfo *MFFrame = MF.getFrameInfo();
71  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
72  bool HasFP = hasFP(MF);
73  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
74  bool IsVarArg = MF.getFunction()->isVarArg();
75
76  // va_start stores incoming FPR varargs in the normal way, but delegates
77  // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
78  // Record these pending uses, which typically include the call-saved
79  // argument register R6D.
80  if (IsVarArg)
81    for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
82      SavedRegs.set(SystemZ::ArgGPRs[I]);
83
84  // If the function requires a frame pointer, record that the hard
85  // frame pointer will be clobbered.
86  if (HasFP)
87    SavedRegs.set(SystemZ::R11D);
88
89  // If the function calls other functions, record that the return
90  // address register will be clobbered.
91  if (MFFrame->hasCalls())
92    SavedRegs.set(SystemZ::R14D);
93
94  // If we are saving GPRs other than the stack pointer, we might as well
95  // save and restore the stack pointer at the same time, via STMG and LMG.
96  // This allows the deallocation to be done by the LMG, rather than needing
97  // a separate %r15 addition.
98  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
99  for (unsigned I = 0; CSRegs[I]; ++I) {
100    unsigned Reg = CSRegs[I];
101    if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
102      SavedRegs.set(SystemZ::R15D);
103      break;
104    }
105  }
106}
107
108// Add GPR64 to the save instruction being built by MIB, which is in basic
109// block MBB.  IsImplicit says whether this is an explicit operand to the
110// instruction, or an implicit one that comes between the explicit start
111// and end registers.
112static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
113                        unsigned GPR64, bool IsImplicit) {
114  const TargetRegisterInfo *RI =
115      MBB.getParent()->getSubtarget().getRegisterInfo();
116  unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
117  bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
118  if (!IsLive || !IsImplicit) {
119    MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
120    if (!IsLive)
121      MBB.addLiveIn(GPR64);
122  }
123}
124
125bool SystemZFrameLowering::
126spillCalleeSavedRegisters(MachineBasicBlock &MBB,
127                          MachineBasicBlock::iterator MBBI,
128                          const std::vector<CalleeSavedInfo> &CSI,
129                          const TargetRegisterInfo *TRI) const {
130  if (CSI.empty())
131    return false;
132
133  MachineFunction &MF = *MBB.getParent();
134  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
135  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
136  bool IsVarArg = MF.getFunction()->isVarArg();
137  DebugLoc DL;
138
139  // Scan the call-saved GPRs and find the bounds of the register spill area.
140  unsigned LowGPR = 0;
141  unsigned HighGPR = SystemZ::R15D;
142  unsigned StartOffset = -1U;
143  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
144    unsigned Reg = CSI[I].getReg();
145    if (SystemZ::GR64BitRegClass.contains(Reg)) {
146      unsigned Offset = RegSpillOffsets[Reg];
147      assert(Offset && "Unexpected GPR save");
148      if (StartOffset > Offset) {
149        LowGPR = Reg;
150        StartOffset = Offset;
151      }
152    }
153  }
154
155  // Save the range of call-saved registers, for use by the epilogue inserter.
156  ZFI->setLowSavedGPR(LowGPR);
157  ZFI->setHighSavedGPR(HighGPR);
158
159  // Include the GPR varargs, if any.  R6D is call-saved, so would
160  // be included by the loop above, but we also need to handle the
161  // call-clobbered argument registers.
162  if (IsVarArg) {
163    unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
164    if (FirstGPR < SystemZ::NumArgGPRs) {
165      unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
166      unsigned Offset = RegSpillOffsets[Reg];
167      if (StartOffset > Offset) {
168        LowGPR = Reg; StartOffset = Offset;
169      }
170    }
171  }
172
173  // Save GPRs
174  if (LowGPR) {
175    assert(LowGPR != HighGPR && "Should be saving %r15 and something else");
176
177    // Build an STMG instruction.
178    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
179
180    // Add the explicit register operands.
181    addSavedGPR(MBB, MIB, LowGPR, false);
182    addSavedGPR(MBB, MIB, HighGPR, false);
183
184    // Add the address.
185    MIB.addReg(SystemZ::R15D).addImm(StartOffset);
186
187    // Make sure all call-saved GPRs are included as operands and are
188    // marked as live on entry.
189    for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
190      unsigned Reg = CSI[I].getReg();
191      if (SystemZ::GR64BitRegClass.contains(Reg))
192        addSavedGPR(MBB, MIB, Reg, true);
193    }
194
195    // ...likewise GPR varargs.
196    if (IsVarArg)
197      for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
198        addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
199  }
200
201  // Save FPRs in the normal TargetInstrInfo way.
202  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
203    unsigned Reg = CSI[I].getReg();
204    if (SystemZ::FP64BitRegClass.contains(Reg)) {
205      MBB.addLiveIn(Reg);
206      TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
207                               &SystemZ::FP64BitRegClass, TRI);
208    }
209  }
210
211  return true;
212}
213
214bool SystemZFrameLowering::
215restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
216                            MachineBasicBlock::iterator MBBI,
217                            const std::vector<CalleeSavedInfo> &CSI,
218                            const TargetRegisterInfo *TRI) const {
219  if (CSI.empty())
220    return false;
221
222  MachineFunction &MF = *MBB.getParent();
223  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
224  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
225  bool HasFP = hasFP(MF);
226  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
227
228  // Restore FPRs in the normal TargetInstrInfo way.
229  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
230    unsigned Reg = CSI[I].getReg();
231    if (SystemZ::FP64BitRegClass.contains(Reg))
232      TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
233                                &SystemZ::FP64BitRegClass, TRI);
234  }
235
236  // Restore call-saved GPRs (but not call-clobbered varargs, which at
237  // this point might hold return values).
238  unsigned LowGPR = ZFI->getLowSavedGPR();
239  unsigned HighGPR = ZFI->getHighSavedGPR();
240  unsigned StartOffset = RegSpillOffsets[LowGPR];
241  if (LowGPR) {
242    // If we saved any of %r2-%r5 as varargs, we should also be saving
243    // and restoring %r6.  If we're saving %r6 or above, we should be
244    // restoring it too.
245    assert(LowGPR != HighGPR && "Should be loading %r15 and something else");
246
247    // Build an LMG instruction.
248    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
249
250    // Add the explicit register operands.
251    MIB.addReg(LowGPR, RegState::Define);
252    MIB.addReg(HighGPR, RegState::Define);
253
254    // Add the address.
255    MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
256    MIB.addImm(StartOffset);
257
258    // Do a second scan adding regs as being defined by instruction
259    for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
260      unsigned Reg = CSI[I].getReg();
261      if (Reg != LowGPR && Reg != HighGPR)
262        MIB.addReg(Reg, RegState::ImplicitDefine);
263    }
264  }
265
266  return true;
267}
268
269void SystemZFrameLowering::
270processFunctionBeforeFrameFinalized(MachineFunction &MF,
271                                    RegScavenger *RS) const {
272  MachineFrameInfo *MFFrame = MF.getFrameInfo();
273  uint64_t MaxReach = (MFFrame->estimateStackSize(MF) +
274                       SystemZMC::CallFrameSize * 2);
275  if (!isUInt<12>(MaxReach)) {
276    // We may need register scavenging slots if some parts of the frame
277    // are outside the reach of an unsigned 12-bit displacement.
278    // Create 2 for the case where both addresses in an MVC are
279    // out of range.
280    RS->addScavengingFrameIndex(MFFrame->CreateStackObject(8, 8, false));
281    RS->addScavengingFrameIndex(MFFrame->CreateStackObject(8, 8, false));
282  }
283}
284
285// Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
286static void emitIncrement(MachineBasicBlock &MBB,
287                          MachineBasicBlock::iterator &MBBI,
288                          const DebugLoc &DL,
289                          unsigned Reg, int64_t NumBytes,
290                          const TargetInstrInfo *TII) {
291  while (NumBytes) {
292    unsigned Opcode;
293    int64_t ThisVal = NumBytes;
294    if (isInt<16>(NumBytes))
295      Opcode = SystemZ::AGHI;
296    else {
297      Opcode = SystemZ::AGFI;
298      // Make sure we maintain 8-byte stack alignment.
299      int64_t MinVal = -uint64_t(1) << 31;
300      int64_t MaxVal = (int64_t(1) << 31) - 8;
301      if (ThisVal < MinVal)
302        ThisVal = MinVal;
303      else if (ThisVal > MaxVal)
304        ThisVal = MaxVal;
305    }
306    MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
307      .addReg(Reg).addImm(ThisVal);
308    // The CC implicit def is dead.
309    MI->getOperand(3).setIsDead();
310    NumBytes -= ThisVal;
311  }
312}
313
314void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
315                                        MachineBasicBlock &MBB) const {
316  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
317  MachineFrameInfo *MFFrame = MF.getFrameInfo();
318  auto *ZII =
319      static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
320  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
321  MachineBasicBlock::iterator MBBI = MBB.begin();
322  MachineModuleInfo &MMI = MF.getMMI();
323  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
324  const std::vector<CalleeSavedInfo> &CSI = MFFrame->getCalleeSavedInfo();
325  bool HasFP = hasFP(MF);
326
327  // Debug location must be unknown since the first debug location is used
328  // to determine the end of the prologue.
329  DebugLoc DL;
330
331  // The current offset of the stack pointer from the CFA.
332  int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
333
334  if (ZFI->getLowSavedGPR()) {
335    // Skip over the GPR saves.
336    if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
337      ++MBBI;
338    else
339      llvm_unreachable("Couldn't skip over GPR saves");
340
341    // Add CFI for the GPR saves.
342    for (auto &Save : CSI) {
343      unsigned Reg = Save.getReg();
344      if (SystemZ::GR64BitRegClass.contains(Reg)) {
345        int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
346        unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
347            nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
348        BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
349            .addCFIIndex(CFIIndex);
350      }
351    }
352  }
353
354  uint64_t StackSize = getAllocatedStackSize(MF);
355  if (StackSize) {
356    // Allocate StackSize bytes.
357    int64_t Delta = -int64_t(StackSize);
358    emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
359
360    // Add CFI for the allocation.
361    unsigned CFIIndex = MMI.addFrameInst(
362        MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
363    BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
364        .addCFIIndex(CFIIndex);
365    SPOffsetFromCFA += Delta;
366  }
367
368  if (HasFP) {
369    // Copy the base of the frame to R11.
370    BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
371      .addReg(SystemZ::R15D);
372
373    // Add CFI for the new frame location.
374    unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
375    unsigned CFIIndex = MMI.addFrameInst(
376        MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
377    BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
378        .addCFIIndex(CFIIndex);
379
380    // Mark the FramePtr as live at the beginning of every block except
381    // the entry block.  (We'll have marked R11 as live on entry when
382    // saving the GPRs.)
383    for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
384      I->addLiveIn(SystemZ::R11D);
385  }
386
387  // Skip over the FPR saves.
388  SmallVector<unsigned, 8> CFIIndexes;
389  for (auto &Save : CSI) {
390    unsigned Reg = Save.getReg();
391    if (SystemZ::FP64BitRegClass.contains(Reg)) {
392      if (MBBI != MBB.end() &&
393          (MBBI->getOpcode() == SystemZ::STD ||
394           MBBI->getOpcode() == SystemZ::STDY))
395        ++MBBI;
396      else
397        llvm_unreachable("Couldn't skip over FPR save");
398
399      // Add CFI for the this save.
400      unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
401      unsigned IgnoredFrameReg;
402      int64_t Offset =
403          getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
404
405      unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
406          nullptr, DwarfReg, SPOffsetFromCFA + Offset));
407      CFIIndexes.push_back(CFIIndex);
408    }
409  }
410  // Complete the CFI for the FPR saves, modelling them as taking effect
411  // after the last save.
412  for (auto CFIIndex : CFIIndexes) {
413    BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
414        .addCFIIndex(CFIIndex);
415  }
416}
417
418void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
419                                        MachineBasicBlock &MBB) const {
420  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
421  auto *ZII =
422      static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
423  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
424
425  // Skip the return instruction.
426  assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
427
428  uint64_t StackSize = getAllocatedStackSize(MF);
429  if (ZFI->getLowSavedGPR()) {
430    --MBBI;
431    unsigned Opcode = MBBI->getOpcode();
432    if (Opcode != SystemZ::LMG)
433      llvm_unreachable("Expected to see callee-save register restore code");
434
435    unsigned AddrOpNo = 2;
436    DebugLoc DL = MBBI->getDebugLoc();
437    uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
438    unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
439
440    // If the offset is too large, use the largest stack-aligned offset
441    // and add the rest to the base register (the stack or frame pointer).
442    if (!NewOpcode) {
443      uint64_t NumBytes = Offset - 0x7fff8;
444      emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
445                    NumBytes, ZII);
446      Offset -= NumBytes;
447      NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
448      assert(NewOpcode && "No restore instruction available");
449    }
450
451    MBBI->setDesc(ZII->get(NewOpcode));
452    MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
453  } else if (StackSize) {
454    DebugLoc DL = MBBI->getDebugLoc();
455    emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
456  }
457}
458
459bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const {
460  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
461          MF.getFrameInfo()->hasVarSizedObjects() ||
462          MF.getInfo<SystemZMachineFunctionInfo>()->getManipulatesSP());
463}
464
465int SystemZFrameLowering::getFrameIndexReference(const MachineFunction &MF,
466                                                 int FI,
467                                                 unsigned &FrameReg) const {
468  const MachineFrameInfo *MFFrame = MF.getFrameInfo();
469  const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
470
471  // Fill in FrameReg output argument.
472  FrameReg = RI->getFrameRegister(MF);
473
474  // Start with the offset of FI from the top of the caller-allocated frame
475  // (i.e. the top of the 160 bytes allocated by the caller).  This initial
476  // offset is therefore negative.
477  int64_t Offset = (MFFrame->getObjectOffset(FI) +
478                    MFFrame->getOffsetAdjustment());
479
480  // Make the offset relative to the incoming stack pointer.
481  Offset -= getOffsetOfLocalArea();
482
483  // Make the offset relative to the bottom of the frame.
484  Offset += getAllocatedStackSize(MF);
485
486  return Offset;
487}
488
489uint64_t SystemZFrameLowering::
490getAllocatedStackSize(const MachineFunction &MF) const {
491  const MachineFrameInfo *MFFrame = MF.getFrameInfo();
492
493  // Start with the size of the local variables and spill slots.
494  uint64_t StackSize = MFFrame->getStackSize();
495
496  // We need to allocate the ABI-defined 160-byte base area whenever
497  // we allocate stack space for our own use and whenever we call another
498  // function.
499  if (StackSize || MFFrame->hasVarSizedObjects() || MFFrame->hasCalls())
500    StackSize += SystemZMC::CallFrameSize;
501
502  return StackSize;
503}
504
505bool
506SystemZFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
507  // The ABI requires us to allocate 160 bytes of stack space for the callee,
508  // with any outgoing stack arguments being placed above that.  It seems
509  // better to make that area a permanent feature of the frame even if
510  // we're using a frame pointer.
511  return true;
512}
513
514void SystemZFrameLowering::
515eliminateCallFramePseudoInstr(MachineFunction &MF,
516                              MachineBasicBlock &MBB,
517                              MachineBasicBlock::iterator MI) const {
518  switch (MI->getOpcode()) {
519  case SystemZ::ADJCALLSTACKDOWN:
520  case SystemZ::ADJCALLSTACKUP:
521    assert(hasReservedCallFrame(MF) &&
522           "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
523    MBB.erase(MI);
524    break;
525
526  default:
527    llvm_unreachable("Unexpected call frame instruction");
528  }
529}
530