1//===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file provides X86 specific target descriptions. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 15#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 16 17#include "llvm/Support/DataTypes.h" 18#include <string> 19 20namespace llvm { 21class MCAsmBackend; 22class MCCodeEmitter; 23class MCContext; 24class MCInstrInfo; 25class MCObjectWriter; 26class MCRegisterInfo; 27class MCSubtargetInfo; 28class MCRelocationInfo; 29class MCStreamer; 30class Target; 31class Triple; 32class StringRef; 33class raw_ostream; 34class raw_pwrite_stream; 35 36extern Target TheX86_32Target, TheX86_64Target; 37 38/// Flavour of dwarf regnumbers 39/// 40namespace DWARFFlavour { 41 enum { 42 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 43 }; 44} 45 46/// Native X86 register numbers 47/// 48namespace N86 { 49 enum { 50 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 51 }; 52} 53 54namespace X86_MC { 55std::string ParseX86Triple(const Triple &TT); 56 57unsigned getDwarfRegFlavour(const Triple &TT, bool isEH); 58 59void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI); 60 61/// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. 62/// do not need to go through TargetRegistry. 63MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, 64 StringRef FS); 65} 66 67MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 68 const MCRegisterInfo &MRI, 69 MCContext &Ctx); 70 71MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, 72 const Triple &TT, StringRef CPU); 73MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, 74 const Triple &TT, StringRef CPU); 75 76/// Construct an X86 Windows COFF machine code streamer which will generate 77/// PE/COFF format object files. 78/// 79/// Takes ownership of \p AB and \p CE. 80MCStreamer *createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB, 81 raw_pwrite_stream &OS, MCCodeEmitter *CE, 82 bool RelaxAll, bool IncrementalLinkerCompatible); 83 84/// Construct an X86 Mach-O object writer. 85MCObjectWriter *createX86MachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, 86 uint32_t CPUType, 87 uint32_t CPUSubtype); 88 89/// Construct an X86 ELF object writer. 90MCObjectWriter *createX86ELFObjectWriter(raw_pwrite_stream &OS, bool IsELF64, 91 uint8_t OSABI, uint16_t EMachine); 92/// Construct an X86 Win COFF object writer. 93MCObjectWriter *createX86WinCOFFObjectWriter(raw_pwrite_stream &OS, 94 bool Is64Bit); 95 96/// Construct X86-64 Mach-O relocation info. 97MCRelocationInfo *createX86_64MachORelocationInfo(MCContext &Ctx); 98 99/// Construct X86-64 ELF relocation info. 100MCRelocationInfo *createX86_64ELFRelocationInfo(MCContext &Ctx); 101} // End llvm namespace 102 103 104// Defines symbolic names for X86 registers. This defines a mapping from 105// register name to register number. 106// 107#define GET_REGINFO_ENUM 108#include "X86GenRegisterInfo.inc" 109 110// Defines symbolic names for the X86 instructions. 111// 112#define GET_INSTRINFO_ENUM 113#include "X86GenInstrInfo.inc" 114 115#define GET_SUBTARGETINFO_ENUM 116#include "X86GenSubtargetInfo.inc" 117 118#endif 119