1/*
2// Copyright (c) 2014 Intel Corporation 
3//
4// Licensed under the Apache License, Version 2.0 (the "License");
5// you may not use this file except in compliance with the License.
6// You may obtain a copy of the License at
7//
8//      http://www.apache.org/licenses/LICENSE-2.0
9//
10// Unless required by applicable law or agreed to in writing, software
11// distributed under the License is distributed on an "AS IS" BASIS,
12// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13// See the License for the specific language governing permissions and
14// limitations under the License.
15*/
16#ifndef OVERLAY_HARDWARE_H
17#define OVERLAY_HARDWARE_H
18
19namespace android {
20namespace intel {
21
22// only one overlay data buffer for testing
23#define INTEL_OVERLAY_BUFFER_NUM          1
24#define INTEL_OVERLAY_MAX_WIDTH         2048
25#define INTEL_OVERLAY_MAX_HEIGHT        2048
26#define INTEL_OVERLAY_MIN_STRIDE        512
27#define INTEL_OVERLAY_MAX_STRIDE_PACKED (8 * 1024)
28#define INTEL_OVERLAY_MAX_STRIDE_LINEAR (4 * 1024)
29#define INTEL_OVERLAY_MAX_SCALING_RATIO   7
30
31// Polyphase filter coefficients
32#define N_HORIZ_Y_TAPS                  5
33#define N_VERT_Y_TAPS                   3
34#define N_HORIZ_UV_TAPS                 3
35#define N_VERT_UV_TAPS                  3
36#define N_PHASES                        17
37#define MAX_TAPS                        5
38#define XRGB_BPP                        4
39
40// Filter cutoff frequency limits.
41#define MIN_CUTOFF_FREQ                 1.0
42#define MAX_CUTOFF_FREQ                 3.0
43
44// Overlay init micros
45#define OVERLAY_INIT_CONTRAST           0x4b
46#define OVERLAY_INIT_BRIGHTNESS         -19
47#define OVERLAY_INIT_SATURATION         0x92
48#define OVERLAY_INIT_GAMMA0             0x080808
49#define OVERLAY_INIT_GAMMA1             0x101010
50#define OVERLAY_INIT_GAMMA2             0x202020
51#define OVERLAY_INIT_GAMMA3             0x404040
52#define OVERLAY_INIT_GAMMA4             0x808080
53#define OVERLAY_INIT_GAMMA5             0xc0c0c0
54#define OVERLAY_INIT_COLORKEY           0
55#define OVERLAY_INIT_COLORKEYMASK       ((0x0 << 31) | (0X0 << 30))
56#define OVERLAY_INIT_CONFIG             ((0x1 << 18) | (0x1 << 3))
57
58// overlay register values
59#define OVERLAY_FORMAT_MASK             (0xf << 10)
60#define OVERLAY_FORMAT_PLANAR_XRGB      (0x1 << 10)
61#define OVERLAY_FORMAT_PACKED_YUV422    (0x8 << 10)
62#define OVERLAY_FORMAT_PLANAR_NV12_1    (0x7 << 10)
63#define OVERLAY_FORMAT_PLANAR_NV12_2    (0xb << 10)
64#define OVERLAY_FORMAT_PLANAR_YUV420    (0xc << 10)
65#define OVERLAY_FORMAT_PLANAR_YUV422    (0xd << 10)
66#define OVERLAY_FORMAT_PLANAR_YUV41X    (0xe << 10)
67
68#define OVERLAY_PACKED_ORDER_YUY2       (0x0 << 14)
69#define OVERLAY_PACKED_ORDER_YVYU       (0x1 << 14)
70#define OVERLAY_PACKED_ORDER_UYVY       (0x2 << 14)
71#define OVERLAY_PACKED_ORDER_VYUY       (0x3 << 14)
72#define OVERLAY_PACKED_ORDER_MASK       (0x3 << 14)
73
74#define OVERLAY_MEMORY_LAYOUT_TILED     (0x1 << 19)
75#define OVERLAY_MEMORY_LAYOUT_LINEAR    (0x0 << 19)
76
77#define OVERLAY_MIRRORING_NORMAL        (0x0 << 17)
78#define OVERLAY_MIRRORING_HORIZONTAL    (0x1 << 17)
79#define OVERLAY_MIRRORING_VERTIACAL     (0x2 << 17)
80#define OVERLAY_MIRRORING_BOTH          (0x3 << 17)
81
82#define OVERLAY_CONFIG_BYPASS_DISABLE   (0x1 << 4)
83
84#define BUF_TYPE                (0x1<<5)
85#define BUF_TYPE_FRAME          (0x0<<5)
86#define BUF_TYPE_FIELD          (0x1<<5)
87#define TEST_MODE               (0x1<<4)
88#define BUFFER_SELECT           (0x3<<2)
89#define BUFFER0                 (0x0<<2)
90#define BUFFER1                 (0x1<<2)
91#define FIELD_SELECT            (0x1<<1)
92#define FIELD0                  (0x0<<1)
93#define FIELD1                  (0x1<<1)
94#define OVERLAY_ENABLE          0x1
95
96
97// Overlay contorl registers
98typedef struct {
99    uint32_t OBUF_0Y;
100    uint32_t OBUF_1Y;
101    uint32_t OBUF_0U;
102    uint32_t OBUF_0V;
103    uint32_t OBUF_1U;
104    uint32_t OBUF_1V;
105    uint32_t OSTRIDE;
106    uint32_t YRGB_VPH;
107    uint32_t UV_VPH;
108    uint32_t HORZ_PH;
109    uint32_t INIT_PHS;
110    uint32_t DWINPOS;
111    uint32_t DWINSZ;
112    uint32_t SWIDTH;
113    uint32_t SWIDTHSW;
114    uint32_t SHEIGHT;
115    uint32_t YRGBSCALE;
116    uint32_t UVSCALE;
117    uint32_t OCLRC0;
118    uint32_t OCLRC1;
119    uint32_t DCLRKV;
120    uint32_t DCLRKM;
121    uint32_t SCHRKVH;
122    uint32_t SCHRKVL;
123    uint32_t SCHRKEN;
124    uint32_t OCONFIG;
125    uint32_t OCMD;
126    uint32_t RESERVED1;
127    uint32_t OSTART_0Y;
128    uint32_t OSTART_1Y;
129    uint32_t OSTART_0U;
130    uint32_t OSTART_0V;
131    uint32_t OSTART_1U;
132    uint32_t OSTART_1V;
133    uint32_t OTILEOFF_0Y;
134    uint32_t OTILEOFF_1Y;
135    uint32_t OTILEOFF_0U;
136    uint32_t OTILEOFF_0V;
137    uint32_t OTILEOFF_1U;
138    uint32_t OTILEOFF_1V;
139    uint32_t FASTHSCALE;
140    uint32_t UVSCALEV;
141
142    uint32_t RESERVEDC[(0x200 - 0xA8) / 4];
143    uint16_t Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES];
144    uint16_t RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
145    uint16_t Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES];
146    uint16_t RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
147    uint16_t UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES];
148    uint16_t RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
149    uint16_t UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES];
150    uint16_t RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
151} OverlayBackBufferBlk;
152
153typedef struct {
154    uint8_t sign;
155    uint16_t mantissa;
156    uint8_t exponent;
157} coeffRec, *coeffPtr;
158
159
160} // namespace intel
161} // nam
162
163
164#endif
165