| b089eccf503646e6ed2d5bb20d973d9131166655 |
01-Jun-2016 |
Vladimir Marko <vmarko@google.com> |
Delay dex-to-dex compilation until Optimizing is done.
This fixes a race between inlining in the Optimizing
backend and dex-to-dex quickening where the Optimizing can
read the non-quickened opcode and then the quickened field
index or vtable index and look up the wrong field or method.
Even if we such tearing of the dex instruction does not
happen, the possible reordering of dex-to-dex and Optimizing
compilation makes the final oat file non-deterministic.
Also, remove VerificationResults::RemoveVerifiedMethod() as
we have only the Optimizing backend now and as such it was
dead code and would have interfered with this change.
Bug: 29043547
Bug: 29089975
(cherry picked from commit 492a7fa6df3b197a24099a50f5abf624164f3842)
Change-Id: I1337b772dc69318393845a790e5f6d38aa3de60f
erification_results.cc
erification_results.h
|
| 8c185bf0c6f18a5349bc87a7e3751ba06d90f461 |
23-May-2016 |
Vladimir Marko <vmarko@google.com> |
Compile JNI stubs for verify-profile and interpret-only.
This is the intended behavior to have a good JNI transition
performance.
Bug: 28902384
Change-Id: Iedb2ca343d66cf422ef2dc0527639e81d6ba8960
erification_results.cc
|
| e5de54cfab5f14ba0b8ff25d8d60901c7021943f |
20-Apr-2016 |
Calin Juravle <calin@google.com> |
Split profile recording from jit compilation
We still use ProfileInfo objects to record profile information. That
gives us the flexibility to add the inline caches in the future and the
convenience of the already implemented GC.
If UseJIT is false and SaveProfilingInfo true, we will only record the
ProfileInfo and never launch compilation tasks.
Bug: 27916886
Change-Id: I6e4768dc5d58f2f85f947b276b4244aa11ce3fca
erification_results.cc
erified_method.cc
|
| 9d07e3d128ccfa0ef7670feadd424a825e447d1d |
31-Mar-2016 |
Vladimir Marko <vmarko@google.com> |
Clean up OatQuickMethodHeader after Quick removal.
This reduces the size of the pre-header by 8 bytes, reducing
oat file size and mmapped .text section size. The memory
needed to store a CompiledMethod by dex2oat is also reduced,
for 32-bit dex2oat by 8B and for 64-bit dex2oat by 16B. The
aosp_flounder-userdebug 32-bit and 64-bit boot.oat are each
about 1.1MiB smaller.
Disable the broken StubTest.IMT, b/27991555 .
Change-Id: I05fe45c28c8ffb7a0fa8b1117b969786748b1039
ex_to_dex_compiler.cc
|
| bf9611f821697b14bf9e170f503c3f47613b046b |
26-Mar-2016 |
Andreas Gampe <agampe@google.com> |
ART: Clean up verifier
Clean up verifier post-Quick.
Change-Id: I0b05e10dd06edd228fe2068c8afffc4b7d7fdffa
erification_results.cc
erified_method.cc
erified_method.h
|
| 2e384346d93a747e19fb74f32eba2d1e9403721f |
24-Mar-2016 |
Vladimir Marko <vmarko@google.com> |
Merge "Post-Quick cleanup: Remove CompilationUnit."
|
| df739841b781dbd49c247e3795696389c4799020 |
23-Mar-2016 |
Vladimir Marko <vmarko@google.com> |
Post-Quick cleanup: Remove CompilationUnit.
Change-Id: I309411b0fffaaed1e218e2c34394bdf6e2f75b48
ex_to_dex_compiler.cc
|
| 29d38e77c553c6cf71fc4dafe2d22b4e3f814872 |
23-Mar-2016 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "Use compiler filter to determine oat file status.""
This reverts commit 845e5064580bd37ad5014f7aa0d078be7265464d.
Add an option to change what OatFileManager considers up-to-date.
In our tests we're allowed to write to the dalvik-cache, so it
cannot be kSpeed.
Bug: 27689078
Change-Id: I0c578705a9921114ed1fb00d360cc7448addc93a
erification_results.cc
|
| 845e5064580bd37ad5014f7aa0d078be7265464d |
23-Mar-2016 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Use compiler filter to determine oat file status."
Bots are red. Tentative reverting as this is likely the offender.
Bug: 27689078
This reverts commit a62d2f04a6ecf804f8a78e722a6ca8ccb2dfa931.
Change-Id: I3ec6947a5a4be878ff81f26f17dc36a209734e2a
erification_results.cc
|
| a62d2f04a6ecf804f8a78e722a6ca8ccb2dfa931 |
18-Mar-2016 |
Richard Uhler <ruhler@google.com> |
Use compiler filter to determine oat file status.
Record the compiler filter in the oat header. Use that to determine
when the oat file is up-to-date with respect to a target compiler
filter level.
New xxx-profile filter levels are added to specify if a profile should
be used instead of testing for the presence of a profile file.
This change should allow for different compiler-filters to be set for
different package manager use cases.
Bug: 27689078
Change-Id: Id6706d0ed91b45f307142692ea4316aa9713b023
erification_results.cc
|
| 3c94f0945ed596ceee39783fa075f013b65e80a1 |
21-Mar-2016 |
Nicolas Geoffray <ngeoffray@google.com> |
Remove Quick from tree.
So long, old friend.
Change-Id: I0241c798a34b92bf994fed83888da67d6e7f1891
b_optimizations.cc
b_optimizations.h
ompiler_ir.cc
ompiler_ir.h
ataflow_iterator-inl.h
ataflow_iterator.h
ex_flags.h
ex_types.h
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
vn_dead_code_elimination.cc
vn_dead_code_elimination.h
vn_dead_code_elimination_test.cc
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_analysis.cc
ir_dataflow.cc
ir_field_info.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_method_info.cc
ir_method_info.h
ir_optimization.cc
ir_optimization_test.cc
ass.h
ass_driver.h
ass_driver_me.h
ass_driver_me_opts.cc
ass_driver_me_opts.h
ass_driver_me_post_opt.cc
ass_driver_me_post_opt.h
ass_manager.cc
ass_manager.h
ass_me.h
ost_opt_passes.cc
ost_opt_passes.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/backend_arm.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/backend_arm64.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/lazy_debug_frame_opcode_writer.cc
uick/lazy_debug_frame_opcode_writer.h
uick/local_optimizations.cc
uick/mips/README.mips
uick/mips/assemble_mips.cc
uick/mips/backend_mips.h
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/quick_cfi_test.cc
uick/quick_cfi_test_expected.inc
uick/quick_compiler.cc
uick/quick_compiler.h
uick/quick_compiler_factory.h
uick/ralloc_util.cc
uick/resource_mask.cc
uick/resource_mask.h
uick/x86/assemble_x86.cc
uick/x86/backend_x86.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/quick_assemble_x86_test.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_location.h
eg_storage.h
eg_storage_eq.h
sa_transformation.cc
ype_inference.cc
ype_inference.h
ype_inference_test.cc
reg_analysis.cc
|
| f6a35de9eeefb20f6446f1b4815b4dcb0161d09c |
21-Mar-2016 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Fix register allocator validation memory usage.
Also attribute ArenaBitVector allocations to appropriate
passes. This was used to track down the source of the
excessive memory alloactions.
Bug: 27690481
Change-Id: Ib895984cb7c04e24cbc7abbd8322079bab8ab100
lobal_value_numbering_test.cc
vn_dead_code_elimination_test.cc
ir_dataflow.cc
ir_graph.cc
ir_optimization.cc
sa_transformation.cc
ype_inference_test.cc
|
| f969a209c30e3af636342d2fb7851d82a2529bf7 |
09-Mar-2016 |
Roland Levillain <rpl@google.com> |
Fix and enable java.lang.StringFactory intrinsics.
The following intrinsics were not considered by the
intrinsics recognizer:
- StringNewStringFromBytes
- StringNewStringFromChars
- StringNewStringFromString
This CL enables them and add tests for them.
This CL also:
- Fixes the locations of the ARM64 & MIPS64
StringNewStringFromString intrinsics.
- Fixes the definitions of the FOUR_ARG_DOWNCALL macros on
ARM and x86, which are used to implement the
art_quick_alloc_string_from_bytes* runtime entry points.
- Fixes PC info (stack maps) recording in the
StringNewStringFromBytes, StringNewStringFromChars and
StringNewStringFromString ARM, ARM64 & MIPS64 intrinsics.
Bug: 27425743
Change-Id: I38c00d3f0b2e6b64f7d3fe9146743493bef9e45c
uick/dex_file_method_inliner.cc
|
| 0e54c0160c84894696c05af6cad9eae3690f9496 |
04-Mar-2016 |
Aart Bik <ajcbik@google.com> |
Unsafe: Recognize intrinsics for 1.8 java.util.concurrent
With unit test.
Rationale:
Recognizing the 1.8 methods as intrinsics is the first step
towards providing efficient implementation on all architectures.
Where not implemented (everywhere for now), the methods fall back
to the JNI native or reference implementation.
NOTE: needs iam's CL first!
bug=26264765
Change-Id: Ife65e81689821a16cbcdd2bb2d35641c6de6aeb6
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 4cb069fa2fd967312d5884b86bbdac343df9eb28 |
01-Mar-2016 |
Roland Levillain <rpl@google.com> |
Merge "Fix the signature of the IndexOf entry point."
|
| 42ad288254e660ad091d03fad8c8fbad1d34ec89 |
29-Feb-2016 |
Roland Levillain <rpl@google.com> |
Fix the signature of the IndexOf entry point.
The IndexOf entry point was declared as taking four
arguments (void*, uint32_t, uint32_t, uint32_t) whereas all
actual implementations use three arguments (void*, uint32_t,
uint32_t). As that fourth argument is not documented, drop
it from the intrinsic declaration to have it match the
implementations.
Change-Id: I65d747033192025ccd2b9a5e8f8ed05b77a21941
uick/gen_invoke.cc
|
| cc3839c15555a2751e13980638fc40e4d3da633e |
29-Feb-2016 |
Roland Levillain <rpl@google.com> |
Improve documentation about StringFactory.newStringFromChars.
Make it clear that the native method requires its third
argument to be non-null, and therefore that the intrinsics
do not need a null check for it.
Bug: 27378573
Change-Id: Id2f78ceb0f7674f1066bc3f216b738358ca25542
uick/gen_invoke.cc
|
| 1bdfdb3e879267dafb4b6811dd70cc8b7511fe15 |
26-Feb-2016 |
Aart Bik <ajcbik@google.com> |
Merge "Implement fp to bits methods as intrinsics."
|
| 2a6aad9d388bd29bff04aeec3eb9429d436d1873 |
25-Feb-2016 |
Aart Bik <ajcbik@google.com> |
Implement fp to bits methods as intrinsics.
Rationale:
Better optimization, better performance.
Results on libcore benchmark:
Most gain is from moving the invariant call out of the loop
after we detect everything is a side-effect free intrinsic.
But generated code in general case is much cleaner too.
Before:
timeFloatToIntBits() in 181 ms.
timeFloatToRawIntBits() in 35 ms.
timeDoubleToLongBits() in 208 ms.
timeDoubleToRawLongBits() in 35 ms.
After:
timeFloatToIntBits() in 36 ms.
timeFloatToRawIntBits() in 35 ms.
timeDoubleToLongBits() in 35 ms.
timeDoubleToRawLongBits() in 34 ms.
bug=11548336
Change-Id: I6e001bd3708e800bd75a82b8950fb3a0fc01766e
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| a1de9188a05afdecca8cd04ecc4fefbac8b9880f |
25-Feb-2016 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Reduce memory usage of HInstructions.
Pack narrow fields and flags into a single 32-bit field.
Change-Id: Ib2f7abf987caee0339018d21f0d498f8db63542d
ompiler_enums.h
|
| 944da603cde59a4277f3bbc31d860a90842a1a2a |
19-Feb-2016 |
Vladimir Marko <vmarko@google.com> |
ART: Allow method references across oat files for multi-image, 2nd attempt.
These were disabled because we didn't have sufficient
information about the multi-image layout when processing
link-time patches in OatWriter. This CL refactors the
ELF file creation so that the information is available.
Also clean up ImageWriter to use oat file indexes instead
of filenames and avoid reopening the oat file to retrieve
the checksum.
Change-Id: Icc7b528deca29da1e473c8f079521a36d6c4892f
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| 98e6ce44c700abd9375fe17f0aa31fea1e1e938b |
16-Feb-2016 |
Nicolas Geoffray <ngeoffray@google.com> |
Remove string init map.
Partial revert of the String init change.
- Make Quick bailout in the presence of String allocation.
- Rely on the compiler for knowing when dex registers alias.
bug:27173201
Change-Id: I0bf58ba3825c71cef110b53f3a0a6f567cb2ef9a
ir_optimization.cc
uick/quick_compiler.cc
uick/quick_compiler.h
erified_method.cc
erified_method.h
|
| 45724f9a0cc38dbb3071beb3eeab96499868b49c |
17-Feb-2016 |
Vladimir Marko <vmarko@google.com> |
Revert "Allow method references across oat files for multi-image."
Breaks Quick tests.
This reverts commit 6065402316da2b51eed5fc34cffbd991766bd408.
Change-Id: I8a5469ba7cea5f46b85cb489b3e0ef06ed548f03
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| 6065402316da2b51eed5fc34cffbd991766bd408 |
16-Feb-2016 |
Vladimir Marko <vmarko@google.com> |
Allow method references across oat files for multi-image.
These were disabled because we didn't have sufficient
information about the multi-image layout when processing
link-time patches in OatWriter. This CL refactors the
ELF file creation so that the information is available.
Change-Id: I6f2e8dc8572d143c72cc2693bb0ba4fd76f889ab
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| 927f40d925e2106598d413ac02e8d80463357258 |
10-Feb-2016 |
Vladimir Marko <vmarko@google.com> |
Merge "Try to substitute constructor chains for IPUTs."
|
| 354efa6cdf558b2331e8fec539893fa51763806e |
04-Feb-2016 |
Vladimir Marko <vmarko@google.com> |
Try to substitute constructor chains for IPUTs.
Match a constructor chain where each constructor either
forwards some or all of its arguments to the next (i.e.
superclass constructor or a constructor in the same class)
and may pass extra zeros (of any type, including null),
followed by any number of IPUTs on "this", storing either
arguments or zeros, until we reach the contructor of
java.lang.Object.
When collecting IPUTs from the constructor chain, remove
any IPUTs that store the same field as an IPUT that comes
later. This is safe in this case even if those IPUTs store
volatile fields because the uninitialized object reference
wasn't allowed to escape yet. Also remove any IPUTs that
store zero values as the allocated object is already zero
initialized.
Change-Id: If93022310bf04fe38ee741665ac4a65d4c2bb25f
uick/dex_file_method_inliner.cc
|
| 4fda4eb799c95be266f52aaf3461a440ea86b841 |
05-Feb-2016 |
David Srbecky <dsrbecky@google.com> |
Move code related to debug info generation to its own directory.
debug/dwarf/ contains helper classes which hide the details
of the DWARF file format. It acts as independent DWARF library.
debug/ contains ART-specific code which generates ELF debug
sections (which includes non-DWARF sections like .symtab).
Change-Id: Id351f604e4e64be2ca395a78324ea02e30481497
uick/lazy_debug_frame_opcode_writer.h
|
| d967266cdfc8011c81ba6e9857a247c4a73bd0fc |
03-Sep-2015 |
Lazar Trsic <Lazar.Trsic@imgtec.com> |
MIPS64: Remove unaligned memory access from art generated code
Unaligned memory access was caused by sd, ld, ldc1 and sdc1
instructions. Check if offset is unaligned and replace it
with two 32 bit memory accesses, if so.
Added assembler tests for new instructions, as well as assembler
tests for LoadFromOffset, LoadFpuFromOffset, StoreToOffset and
StoreFpuToOffset.
Change-Id: I0228a4a2ce6c801eeb5b46952b8330e14468deb3
uick/mips/utility_mips.cc
|
| 78e90155b249588cb800e7f6e5993ebcbd465292 |
28-Jan-2016 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Add option to ensure deterministic compilation"
|
| ace0dc1dd5480ad458e622085e51583653853fb9 |
20-Jan-2016 |
Andreas Gampe <agampe@google.com> |
ART: Add option to ensure deterministic compilation
To ensure reliable stable generation of a boot image, add a flag
for forced determinism, trading compile time for a deterministic
output.
We have to run certain passes in the compiler-driver single-threaded.
It is also necessary to try to make the heap layout deterministic.
Switch to nonconcurrent GC, use the free-list implementation for LOS,
and try to allocate the main space at a known location. This is best
effort at the moment.
To allow the compiler phase to be parallelized, const-strings need
to be created beforehand.
The identity hashcode seed needs to be pinned.
Besides the Dex object we also need to null the DexFile pointer in
dex caches.
For classes, we need to remove the clinit thread ID.
Fix oatdump alignment padding accounting.
Bug: 26687569
Change-Id: Ia82120e8f715bb3691d861817b12778ac677355a
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| 30202b2665adbb3c7b88b06adfe96d2f0e159099 |
27-Jan-2016 |
David Srbecky <dsrbecky@google.com> |
Merge "Revert "Revert "Add option to generate compressed backtrace info."""
|
| b1bd048f569aea0c2e76abd999750add2da6280c |
26-Jan-2016 |
Aart Bik <ajcbik@google.com> |
Merge "Recognize common utilities as intrinsics."
|
| 9724c636467d56632a45fdf6353e3d57d1925501 |
07-Jan-2016 |
Neil Fuller <nfuller@google.com> |
Enable interface default methods by default.
This also enables interface static methods.
This removes the -Xexperimental:default-methods flag and all places
where we explicitly check for its presence.
Bug: 24618811
Change-Id: Icd91e377bd6e1a45a1645f810d15de1b0312e31d
uick/quick_compiler.cc
|
| 59c9454b92c2096a30a2bbdffb64edf33dbdd916 |
25-Jan-2016 |
Aart Bik <ajcbik@google.com> |
Recognize common utilities as intrinsics.
Rationale:
Recognizing these method calls as intrinsics already has
major advantages (compiler knows about no-side-effects/no-throw
properties). Next step is, of course, to implement these
with native instructions on each architecture.
Change-Id: I06fd12973238caec00d67b31b195d7f8807a538e
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 5b1c2ca30dad519be285f0a1e839c23cc4e3a51d |
25-Jan-2016 |
David Srbecky <dsrbecky@google.com> |
Revert "Revert "Add option to generate compressed backtrace info.""
This reverts commit 8546cc9aeb05e866e1fb6a9e4130d53ea330baa8.
Change-Id: I676fdf9af27fa3b16fa8921778ff8832ab8c437d
uick/codegen_util.cc
|
| 8546cc9aeb05e866e1fb6a9e4130d53ea330baa8 |
25-Jan-2016 |
David Srbecky <dsrbecky@google.com> |
Revert "Add option to generate compressed backtrace info."
This reverts commit 5fdcc3c931b70204fd8c491afa66f57f8428490f.
Change-Id: I9c1f5aad6933a46af6717e3a90a51f76111f9c8a
uick/codegen_util.cc
|
| 5fdcc3c931b70204fd8c491afa66f57f8428490f |
19-Jan-2016 |
David Srbecky <dsrbecky@google.com> |
Add option to generate compressed backtrace info.
Add flag --generate-mini-debug-info which generates
LZMA compressed .symtab and .debug_frame, which are
sufficient to print java backtraces in libunwind.
If enabled, it increases the size of boot.oat by about 3.5%.
Change-Id: Ic3c2ef7704c05fa328720c6781ca2a9b8e3935a3
uick/codegen_util.cc
|
| 3f67e692860d281858485d48a4f1f81b907f1444 |
15-Jan-2016 |
Aart Bik <ajcbik@google.com> |
Implemented BitCount as an intrinsic. With unit test.
Rationale:
Recognizing this important operation as an intrinsic has
various advantages:
(1) having the no-side-effects/no-throw allows for
much more GVN/LICM/BCE.
(2) Some architectures, like x86_64, provide direct
support for this operation.
Performance improvements on X86_64:
CheckersEvalBench (32-bit bitboard): 27,210KNS -> 36,798KNS = + 35%
ReversiEvalBench (64-bit bitboard): 52,562KNS -> 89,086KNS = + 69%
Change-Id: I65d549b0469b7909b12c6611cdc34a8640a5751f
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 0021c310e2e613d6d180acda0d9d422dba8688b0 |
21-Jan-2016 |
Aart Bik <ajcbik@google.com> |
Merge "JIT: Fix incorrect CHECK"
|
| 91d65e024846717fce3572106cffe9b957b8902c |
19-Jan-2016 |
Roland Levillain <rpl@google.com> |
Fix various typos in ART's comments and string literals.
Change-Id: I85d628055b1a61647a77fef730c9631c234e22a2
uick/dex_file_method_inliner.cc
|
| c903b6af634927479915eaa9516d493eea23f911 |
18-Jan-2016 |
Nicolas Geoffray <ngeoffray@google.com> |
Move --dump-cfg and dump-cfg-append to CompilerOptions.
It simplifies passing the option to the JIT.
Change-Id: Iee1b722362899e5809ef97be90961e3dda1e16cc
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| 51e55914d5b3045718e871401f096d059a2f7d31 |
10-Nov-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
JIT: Fix incorrect CHECK
MirMethodLoweringInfo::Resolve() contains a CHECK that fails if the
invoke being resolved is String.<init>(). This changes the invoke_type
to kDirect, and then CHECKs that it is kVirtual, which doesn't work
well.
Change-Id: I2c3afa38533fb39f0b1260968c46b251088e75c8
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
ir_method_info.cc
|
| 7b4199a5fa9f151fbf3af2a34f26d04215a1016c |
14-Jan-2016 |
Alex Light <allight@google.com> |
Merge "Support directly invoking interface default methods"
|
| 705ad49f353d3f90d8b63625aca2c2035bacdbef |
21-Sep-2015 |
Alex Light <allight@google.com> |
Support directly invoking interface default methods
With the Java 8 Language one is allowed to directly call default
interface methods of interfaces one (directly) implements through the
use of the super keyword. We support this behavior through the
invoke-super opcode with the target being an interface.
We add 3 tests for this behavior.
Currently only supports slow-path interpreter.
Invoke-super is currently extremely slow.
Bug: 24618811
Change-Id: I7e06e17326f7dbae0116bd7dfefca151f0092bd2
uick/quick_compiler.cc
uick/quick_compiler.h
|
| 998c21661b5074c293cae818d0ab7c44dcda3a66 |
21-Dec-2015 |
Calin Juravle <calin@google.com> |
Perform profile file analysis in dex2oat
Dex2oat can accept now multiple profile files to drive a profile based
compilation. --profile-file and --reference-profile-file speficy a pair
of profile files which will be evaluated for significant differences
before starting the compilation. If the difference is insignificant
(according to some internal metric) the compilation is skipped and a
message is logged.
Multiple pairs of --profile-file and --reference-profile-file can be
specified. This effectively enables multi user support since profiles
for different users will be kept separately.
--reference-profile-file can be left out, case in which the decision is
solely based on --profile-file. If both flags are present, then their
repetition should form unique pairs.
If the compilation is performed and --reference-profile-file is given
then its data is merged with the data from the corresponding --profile-
file and saved back to the file.
If no profile flags are given, dex2oat proceeds as before and compiles
the dex files unconditionally.
As part of this change
- merge ProfileCompilationInfo and OfflineProfilingInfo under the same
object. There was no use to keep them separate anymore.
- SaveProfilingInfo now merges the data with what was in
the file before instead of overwriting it.
Bug: 26080105
Change-Id: Ia8c8b55587d468bca5179f78941854285426234d
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| e6d0d8de85f79c8702ee722a04cd89ee7e89aeb7 |
28-Dec-2015 |
Andreas Gampe <agampe@google.com> |
ART: Disable Math.round intrinsics
The move to OpenJDK means that Android has caught up with the
definition change of Math.round. Disable intrinsics.
Bug: 26327751
Change-Id: I00dc6cfca12bd7c95e56a4ab76ffee707d3822dc
uick/arm64/fp_arm64.cc
|
| 095b1df3d20e806ed7ad8c545b03866c1561d1f6 |
28-Dec-2015 |
Andreas Gampe <agampe@google.com> |
Revert "Make Math.round consistent on arm64."
This reverts commit 40041c9a38e3961d8675d117517719458a115520.
Needs to be generalized to all platforms.
Bug: 26327751
Change-Id: Iae8f1c8846d120d8e3e99b6eb87f3760bf793ec5
uick/arm64/fp_arm64.cc
|
| 40041c9a38e3961d8675d117517719458a115520 |
27-Dec-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Make Math.round consistent on arm64.
OpenJDK seems to have a different rounding implementation than
libcore. Temporarily disable the intrinsic.
Test that fails:
Assert.assertEquals(StrictMath.round(0.49999999999999994d), 1l);
Assert.assertEquals(Math.round(0.49999999999999994d), 1l);
bug:26327751
Change-Id: Iad2fb847e4a553b8c1f5031f772c81e7e4db9f4c
uick/arm64/fp_arm64.cc
|
| dcdc85bbd569f0ee66c331b4219c19304a616214 |
04-Dec-2015 |
Jeff Hao <jeffhao@google.com> |
Dex2oat support for multiple oat file and image file outputs.
Multiple changes to dex2oat and the runtime to support a --multi-image
option. This generates a separate oat file and image file output for
each dex file input.
Change-Id: Ie1d6f0b8afa8aed5790065b8c2eb177990c60129
uick/dex_file_method_inliner.cc
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| 9865bde5d822f56c4732214c2005dfcaa41f94cf |
21-Dec-2015 |
Mathieu Chartier <mathieuc@google.com> |
Rename NullHandle to ScopedNullHandle
This makes it clearer that is invalid to do things like:
Handle<T> h = ScopedNullHandle<T>();
Bug: 26233305
Change-Id: I6d8f54eae01ec2e901cb7043afa853ea77db79fe
ype_inference_test.cc
|
| 17077d888a6752a2e5f8161eee1b2c3285783d12 |
16-Dec-2015 |
Mark P Mendell <mark.p.mendell@intel.com> |
Revert "Revert "X86: Use locked add rather than mfence""
This reverts commit 0da3b9117706760e8722029f407da6d0297cc943.
Fix a compilation failure that slipped in somehow.
Change-Id: Ide8681cdc921febb296ea47aa282cc195f154049
uick/x86/assemble_x86.cc
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 0da3b9117706760e8722029f407da6d0297cc943 |
16-Dec-2015 |
Aart Bik <ajcbik@google.com> |
Revert "X86: Use locked add rather than mfence"
This reverts commit 7b3e4f99b25c31048a33a08688557b133ad345ab.
Reason: build error on sdk (linux) in git_mirror-aosp-master-with-vendor , please fix first
art/compiler/optimizing/code_generator_x86_64.cc:4032:7: error: use of
undeclared identifier 'codegen_'
codegen_->MemoryFence();
Change-Id: I91f8542cfd944b7425d1981c35872dcdcb901e18
uick/x86/assemble_x86.cc
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 7b3e4f99b25c31048a33a08688557b133ad345ab |
19-Nov-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
X86: Use locked add rather than mfence
Java semantics for memory ordering can be satisfied using
lock addl $0,0(SP)
rather than mfence. The locked add synchronizes the memory caches, but
doesn't affect device memory.
Timing on a micro benchmark with a mfence or lock add $0,0(sp) in a loop
with 600000000 iterations:
time ./mfence
real 0m5.411s
user 0m5.408s
sys 0m0.000s
time ./locked_add
real 0m3.552s
user 0m3.550s
sys 0m0.000s
Implement this as an instruction-set-feature lock_add. This is off by
default (uses mfence), and enabled for atom & silvermont variants.
Generation of mfence can be forced by a parameter to MemoryFence.
Change-Id: I5cb4fded61f4cbbd7b7db42a1b6902e43e458911
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 226501b317e148aa8a8983355e85acb59c1eee83 |
11-Dec-2015 |
Calin Juravle <calin@google.com> |
Revert "Revert "Enable profiled guided compilation in dex2oat""
This reverts commit 2306ae0d412cc53cbf64877e4a8c37292dd907d8.
Change-Id: I50640009c2fac88ea703812b76549a0e8a6d7584
ir_analysis.cc
ir_graph.h
uick/quick_compiler.cc
|
| 66278646b5b332142d1474703ac7d945dfbf7c78 |
11-Dec-2015 |
Calin Juravle <calin@google.com> |
Merge "Revert "Enable profiled guided compilation in dex2oat""
|
| 2306ae0d412cc53cbf64877e4a8c37292dd907d8 |
11-Dec-2015 |
Calin Juravle <calin@google.com> |
Revert "Enable profiled guided compilation in dex2oat"
The test still have some flakiness in it which didn't reproduce locally.
This reverts commit 500c9be1f261a8a95ae7a25f4f8084f43207f313.
Change-Id: I132aff62bf03c2f926aafde6869707573bae9b36
ir_analysis.cc
ir_graph.h
uick/quick_compiler.cc
|
| a79c717fd4de0d7361a51bee1e3cf4f2ff5f085a |
11-Dec-2015 |
Calin Juravle <calin@google.com> |
Merge "Enable profiled guided compilation in dex2oat"
|
| 376cbcc5163b3bb80811b9af6b67b6f8719db9f2 |
11-Dec-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Optimizing: Add direct calls to math intrinsics"
|
| a4f1220c1518074db18ca1044e9201492975750b |
06-Aug-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
Optimizing: Add direct calls to math intrinsics
Support the double forms of:
cos, sin, acos, asin, atan, atan2, cbrt, cosh, exp, expm1,
hypot, log, log10, nextAfter, sinh, tan, tanh
Add these entries to the vector addressed off the thread pointer. Call
the libc routines directly, which means that we have to implement the
native ABI, not the ART one. For x86_64, that includes saving XMM12-15
as the native ABI considers them caller-save, while the ART ABI
considers them callee-save. We save them by marking them as used by the
call to the math function. For x86, this is not an issue, as all the XMM
registers are caller-save.
Other architectures will call Java as before until they are ready to
implement the new intrinsics.
Bump the OAT version since we are incompatible with old boot.oat files.
Change-Id: Ic6332c3555c09393a17d1ad4daf62932488722fb
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 500c9be1f261a8a95ae7a25f4f8084f43207f313 |
25-Nov-2015 |
Calin Juravle <calin@google.com> |
Enable profiled guided compilation in dex2oat
- add parsing of the profile info saved during JIT.
- don't compile methods which are not part of the profile info.
- delete old profile hooks.
- add test for reading/writing profile. The test is disable in:
* interpreter modes: the test needs JIT.
* no-dex2oat/no-prebuild: we only save profiling info for the primary
oat file. In these modes we don't create oat files and thus nothing
is saved.
Bug:26080105
Change-Id: Ifdc63dc9d4b537fc79e54c3edc3ae3a462bc30fb
ir_analysis.cc
ir_graph.h
uick/quick_compiler.cc
|
| 53e32d14d7a51198c6ef09120c15bafdd1d055c2 |
10-Dec-2015 |
Andreas Gampe <agampe@google.com> |
ART: Refactor verifier callbacks
Change the return type of MethodVerified to void. It was never
used anyways.
Remove the callbacks calls from the core of the verifier (Verify()).
Instead, make the convenience functions do the work, and add a
parameter to supply the callback so that the verifier becomes
independent of the Runtime-stored one.
Fix up calls that now need to provide a callback, but leave places
that only run the verifier to get metadata (e.g., register type data,
lock state) without callback. This avoids callback calls when in JIT
mode.
Bug: 26075442
Change-Id: I2c270f01e4de088771d4d4b19dae4f07d77640f0
uick_compiler_callbacks.cc
uick_compiler_callbacks.h
erification_results.cc
erification_results.h
|
| 9fdb129b90c9a985f606f9d95627b4852171dc11 |
02-Dec-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Enable profiled guided compilation in dex2oat"
Test has flakes:
+art F 30865 30865 art/runtime/java_vm_ext.cc:466] JNI DETECTED ERROR IN APPLICATION: input is not valid Modified UTF-8: illegal start byte 0x80
+art F 30865 30865 art/runtime/java_vm_ext.cc:466] string: '��gy�'
+art F 30865 30865 art/runtime/java_vm_ext.cc:466] input: '<0x80> 0xd8 0x67 0x79 0x8e 0x7f'
+art F 30865 30865 art/runtime/java_vm_ext.cc:466] in call to NewStringUTF
+art F 30865 30865 art/runtime/java_vm_ext.cc:466] from java.lang.String Main.getProfileInfoDump(java.lang.String, java.lang.Class, java.lang.Class)
This reverts commit 27e17fd81cc30e16e86c9c15498cae7f920c9dfe.
Change-Id: Id224b5970c3620c4c71fc0d39ed4a2e4755e5f29
ir_analysis.cc
ir_graph.h
uick/quick_compiler.cc
|
| 27e17fd81cc30e16e86c9c15498cae7f920c9dfe |
25-Nov-2015 |
Calin Juravle <calin@google.com> |
Enable profiled guided compilation in dex2oat
- add parsing of the profile info saved during JIT
- don't compile methods which are not part of the profile info.
- delete old profile hooks
Change-Id: I45a13c3aeb36265d335e57cd160b9ea0fab3cbb5
ir_analysis.cc
ir_graph.h
uick/quick_compiler.cc
|
| fb8464ae5f5194dc16278e528cfcbff71498c767 |
02-Nov-2015 |
Mingyao Yang <mingyao@google.com> |
Revert "Revert "Enable store elimination for singleton objects.""
This reverts commit 55d02cf056f993aeafebd54e7b7c68c7a48507c9, and
makes the following change:
Currently we leverage loop side effects to decide whether heap values are
killed by the loop. Stores need to be kept if heap values may be killed
by loops and the corresponding loads cannot be eliminated. Similar thing
need to be done for each predecessor when we merge predecessor heap values.
To do that, the HInstanceFieldSet instruction itself is put in the heap
value array instead of the value of the store instruction. The store
instruction may be added to possibly_removed_stores_ first, but can later
be removed from possibly_removed_stores_ when it's found out that the store
needs to be kept due to merging/loop side effects.
Change-Id: I4f7bb1960f7b47240873e00ff1adac46fc102a02
uick/gen_common.cc
|
| 0d5a281c671444bfa75d63caf1427a8c0e6e1177 |
13-Nov-2015 |
Roland Levillain <rpl@google.com> |
x86/x86-64 read barrier support for concurrent GC in Optimizing.
This first implementation uses slow paths to instrument heap
reference loads and GC root loads for the concurrent copying
collector, respectively calling the artReadBarrierSlow and
artReadBarrierForRootSlow (new) runtime entry points.
Notes:
- This implementation does not instrument HInvokeVirtual
nor HInvokeInterface instructions (for class reference
loads), as the corresponding read barriers are not stricly
required with the current concurrent copying collector.
- Intrinsics which may eventually call (on slow path) are
disabled when read barriers are enabled, as the current
slow path infrastructure does not support this case.
- When read barriers are enabled, the code generated for a
HArraySet instruction always go into the array set slow
path for object arrays (delegating the operation to the
runtime), as we are lacking a mechanism to keep a
temporary register live accross a runtime call (needed for
the instrumentation of type checking code, which requires
two successive read barriers).
Bug: 12687968
Change-Id: I14cd6107233c326389120336f93955b28ffbb329
uick/quick_compiler.cc
|
| 9139e008abe30b7beaf4afd6533228a1dd9b202c |
10-Oct-2015 |
Alex Light <allight@google.com> |
Correct exception behavior for default methods
Default methods are defined to throw an IncompatibleClassChangeError
(ICCE) when they are called and there is no "best" implementation.
Previously we would simply throw an ICCE during class loading as soon
as we noticed that this would happen if called. This makes us wait
until we actually attempt to execute the method. Furthermore, this
allows us to use other, non-conflicting, methods on the object as
normal.
Furthermore, this makes us correctly throw AbstractMethodErrors in
cases where all default implementations of a method are overridden by
abstract declarations.
Adds 3 tests for this new behavior.
Bug: 24618811
Change-Id: Id891958a81f9b3862b2ce5919636aabef7d3422e
erified_method.cc
|
| da5b28adf5ba013f0784578a8b97577782e23d95 |
05-Nov-2015 |
Mathieu Chartier <mathieuc@google.com> |
Revert "Revert "Add basic image writer support for app images""
No changes, bug fixed in:
https://android-review.googlesource.com/#/c/180886/
Bug: 22858531
This reverts commit 4b018565e57c3349a3c1b5ec8ac9dae261c5e00b.
Change-Id: I86d9c2b55d535d803c6e1b3b8b4836bf6ff077e5
uick/arm64/call_arm64.cc
|
| 4b018565e57c3349a3c1b5ec8ac9dae261c5e00b |
05-Nov-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Add basic image writer support for app images"
interpreter and jit tests fail.
Bug: 22858531
This reverts commit c033474cfbfe1e963c07fa5c38aed02e35ed6f91.
Change-Id: Ic12a3e2a1908ac0db52d21a0b44b2508c88b2585
uick/arm64/call_arm64.cc
|
| c033474cfbfe1e963c07fa5c38aed02e35ed6f91 |
02-Nov-2015 |
Mathieu Chartier <mathieuc@google.com> |
Add basic image writer support for app images
Needed to handle references from app image -> boot image.
Generate app images for tests to enable some testing.
Bug: 22858531
Change-Id: I1af98b6c4dfcb3a147fb5b0dea64aa4946c7ce57
uick/arm64/call_arm64.cc
|
| f31f9739e6cb06298604f5fb723db2ab9a8f2962 |
30-Oct-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Refactor code so that JIT can parse compiler options."
|
| abbb0f76b07417f13f712f54d5afddb72e3b9931 |
29-Oct-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Refactor code so that JIT can parse compiler options.
Currently only the CompilerOptions class. We should also
do it for the CompilerDriver options.
This will fix the flakiness seen on jdwp testing, as the
debuggable flag was not passed to the compiler.
Change-Id: I4218dd5928c9f4fe2d6191ab11e5598e7cf84bcf
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| 9507fa2c9545156747a5eb248bc1af3159bfd8c8 |
29-Oct-2015 |
Mathieu Chartier <mathieuc@google.com> |
Change a few places to use string version of GetTypeId
GetTypeId is about 20% faster than GetStringId + integer GetTypeID
since it does less binary searches.
Change-Id: I876c4ac89ab206acca217b2287b0197ef2e408c2
uick/dex_file_method_inliner.cc
|
| 55d02cf056f993aeafebd54e7b7c68c7a48507c9 |
29-Oct-2015 |
Andreas Gampe <agampe@google.com> |
Revert "Enable store elimination for singleton objects."
This reverts commit 7f43a3d48fc29045875d50e10bbc5d6ffc25d61e.
Fails booting.
Bug: 25357772
Change-Id: Ied19536f3ce8d81e76885cb6baed4853e2ed6714
uick/gen_common.cc
|
| 7f43a3d48fc29045875d50e10bbc5d6ffc25d61e |
28-Oct-2015 |
Mingyao Yang <mingyao@google.com> |
Enable store elimination for singleton objects.
Enable store elimination for singleton objects. However for finalizable object,
don't eliminate stores. Also added a testcase.
Change-Id: Icf991e7ded5b490f55f580ef928ece5c45e89902
uick/gen_common.cc
|
| 35831e8bfa1c0944d4c978d99c4c5b9577945170 |
11-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Reduce memory used by CompiledMethods.
Use LengthPrefixedArray<>s instead of SwapVector<>s to store
CompiledMethod data and get rid of the unnecessary members
of CompiledMethod to reduce dex2oat memory usage. Refactor
the deduplication from CompilerDriver to a new class.
Use HashSet<> instead of std::set<> for the DedupeSet<> to
further decrease the memory usage and improve performance.
This reduces the dex2oat memory usage when compiling boot
image on Nexus 5 (with Optimizing, -j1) by ~6.75MiB (5%).
This also reduces the compile time by ~2.2% (~1.6% dex2oat
time; with Optimizing, without -j).
Change-Id: I974f1f5e58350de2bf487a2bca3907fa05fb80ea
ex_to_dex_compiler.cc
uick/codegen_util.cc
uick/ralloc_util.cc
|
| e5d80f83ae53792bc1eebd4e33e4e99f7c031b0c |
16-Oct-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move ArenaBitVector into the runtime
Motivation is using arenas in the verifier.
Bug: 10921004
Change-Id: I3c7ed369194b2309a47b12a621e897e0f2f65fcf
vn_dead_code_elimination.cc
ir_graph.h
|
| 58554b7de4b437ddef7ff550e62c8ec0b16f9264 |
21-Oct-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix left-shift of negative numbers
Shifting negative numbers is undefined.
Change-Id: I0c32a3fcf372eae74507a5f2383edbfaf5c6830c
ocal_value_numbering_test.cc
|
| 524e7ea8cd17bad17bd9f3e0ccbb19ad0d4d9c02 |
16-Oct-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Remove ArtCode.
- Instead use OatQuickMethodHeader.
- Various cleanups now that we don't have all those
ArtMethod -> ArtCode -> OatQuickMethodHeader indirections.
As a consequence of this cleanup, exception handling got a bit
faster.
ParserCombinators benchmark (exception intensive) on x64: (lower is better)
Before:
ParserCombinators(RunTime): 1062500.0 us.
After:
ParserCombinators(RunTime): 833000.0 us.
Change-Id: Idac917b6f1b0dc254ad68fb3781cd61bccadb0f3
uick/x86/assemble_x86.cc
uick/x86/target_x86.cc
|
| 4b8f1ecd3aa5a29ec1463ff88fee9db365f257dc |
26-Aug-2015 |
Roland Levillain <rpl@google.com> |
Use ATTRIBUTE_UNUSED more.
Use it in lieu of UNUSED(), which had some incorrect uses.
Change-Id: If247dce58b72056f6eea84968e7196f0b5bef4da
ir_graph.cc
ass.h
ass_driver.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
uick/ralloc_util.cc
uick/x86/assemble_x86.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
erification_results.cc
|
| eb7c144a6aff7da673ba53d501c46f00311d4d7f |
31-Aug-2015 |
Alex Light <allight@google.com> |
Add initial default method support to Art
This commit starts the process of adding default methods and their
associated pieces to ART.
This adds full support for calling default methods using
invoke-interface and invoke-virtual on objects implementing the
interfaces. Verifier is changed to allow this when the runtime is
started with -Xexperimental:default-methods.
This also adds support for defining and calling static methods on
interface classes with invoke-static.
Directly calling overridden default methods using invoke-super is not
yet supported.
This adds 5 new run-tests for this functionality.
Bug: 24618811
Change-Id: I35ca800d99d3329348b277789b70ceeeba6e7f03
uick/quick_compiler.cc
|
| 439ffb8d4fa25b4ac7518a3bd5cbc3f3769ead48 |
12-Oct-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Intrinsify System.arraycopy."
|
| ee3cf0731d0ef0787bc2947c8e3ca432b513956b |
06-Oct-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Intrinsify System.arraycopy.
Currently on x64, will do the other architectures in
different changes.
Change-Id: I15fbbadb450dd21787809759a8b14b21b1e42624
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 4bf9012582f5f9cd16fe68fa8585848016caecc6 |
08-Oct-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Do not include endian.h on Mac.
Change-Id: I1bb28bd49bd1847c45e93bf2b06c643be6e09926
uick/codegen_util.cc
|
| ec7802a102d49ab5c17495118d4fe0bcc7287beb |
01-Oct-2015 |
Vladimir Marko <vmarko@google.com> |
Add DCHECKs to ArenaVector and ScopedArenaVector.
Implement dchecked_vector<> template that DCHECK()s element
access and insert()/emplace()/erase() positions. Change the
ArenaVector<> and ScopedArenaVector<> aliases to use the new
template instead of std::vector<>. Remove DCHECK()s that
have now become unnecessary from the Optimizing compiler.
Change-Id: Ib8506bd30d223f68f52bd4476c76d9991acacadc
uick/codegen_util.cc
uick/lazy_debug_frame_opcode_writer.h
|
| 7bda3b600d74c9a5746840ebb8534443e486615a |
07-Oct-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "Quick: Work around large frame sizes for x86_64."
Instead, move the MEMORY_TOOL_MAKE_* calls out-of-line.
Bug: 24729377
This reverts commit d4cf1e4fe0624b99df22ed5556dc1d042b32a7e0.
Change-Id: I9bccc8bd4a691a2d018b84de8b95bc68fafad4e1
lobal_value_numbering.cc
ocal_value_numbering.cc
ocal_value_numbering.h
ir_analysis.cc
|
| d4cf1e4fe0624b99df22ed5556dc1d042b32a7e0 |
07-Oct-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Work around large frame sizes for x86_64.
Bug: 24729377
Change-Id: Id608aabad60fb7f1a1450a02444bddfb0eb008a6
lobal_value_numbering.cc
ocal_value_numbering.cc
ocal_value_numbering.h
ir_analysis.cc
|
| edbff6f51abc2bfb43be78b9a1beaa382c498a1f |
02-Oct-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Use an iterative way in DoDFSPreOrderSSARename()"
|
| e460d1df1f789c7c8bb97024a8efbd713ac175e9 |
29-Sep-2015 |
Calin Juravle <calin@google.com> |
Revert "Revert "Support unresolved fields in optimizing"
The CL also changes the calling convetion for 64bit static field set
to use kArg2 instead of kArg1. This allows optimizing to keep
the asumptions:
- arm pairs are always of form (even_reg, odd_reg)
- ecx_edx is not used as a register on x86.
This reverts commit e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1.
Change-Id: I93159917565824084abc96775f31be1a4249f2f3
uick/gen_invoke.cc
|
| a661d7d12ce5736cab1fe1d3b3d559e37b902b5b |
13-Aug-2015 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Use an iterative way in DoDFSPreOrderSSARename()
This patch changes the recursion to an iterative implementation.
It tries to solve a stack overflow issue when installing
Facebook on some devices. The recursion reaches more than 2600
levels when compiling
"java.util.Map com.facebook.graphql.model.GraphQLNodeDeserializer.a()".
Change-Id: Ibe74359526e10fe6afa833e3bb46b6138aaf5435
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
sa_transformation.cc
|
| 97a87ec836ff8f480af1166d05b92dad1c5daadd |
29-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Avoid shifting -1 left (undefined behavior).
C++11 clarifies that shifting left a negative value is
undefined behavior. Fix legacy code that shifted -1 left.
Bug: 24489455
Change-Id: Iaf4f26c7cde175f039b6a2cad12af6f0b1624fba
uick/codegen_util.cc
|
| 6918bf13eb855b3aa8ccdddda2d27ae8c60cec56 |
28-Sep-2015 |
Igor Murashkin <iam@google.com> |
Revert "Revert "lambda: Experimental support for capture-variable and liberate-variable""
This reverts commit 7bbb80ab52c203e44d2ded2c947b3b03b4b31ec4.
Change-Id: If806ce5c6c5e96fdb2c3761dee096f74e7e5b001
uick/quick_compiler.cc
|
| 7bbb80ab52c203e44d2ded2c947b3b03b4b31ec4 |
27-Sep-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "lambda: Experimental support for capture-variable and liberate-variable"
Test fails.
This reverts commit b72123440d8541362ebdb131436f9dbdda5fd329.
Change-Id: Ic9ed92f8c826d8465eb36b746dc44af05caf041c
uick/quick_compiler.cc
|
| b72123440d8541362ebdb131436f9dbdda5fd329 |
25-Sep-2015 |
Igor Murashkin <iam@google.com> |
lambda: Experimental support for capture-variable and liberate-variable
Supports capturing/liberating any primitive variables.
No support for capturing objects/lambdas yet since they would both
need GC changes to track roots through closures.
Change-Id: Ibfb68bfe4c579dbf93823aac4c0e6ac8f6360c5d
uick/quick_compiler.cc
|
| 87000a948524cba7538ccc5438f6a9ecbd4e347e |
24-Aug-2015 |
Calin Juravle <calin@google.com> |
Add option to append to the cfg dump.
This makes life easier when verifying tests with unresolved classes
(which call dex2oat at rutime).
Change-Id: I7985b2b7c0f343462e03a26b8395297c810b1d95
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| 9af47e27674e70e7f82315d39de5bc659c4e1b83 |
14-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Optimizing: Tag basic block allocations with their source."
|
| 2d06e08d25bbf8eff1de945736a60810009e59ad |
11-Sep-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix Quick-style LR vs PC core spill mask bug"
|
| 9ee23f4273efed8d6378f6ad8e63c65e30a17139 |
23-Jul-2015 |
Scott Wakeling <scott.wakeling@linaro.org> |
ARM/ARM64: Intrinsics - numberOfTrailingZeros, rotateLeft, rotateRight
Change-Id: I2a07c279756ee804fb7c129416bdc4a3962e93ed
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 501fd635a557645ab05f893c56e1f358e21bab82 |
11-Sep-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix Quick-style LR vs PC core spill mask bug
It's always been a bug that Quick marked PC as spilled instead of
LR. The root cause was a mutation of the spill mask at frame exit,
when LR is being restored into PC to return. A local should have
been used to keep the actual spill mask safe and sound.
This has only worked because nobody ever uses LR, even after long
jumps for exception dispatch. However, single-frame deoptimization
needs this to work, and I'd rather fix this than being forced to
have machine-specific fixups.
Also fix in optimizing, and bump the oat version.
Change-Id: Ib032a533408bf464097fc96dcbfc5b6a68bf59a1
uick/arm/call_arm.cc
|
| 6058455d486219994921b63a2d774dc9908415a2 |
03-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Tag basic block allocations with their source.
Replace GrowableArray with ArenaVector in HBasicBlock and,
to track the source of allocations, assign one new and two
Quick's arena allocation types to these vectors. Rename
kArenaAllocSuccessor to kArenaAllocSuccessors.
Bug: 23736311
Change-Id: Ib52e51698890675bde61f007fe6039338cf1a025
lobal_value_numbering_test.cc
vn_dead_code_elimination_test.cc
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_optimization_test.cc
ype_inference_test.cc
|
| 957fb8930766ae422568e7b1b816159a9e9bc18c |
04-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Move DexCache arrays to native."
|
| 897ce64153e4758663e464fb5fb339f9a7b496c8 |
04-Sep-2015 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Reduce how often we call FindDexCache"
|
| 736b560f2d2c89b63dc895888c671b5519afa4c8 |
02-Sep-2015 |
Mathieu Chartier <mathieuc@google.com> |
Reduce how often we call FindDexCache
Before host boot.oat -j4 optimizing compile:
real 1m17.792s
user 3m26.140s
sys 0m8.340s
After:
real 1m12.324s
user 3m22.718s
sys 0m8.320s
Change-Id: If18e9e79e06cdf1676692e5efacb682bf93889c3
ex_to_dex_compiler.cc
ir_analysis.cc
ir_field_info.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.cc
ir_optimization.cc
uick/quick_compiler.cc
uick/quick_compiler.h
ype_inference_test.cc
|
| 05792b98980741111b4d0a24d68cff2a8e070a3a |
03-Aug-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Move DexCache arrays to native.
This CL has a companion CL in libcore/
https://android-review.googlesource.com/162985
Change-Id: Icbc9e20ad1b565e603195b12714762bb446515fa
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/gen_common.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir-inl.h
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/int_x86.cc
|
| 145acc5361deb769eed998f057bc23abaef6e116 |
03-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "Optimizing: Tag basic block allocations with their source."
Reverting so that we can have more discussion about the STL API.
This reverts commit 91e11c0c840193c6822e66846020b6647de243d5.
Change-Id: I187fe52f2c16b6e7c5c9d49c42921eb6c7063dba
lobal_value_numbering_test.cc
vn_dead_code_elimination_test.cc
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_optimization_test.cc
ype_inference_test.cc
|
| 91e11c0c840193c6822e66846020b6647de243d5 |
02-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Tag basic block allocations with their source.
Replace GrowableArray with ArenaVector in HBasicBlock and,
to track the source of allocations, assign one new and two
Quick's arena allocation types to these vectors. Rename
kArenaAllocSuccessor to kArenaAllocSuccessors.
Bug: 23736311
Change-Id: I984aef6e615ae2380a532f5c6726af21015f43f5
lobal_value_numbering_test.cc
vn_dead_code_elimination_test.cc
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_optimization_test.cc
ype_inference_test.cc
|
| f9f6441c665b5ff9004d3ed55014f46d416fb1bb |
02-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Tag Arena allocations with their source.
This adds the ability to track where we allocate memory
when the kArenaAllocatorCountAllocations flag is turned on.
Also move some allocations from native heap to the Arena
and remove some unnecessary utilities.
Bug: 23736311
Change-Id: I1aaef3fd405d1de444fe9e618b1ce7ecef07ade3
ex_to_dex_compiler.cc
ir_graph.h
uick/codegen_util.cc
|
| 673ed3d8aedc5462a47ded827c99f35d46525457 |
28-Aug-2015 |
Mathieu Chartier <mathieuc@google.com> |
Revert "Revert "Change dex caches to be weak roots""
This reverts commit 81a9087f0df0518c39405b7d18ba5858a6d8b77b.
Boot.oat creation time goes from 4.7s to 4.9s on host due to extra
locking. Will try to improve this in another CL.
Bug: 23602225
Bug: 22720414
Change-Id: I7e25b75cfb63faa196c7b0f60e46cce50bf12021
ir_method_info.cc
|
| 0760a81257fa427646c309500d603194009265ef |
27-Aug-2015 |
Andreas Gampe <agampe@google.com> |
ART: Propagate verifier failure types to the compilers
Add a bit-set encoding of seen failure types to the verifier and
make it available. Store this in VerifiedMethod, so that compilers
can inspect it and make choices based on failures. Rewrite the
current punting of runtime-throw errors to be at the compiler-driver
level.
Bug: 23502994
Change-Id: I1cfc7cbdf2aec1f14ba18f0169e432ba4ae16883
uick/quick_compiler.cc
erified_method.cc
erified_method.h
|
| ff73498a5539d87424a964265e43765e788aec44 |
24-Aug-2015 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
Revert "Revert "[MIPS] Use hard float calling convention for managed code""
This reverts commit 7fee84c087e0f903e7d43bef180df047db1c8051.
Fixed issue with temporary registers on Mips32r6.
Change-Id: I93018927e6a6036cff2d55e6cda66d3212a4316b
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
|
| 7fee84c087e0f903e7d43bef180df047db1c8051 |
21-Aug-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "[MIPS] Use hard float calling convention for managed code"
MipsMir2Lir::LockCallTemps() is broken for secondary architecture on aosp_mips64-eng.
This reverts commit a29449dcf57c57fe0876f51367985477317cc557.
Change-Id: I480ea7569d73aea7894fc0a6dd804b1135286a37
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
|
| a29449dcf57c57fe0876f51367985477317cc557 |
22-Jul-2015 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
[MIPS] Use hard float calling convention for managed code
Note that this isn't o32 ABI. Same set of registers is used for
arguments ($a0-$a3 and $f12-$f15), but we don't skip registers
and fp arguments are never passed via core registers.
Change-Id: Ifb883ff6e15758b539137898b49ac2f8ee075f49
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
|
| 581550137ee3a068a14224870e71aeee924a0646 |
19-Aug-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "Revert "Optimizing: Better invoke-static/-direct dispatch.""
Fixed kCallArtMethod to use correct callee location for
kRecursive. This combination is used when compiling with
debuggable flag set.
This reverts commit b2c431e80e92eb6437788cc544cee6c88c3156df.
Change-Id: Idee0f2a794199ebdf24892c60f8a5dcf057db01c
uick/codegen_util.cc
|
| d9c4d2e9a9bc01fd82a895091126406081fafb1f |
19-Aug-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Revert "Optimizing: Better invoke-static/-direct dispatch.""
|
| b2c431e80e92eb6437788cc544cee6c88c3156df |
19-Aug-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "Optimizing: Better invoke-static/-direct dispatch."
Reverting due to failing ndebug tests.
This reverts commit 9b688a095afbae21112df5d495487ac5231b12d0.
Change-Id: Ie4f69da6609df3b7c8443412b6cf7f5c43c2c5d9
uick/codegen_util.cc
|
| 464581adaf895d14f73db3d768729f0c9c6f5366 |
19-Aug-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Optimizing: Better invoke-static/-direct dispatch."
|
| 9b688a095afbae21112df5d495487ac5231b12d0 |
06-May-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Better invoke-static/-direct dispatch.
Add framework for different types of loading ArtMethod*
and code pointer retrieval. Implement invoke-static and
invoke-direct calls the same way as Quick. Document the
dispatch kinds in HInvokeStaticOrDirect's new enumerations
MethodLoadKind and CodePtrLocation.
PC-relative loads from dex cache arrays are used only for
x86-64 and arm64. The implementation for other architectures
will be done in separate CLs.
Change-Id: I468ca4d422dbd14748e1ba6b45289f0d31734d94
uick/codegen_util.cc
|
| f71ad9ede9ae322a897e8fe407208dc35c5dee65 |
18-Aug-2015 |
Alex Light <allight@google.com> |
Merge "Svelter libart-compiler"
|
| 50fa993d67f8a20322c27c1a77e7efcf826531fc |
11-Aug-2015 |
Alex Light <allight@google.com> |
Svelter libart-compiler
Added new environment variable ART_{TARGET,HOST}_CODEGEN_ARCHS which
may be set to 'all', 'svelte' or a space separated list of architectures.
When compiled with ART_{TARGET,HOST}_CODEGEN_ARCHS='all' (the default
value) dex2oat will be able to generate output for all supported
architectures.
When compiled with ART_TARGET_CODEGEN_ARCHS='svelte'
only the architectures of the TARGET will be included. When
ART_HOST_CODEGEN_ARCHS='svelte' all architectures the target includes
and the host architectures will be included on the host dex2oat.
If a list of architectures is given only those will be included.
Change-Id: I87f4ad0131ab1b37544d8799e947ce4733b6daec
uick/quick_compiler.cc
|
| 151ab8d096be02b04391fd32460a31ee60ae2b0a |
15-Aug-2015 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: DCHECK zero case for CLZ/CTZ""
This reverts commit 4318d91ea4be673d4deba39d33ac4718d77986a7.
Fix up the lit=-1 case in the arm32 Quick backend; add test case.
Change-Id: I8d0861133db950090ee959f532ede1448683dfa9
uick/arm/int_arm.cc
|
| 7c2af0d873b7033adccf8fa7adf259166c53d369 |
13-Aug-2015 |
Roland Levillain <rpl@google.com> |
Merge "Remove unnecessary `explicit` qualifiers on constructors."
|
| 7da072feb160079734331e994ea52760cb2a3243 |
13-Aug-2015 |
agicsaki <agicsaki@google.com> |
Structure for String.Equals intrinsic
Added structure for implementing String.Equals intrinsics. There is no
functional change at this point- the intrinsic is marked as unimplemented
for all instruction sets and compilers.
Bug: 21481923
Change-Id: Ic2a1e22a113ff6091581126f12e926478c011340
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 3887c468d731420e929e6ad3acf190d5431e94fc |
12-Aug-2015 |
Roland Levillain <rpl@google.com> |
Remove unnecessary `explicit` qualifiers on constructors.
Change-Id: Id12e392ad50f66a6e2251a68662b7959315dc567
ompiler_ir.h
ir_field_info.h
ir_graph.h
ass_driver_me.h
ass_driver_me_opts.h
ass_driver_me_post_opt.h
uick/lazy_debug_frame_opcode_writer.h
|
| 548a3ce2625bc1da12034411036e5a94da183696 |
12-Aug-2015 |
Roland Levillain <rpl@google.com> |
Merge "[MIPS] Avoid using odd numbered fp registers"
|
| 2f2f17399f6bdfc5ec94a875152c31ef79620520 |
09-Aug-2015 |
Serguei Katkov <serguei.i.katkov@intel.com> |
ART: Fix Quick's DCE+GVN
DCE_GVN does not take into account the following case:
mov a, b
...
mov c, b
when optimization tries to replace a with c it must ensure that
for all uses of a there is no new definition of c before use.
Otherwise that use will incorrectly substituted with new c instead
of original b.
Bug: 23102860
Change-Id: I48ee0bd4386419b0f9c814c21b3537a392518cd1
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
vn_dead_code_elimination.cc
vn_dead_code_elimination_test.cc
|
| fc8156a3df88e259c892d50bf23f7c4f11531844 |
28-Jul-2015 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
[MIPS] Avoid using odd numbered fp registers
Don't use odd numbered fp registers for single precision data on
MIPS32r6 (64-bit FPU).
Bug: 23050326
Change-Id: I35cc19df091149773411e2336b01c170929376bc
uick/mips/target_mips.cc
|
| 067f1ed7816cf4eb5d6258ca31b387ddb2073ab7 |
07-Aug-2015 |
Andreas Gampe <agampe@google.com> |
ART: Remove TODO in BitVector
Refactor the BitVector constructor: split it up to remove the
possibility to provide contradicting parameters, and add a custom
copying constructor.
Change-Id: Ie943f279baa007db578aea0f2f33fa93311612ee
vn_dead_code_elimination.cc
|
| 5eb0d38dabda4d17a315c557f07f457308d28fa7 |
23-Jul-2015 |
Andreas Gampe <agampe@google.com> |
ART: Wire up DexToDexCompiler without extern
The extern declaration actually had the wrong signature, a parameter
was missing, and we never noticed.
Remove the function field and extern. Add a header for the compiler.
Use the header file.
Change-Id: Ia4d4dd86211da6045709a45c7bf8430471d1b62b
ex_to_dex_compiler.cc
ex_to_dex_compiler.h
|
| 611d3395e9efc0ab8dbfa4a197fa022fbd8c7204 |
10-Jul-2015 |
Scott Wakeling <scott.wakeling@linaro.org> |
ARM/ARM64: Implement numberOfLeadingZeros intrinsic.
Change-Id: I4042fb7a0b75140475dcfca23e8f79d310f5333b
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| aabdf8ad2e8d3de953dff5c7591e7b3df4d4f60b |
03-Aug-2015 |
Roland Levillain <rpl@google.com> |
Revert "Optimizing String.Equals as an intrinsic (x86)"
Reverted as it breaks the compilation of boot.{oat,art} on x86 (although this CL may not be the culprit, as the issue seems to come from Optimizing's register allocator).
This reverts commit 8ab7bd6c8b10ad58758c33a1dc9326212bd200e9.
Change-Id: If7c8b6258d1e690f4d2a06bcc82c92563ac6cdef
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 8ab7bd6c8b10ad58758c33a1dc9326212bd200e9 |
27-Jul-2015 |
agicsaki <agicsaki@google.com> |
Optimizing String.Equals as an intrinsic (x86)
The third implementation of String.Equals. I added an intrinsic
in x86 which is similar to the original java implementation of
String.equals: an instanceof check, null check, length check, and
reference equality check followed by a loop comparing strings
character by character.
Interesting Benchmarking Values:
Optimizing Compiler on Nexus Player
Intrinsic 15-30 Character Strings: 177 ns
Original 15-30 Character Strings: 275 ns
Intrinsic Null Argument: 59 ns
Original Null Argument: 137 ns
Intrinsic 100-1000 Character Strings: 1812 ns
Original 100-1000 Character Strings: 6334 ns
Bug: 21481923
Change-Id: Ia386e19b9dbfe0dac688b20ec93d8f90f67af47e
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| c60e1b755c5632dfeb04c333489ede52ee5c945f |
30-Jul-2015 |
Andreas Gampe <agampe@google.com> |
ART: Use __ANDROID__ instead of HAVE_ANDROID_OS
Use the proper define.
Change-Id: I71e291ac25f5d5f0187ac9b6ef2d6872f19e6085
uick/quick_cfi_test.cc
|
| 0941b9d48a9a8c6d80a1af7a0d0fc9f80fe2b9a1 |
29-Jul-2015 |
Calin Juravle <calin@google.com> |
Fix gtests.
Change-Id: I19fd46ed96b4f620209533c96faa18d1077b004b
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| f7efc9ef90c38212f8c4fbece99080f784a53181 |
23-Jul-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Fix Quick/Optimizing suspend check assumption mismatch."
|
| d29e8487ff1774b6eb5f0e18d854415c1ee8f6b0 |
22-Jul-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Fix Quick/Optimizing suspend check assumption mismatch.
Quick's SuspendCheckElimination (SCE) expects that every
method contains a suspend check and it eliminates suspend
checks in loops containing an invoke. Optimizing eliminates
the suspend check from leaf methods, so the combination of
a Quick-compiled loop calling an Optimizing-compiled leaf
method can lead to missing suspend checks and potentially
leading to ANRs.
Enable Quick's kLeafOptimization flag to remove suspend
checks from leaf methods and disable Quick's SCE. This
aligns the suspend check placement for the two backends
and avoids the broken combination.
Currently, all methods containing a try-catch are compiled
with Quick, so it's relatively easy to create a regression
test. However, this test will not be valid when Optimizing
starts supporting try-catch.
Bug: 22657404
Change-Id: I3bc40bf3f5c1e7d18704d1547b139e939950b770
ir_graph.h
ir_optimization.cc
ir_optimization_test.cc
|
| 90443477f9a0061581c420775ce3b7eeae7468bc |
17-Jul-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move to newer clang annotations
Also enable -Wthread-safety-negative.
Changes:
Switch to capabilities and negative capabilities.
Future work:
Use capabilities to implement uninterruptible annotations to work
with AssertNoThreadSuspension.
Bug: 20072211
Change-Id: I42fcbe0300d98a831c89d1eff3ecd5a7e99ebf33
ir_field_info.h
ir_method_info.h
uick/dex_file_method_inliner.h
uick/quick_compiler.h
uick_compiler_callbacks.h
erification_results.h
erified_method.h
|
| cced6ad152cf8ec13f38f2210c1b8445919232d3 |
16-Jul-2015 |
Roland Levillain <rpl@google.com> |
Merge "Use (D)CHECK_ALIGNED more."
|
| 8f861e399c96abd8f1bc7c8c585d53b0904f371a |
16-Jul-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: DCE should know that array-length can throw NPE"
|
| b016c6dd3c30b04104a0a43dc294ce93e5f63874 |
14-Jul-2015 |
Serguei Katkov <serguei.i.katkov@intel.com> |
ART: DCE should know that array-length can throw NPE
array-length can throw NPE so it should be taking into account.
Bug: 22521944
Change-Id: I6f961560ccbbf81f57f1c597828f2ee18e2c3054
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
vn_dead_code_elimination.cc
vn_dead_code_elimination_test.cc
|
| 14d90579f013b374638b599361970557ed4b3f09 |
16-Jul-2015 |
Roland Levillain <rpl@google.com> |
Use (D)CHECK_ALIGNED more.
Change-Id: I9d740f6a88d01e028d4ddc3e4e62b0a73ea050af
uick/arm/assemble_arm.cc
uick/arm/utility_arm.cc
uick/arm64/assemble_arm64.cc
uick/mips/utility_mips.cc
uick/x86/utility_x86.cc
|
| c04c800e7bda94abfadc8c2d30f58c50b261b612 |
14-Jul-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Revert "Revert "Make dex2dex return a CompiledMethod after quickening.""""
This reverts commit ed6195a514e3253576af27ea9ba13038509d29ac.
Change-Id: Icb58854301e8982147cdebe3edf2e0d9e0a63a56
ex_to_dex_compiler.cc
|
| ed6195a514e3253576af27ea9ba13038509d29ac |
13-Jul-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Revert "Make dex2dex return a CompiledMethod after quickening."""
Breaks again in some configurations I don't fully understand yet.
This reverts commit f075879649686e59b7a9065c5a061dbfdcdfbecc.
Change-Id: I0ac5533825e40b06462ee69b2740e4a96fb5c582
ex_to_dex_compiler.cc
|
| f075879649686e59b7a9065c5a061dbfdcdfbecc |
13-Jul-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Make dex2dex return a CompiledMethod after quickening.""
This reverts commit 327c5ed30a1f016ef3e1bb26ea7b4abd34eb63b9.
Change-Id: I0dc5d92e5d1ef98830fbd3c40ec59a93f9e0422d
ex_to_dex_compiler.cc
|
| 327c5ed30a1f016ef3e1bb26ea7b4abd34eb63b9 |
13-Jul-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Make dex2dex return a CompiledMethod after quickening."
Build failures on arm/arm64.
This reverts commit 6920703c8eae0d90528ea09945e742582b6f8198.
Change-Id: I0dd5426610150937dac6e4d9dd9aa759bdf7fca4
ex_to_dex_compiler.cc
|
| 6920703c8eae0d90528ea09945e742582b6f8198 |
09-Jul-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Make dex2dex return a CompiledMethod after quickening.
This is the starting piece of pushing more verification and
dex2dex data into an .oat file, to lower the dependency on verification
results at runtime.
Change-Id: I8e1b49a0207714bc5b84d1f606806718c5c7fb69
ex_to_dex_compiler.cc
|
| c7d5ae363bc43ebba0f21c6ee4a2164dfbb209a9 |
08-Jul-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Release inputs in Long.reverse intrinsic in x86"
|
| 575422fa5be7389bdaff5e2d25dd87b1d2d4de85 |
07-Jul-2015 |
Andreas Gampe <agampe@google.com> |
ART: Release inputs in Long.reverse intrinsic in x86
In the worst case we are using two temps each for input and output.
Then we do not have a temp left over for the swap operations. The
input is dead, however, after the first swap. So try to release it
(a no-op if it isn't actually a temp).
Bug: 22324327
Change-Id: I1fc50159afdad14160e34abeaf4670958171d6b2
uick/x86/int_x86.cc
|
| 185a5586c8b796e770e9b4b7ac2befa8ccdaca7e |
06-Jul-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix opsize in LoadArgDirect
If the destination register is a reference, use kReference for the
op size.
Bug: 22244733
Change-Id: Idf52f2ee4c65b5dc41cb66257d95281dc6f32255
uick/mir_to_lir.cc
|
| 22bb5a2ebc1e2724179faf4660b2735dcb185f21 |
03-Jul-2015 |
Douglas Leung <douglas.leung@imgtec.com> |
Add implicit null pointer and stack overflow checks for Mips.
Bug: 21555893
Change-Id: I2a995be128a5603d08753c14956dd8c8240ac63c
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
|
| 4d02711ea578dbb789abb30cbaf12f9926e13d81 |
01-Jul-2015 |
Roland Levillain <rpl@google.com> |
Implement heap poisoning in ART's Optimizing compiler.
- Instrument ARM, ARM64, x86 and x86-64 code generators.
- Note: To turn heap poisoning on in Optimizing, set the
environment variable `ART_HEAP_POISONING' to "true"
before compiling ART.
Bug: 12687968
Change-Id: Ib3120b38cf805a8a50207a314b9ccc90c8d93740
uick/quick_compiler.cc
|
| 2b252dc15995a708aead33aab6d307205d860a88 |
01-Jul-2015 |
Andreas Gampe <agampe@google.com> |
Merge "Quick: Fix a DCHECK to take type conflicts into account."
|
| 5e6926cf67b50bcab56dc244e09b6f8f608d4ca2 |
27-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix a DCHECK to take type conflicts into account.
Bug: 21865466
Change-Id: I010c7058b5a58bea1ec61af5bd6a12c2eb8de1b4
uick/gen_loadstore.cc
|
| f7e7327d7a873d21aaae01471f46a4d64d65433b |
27-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Disable GVN, DCE and LVN for type conflicts.
Bug: 22136903
Change-Id: I657d4b5e623696e1264c2c6c9ad4e7fd466d759c
ype_inference.cc
|
| c83329952b4a313e747c8835a73699e2cae5a6e2 |
26-Jun-2015 |
buzbee <buzbee@google.com> |
ART: Fix kEverything compiler filter
Previously the kEverything filter failed to compile class
initializers. Now it will.
Bug: 19576257
Change-Id: I189d2b5b379aee112c4e95f8d3e6c32abab6ed41
erification_results.cc
|
| 4824c27988c8eeb302791624bb3ce1d557b0db6c |
24-Jun-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Use a flag from the verifier to know if we should compile.
Only used for the lack of bottom type in the aget-object case
for now. Could be used for more.
bug:21865466
Change-Id: I64c2c84dfa1c0d259631e65e5f44b94e4139e6a7
uick/quick_compiler.cc
erified_method.cc
erified_method.h
|
| 87dc1b09cee6e972fbe3ad48ba8b5ae68d37085f |
23-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Compiler generated GC map should take care of temp registers."
|
| ec3a4e7cdc4f268b40d923227c125429f4ee4884 |
22-Jun-2015 |
Igor Murashkin <iam@google.com> |
Merge "runtime: Partially implement box-lambda and unbox-lambda experimental opcodes"
|
| 2ee54e249ad21c74f29a161e248bebe7d22fddf1 |
18-Jun-2015 |
Igor Murashkin <iam@google.com> |
runtime: Partially implement box-lambda and unbox-lambda experimental opcodes
These opcodes are not yet fully specified, and *will* change before they become shippable.
Do not write production code against experimental opcodes.
--
Implement partial interpreter support for new dex instructions box/unbox-lambda.
* box-lambda will take a closure and convert it into an Object
* unbox-lambda will take an Object and convert it to a closure
(Currently does not implement object identity or variable capture).
All new opcodes are disabled by default, use runtime option -Xexperimental-lambdas to enable them.
Change-Id: I3c15ccf8a26ccecd1d35808a8c1b4149220f6019
uick/quick_compiler.cc
|
| f8da196097d1b33121a73abcaf443d173ceab8eb |
19-Jun-2015 |
Mathieu Chartier <mathieuc@google.com> |
Fix GC map generation edge case
Previously we checked the number of bits, but then rounded up to a
byte boundary. If ref_bitmap_bits was 65535, it would pass the check
but not actually fit in the 13 bits for ref_bitmap_bytes since we
rounded up to 8192 bytes.
(cherry picked from commit 1626b919005df42ccc90ebe68fc57b7c56d44029)
Regression test infeasible due to smali limitations.
Bug: 21888453
Change-Id: If4b769431f27ecca14fe7852d017bcde01b3e146
erified_method.cc
|
| dde9827f75d1e1e9cd4b7e6b54086aec54f29b5f |
18-Jun-2015 |
Jeff Hao <jeffhao@google.com> |
Fix case where block has no predecessor for StringChange.
Removes part that checks for throwing half of instruction. It's no
longer necessary. Also adds regression test.
Bug: 21902684
(cherry-picked from commit 3e91a44bc9063f7f69b5415e3cf162991f73283f)
Change-Id: I8d7308ff227816fb475341c2b74ed84d5695a2f5
ir_optimization.cc
|
| e4bb626ff09e409c9482e515716de7cd595ea466 |
19-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Handle total high/low register overlap on arm/mips."
|
| 8958f7f8702327e713264d0538ab5dec586f3738 |
19-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Handle total high/low register overlap on arm/mips.
OpRegCopyWide() in arm and mips backends didn't handle the
total register overlap when the registers holding the source
and destination pairs are the same but in reverse order.
Bug: 21897012
Change-Id: Ia1f0005cbf5cc1c2d30899575dea21b3efa20ae6
uick/arm/int_arm.cc
uick/mips/int_mips.cc
|
| f11c420c448baffac6a70ac0884d481ab347e257 |
19-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix optimizations for empty if blocks.
If a block ending with if-eqz or if-nez has the same "taken"
and "fallthrough", we cannot assume that the value has been
checked against zero in one of the succesors. This affects
the null check elimination pass as well as GVN. Refactor all
those checks to a single function in BasicBlock and check
that the "taken" and "falthrough" are different when needed.
Bug: 21614284
Change-Id: I8c6ac23e96cdaf5984786a555ebbd28110f095cb
lobal_value_numbering.cc
lobal_value_numbering.h
ir_graph.h
ir_optimization.cc
|
| 247e97746016b49183b52f4c386bedf7cd53e590 |
18-Jun-2015 |
Igor Murashkin <iam@google.com> |
Merge "interpreter: Add experimental lambda opcodes for invoke/create-lambda"
|
| 2d1a0a408fd148f7b2a2d670e6942ec3d920f875 |
18-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Don't expect move-exception in every catch block.
The dalvik bytecode doesn't require a move-exception in
a catch handler that ignores the exception.
Bug: 21873167
Change-Id: I3b49218a8c7ff021141387bd929bb2ae798f8509
ir_graph.cc
|
| 158f35c98e2ec0d40d2c032b8cdce5fb60944a7f |
11-Jun-2015 |
Igor Murashkin <iam@google.com> |
interpreter: Add experimental lambda opcodes for invoke/create-lambda
These opcodes are not yet fully specified, and *will* change before they become shippable.
Do not write production code against experimental opcodes.
--
Implement partial interpreter support for new dex instructions invoke/create-lambda, and a
new opcode format 25x.
* Does not verify, in fact verification will soft fail when we see those opcodes.
* Compilers will punt to interpreter since they don't support new opcodes.
* As there is no way to capture/liberate variables yet, the "closure" is just
an ArtMethod for the time being.
All new opcodes are disabled by default, use runtime option -Xexperimental-lambdas to enable them.
For example:
dalvikvm ... -Xexperimental-lambdas ...
dex2oat --runtime-arg -Xexperimental-lambdas ...
Change-Id: I6c996ca32a9b54ec45ec21d7a959b84dfb8a24eb
ir_graph.cc
uick/quick_compiler.cc
|
| 511d408909b7fe9be3c95e032cc7f426f4a01e6e |
17-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix marking unused registers in DCE.
Bug: 21702651
Change-Id: Idca17b465152e0c61704fc49761c7ba89caf5b20
vn_dead_code_elimination.cc
vn_dead_code_elimination_test.cc
|
| 41f9cc28f2c9edd3903ba6ca1c75b022445552ad |
16-Jun-2015 |
Pavel Vyssotski <pavel.n.vyssotski@intel.com> |
ART: Compiler generated GC map should take care of temp registers.
If the compiler use a temp register as a reference it should be
added to generated GC map along with other SSA regs.
Change-Id: I3c79896dcd72228c9cf2bbbe737642d9ffb7684d
Signed-off-by: Pavel Vyssotski <pavel.n.vyssotski@intel.com>
uick/codegen_util.cc
|
| c449e8b79aaaf156ce055524c41474cc1200ed5a |
11-Jun-2015 |
Igor Murashkin <iam@google.com> |
runtime: Minor cleanup and extra comments around interpreter
Change-Id: I24c0b261de8cf737babd9d01bf679482d48c8bc9
erified_method.cc
erified_method.h
|
| 67c8c942e9dfcabd548351db75e6d3b8b5165afa |
08-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix LoopRepeatingTopologicalSortIterator.
Always push the loop head on the loop head stack. This fixes
a bug where we failed to return to an unnatural loop head to
recalculate its GVN data.
Bug: 17410955
Change-Id: I3a2c3225e5d16268c3f56f7f90228759c7da37a9
ataflow_iterator-inl.h
ir_graph_test.cc
ir_optimization.cc
|
| 5b3ee56cd63ee9e3c70c0412d044b81ab9c94513 |
14-Apr-2015 |
Roland Levillain <rpl@google.com> |
Delegate long-to-float type conversions to the runtime on ARM.
On ARM, translate long-to-float type conversions (from both
Quick and Optimizing) as calls to the runtime routine
art_l2f, instead of generating ad hoc code, so as to improve
the precision of the conversions.
Bug: 20413424
Change-Id: I8c414ee1c6f4ff1f32ee78f75734cfd3cf579f71
uick/arm/fp_arm.cc
|
| e401d146407d61eeb99f8d6176b2ac13c4df1e33 |
22-Apr-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move mirror::ArtMethod to native
Optimizing + quick tests are passing, devices boot.
TODO: Test and fix bugs in mips64.
Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.
Some of the savings are from removal of virtual methods and direct
methods object arrays.
Bug: 19264997
Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d
ex_to_dex_compiler.cc
ir_method_info.cc
ir_optimization.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/call_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/quick_cfi_test.cc
uick/quick_cfi_test_expected.inc
uick/quick_compiler.cc
uick/quick_compiler.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/x86_lir.h
ype_inference.cc
ype_inference.h
erified_method.cc
|
| 8363c772581bf00ebcdc2e38391b4bfae51beb75 |
28-May-2015 |
David Srbecky <dsrbecky@google.com> |
Add --generate-debug-info flag and remove the other two flags.
Replace the flags --include-debug-symbols and --include-cfi
with single flag called --generate-debug-info (with alias -g).
The name "symbol" was not ideal, since depending on context it
may be interpreted as "ELF symbols", or "debugging information".
This CL also means that we have only the options to include
either all debugging information or none. This should be fine,
since we can use standard tools to strip anything we do not want.
Change-Id: I721fded56d755d7eed0ef36aa84e841a1f5747f8
uick/codegen_util.cc
uick/quick_cfi_test.cc
uick/x86/quick_assemble_x86_test.cc
|
| dc31313c4577bb4c00d90774159c84e738ed348d |
26-May-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Clean up arm64 kNumberOfXRegisters usage."
|
| 80afd02024d20e60b197d3adfbb43cc303cf29e0 |
19-May-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Clean up arm64 kNumberOfXRegisters usage.
Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.
Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.
Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.
Bug: 13925192
Change-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7
ompiler_ir.cc
ompiler_ir.h
ocal_value_numbering.cc
ocal_value_numbering.h
ir_analysis.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
uick/arm/call_arm.cc
uick/arm/int_arm.cc
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/gen_common.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.h
uick/resource_mask.cc
uick/x86/assemble_x86.cc
uick/x86/int_x86.cc
ype_inference.cc
ype_inference.h
|
| 9bd88b0933a372e6a7b64b850868e6a7998567e2 |
22-Apr-2015 |
Serban Constantinescu <serban.constantinescu@linaro.org> |
ARM64: Move xSELF from x18 to x19.
This patch moves xSELF to callee saved x19 and removes support for
ETR (external thread register), previously used across native calls.
Change-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b
Signed-off-by: Serban Constantinescu <serban.constantinescu@linaro.org>
uick/arm64/arm64_lir.h
uick/arm64/target_arm64.cc
uick/quick_cfi_test_expected.inc
|
| 9cacef6e811940c2f21e7e54055379a2c43f0d06 |
14-May-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix marking high words in DCE.
This CL properly fixes the high word marking and reverts
https://android-review.googlesource.com/150352
which was just covering up the underlying issue. A unit test
for the encountered issue is provided, though it does not
expose the deficiency in the cover-up CL.
Bug: 20640451
Change-Id: Ia19a1134610e271ebbab5679ac0bd0cb0223d462
vn_dead_code_elimination.cc
vn_dead_code_elimination_test.cc
|
| ade58e14582c6ab81978e9cfcbbf5e54cc23fe18 |
12-May-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix DCE, clear high word flag in RemoveChange().
Bug: 20640451
Change-Id: Ibab707ff8e60816b9871c3f4096c0bbbf535cbe8
vn_dead_code_elimination.cc
|
| 83d46ef1eaa8fdecadfdb9564d80e50b42646c37 |
12-May-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix DCE to mark wide register overlaps correctly.
Previously we missed some cases of overlap with registers
coming from previous blocks.
Bug: 20640451
Change-Id: I4b32a7aaea2dea1b0b9560ae3459a4d903683f20
vn_dead_code_elimination.cc
vn_dead_code_elimination.h
vn_dead_code_elimination_test.cc
|
| 7b4de07fffc6dbbbd986bb21b212fa0c4a2aec58 |
07-May-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Fix DCE to rename SSA regs for degenerate Phis."
|
| e299f167c9559401548eab71678d4b779e46c2fb |
07-May-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Abolish kMirOpCheckPart2.
The tricks played with kMirOpCheckPart2 are making the
native GC map generation unnecessarily complex. They have
caused problems in the past and now there is bad interaction
with the DCE. Rather than fixing it time and again, remove
the pseudo-insn.
(The whole purpose of those tricks seems to be to allow the
register tracking to be used for the throwing insn before
resetting the tracking for the next block. However, it's
questionable whether that's better than processing the
throwing insn with the subsequent instructions.)
Bug: 20736048
Change-Id: I4767e4609914d3b6990da4416e5093e4ca209780
ompiler_enums.h
ir_dataflow.cc
ir_graph.cc
uick/codegen_util.cc
uick/mir_to_lir.cc
uick/quick_compiler.cc
|
| f60715c2c0a2398822a143ffb6b75507bffca703 |
07-May-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix DCE to rename SSA regs for degenerate Phis.
If we're inserting a new Phi and all its inputs are the same
SSA reg (for example, we allow a single-input Phi), some
subsequent insn may actually refer to that reg, so we need
to rename it to keep the graph in a consistent state.
Change-Id: Ic6a1907c3138f4a7d3b13f9e58e9107ca2d92f17
vn_dead_code_elimination.cc
vn_dead_code_elimination_test.cc
|
| a412964bf9f8b2aa78e7a4849990381207140850 |
07-May-2015 |
Jeff Hao <jeffhao@google.com> |
In quick compiler, force string init invoke to be fast path.
Was running into an issue where a secondary dex file was falling back on
the quick compiler, and IsFastInvoke returned 0 because the
referrer_class was nullptr, causing the string init to be slow path. The
string init technically does not have to be fast path, but there's no
reason to duplicate the logic to call off a thread pointer on the slow
path.
Bug: 20870917
(cherry picked from commit I47e1524d939eb7e9b1da8186092fafc6e925009e)
Change-Id: Ieacd965943759de2b075c30e03cf0a71863f499e
ir_method_info.cc
|
| f073a36d1ed866e786f7d7784c709c86b00bc58e |
29-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix for incorrect encode and parse of PEXTRW instruction"
|
| e0705f51fdc71e9670a29f8c3a47168f50724b35 |
27-Apr-2015 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
Fix for incorrect encode and parse of PEXTRW instruction
The instruction PEXTRW encoded by sequence 66 0F 3A 15
was incorrectly encoded in compiler table and incorrectly
parsed by disassembler.
Change-Id: Ib4d4db923cb15a76e74f13f6b5514cb0d1cbe164
Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com>
uick/x86/assemble_x86.cc
uick/x86/quick_assemble_x86_test.cc
|
| 2bee20b5f0d783b43c1bbbe281f69a6f9b9e0a98 |
07-Apr-2015 |
Calin Juravle <calin@google.com> |
Quick: Fix crash on fall-through out of method code.
Fix Quick crash when the last insn has a fall-through out of
the method's code. Allow creation of an out-of-method block
and at the end of MIRGraph::InlineMethod() check if that
block is reachable. If it is, punt to interpreter. Add tests
for unreachable if-lt and packed-switch as the last insn.
Also fix MIRGraph::ProcessCanSwitch() to treat the offset to
the data as signed. Jumping over the data with a goto and
using it from a switch further down is valid. This was also
crashing (presumably only on 64-bit dex2oat).
Thanks to Stephen Kyle (stephenckyle@googlemail.com) for the
bug report.
Bug: 19988134
Change-Id: I627f4137f61901897bfb9a5252741c6ded3a1adb
ir_graph.cc
|
| 3adfc4bbe6c42d574bd2069d8e38a13d5ad98ccf |
28-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Avoid unnecessary GVN work in release builds."
|
| a94fb1f99ee3390bca9531b2512f8fc65f13ceee |
28-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Revert "Revert "[optimizing] Replace FP divide by power of 2"""
|
| 9d1e19035a59ff8bf05a09ad880ede99806ba73f |
28-Apr-2015 |
Jeff Hao <jeffhao@google.com> |
Merge "Replace String CharArray with internal uint16_t array."
|
| 848f70a3d73833fc1bf3032a9ff6812e429661d9 |
15-Jan-2014 |
Jeff Hao <jeffhao@google.com> |
Replace String CharArray with internal uint16_t array.
Summary of high level changes:
- Adds compiler inliner support to identify string init methods
- Adds compiler support (quick & optimizing) with new invoke code path
that calls method off the thread pointer
- Adds thread entrypoints for all string init methods
- Adds map to verifier to log when receiver of string init has been
copied to other registers. used by compiler and interpreter
Change-Id: I797b992a8feb566f9ad73060011ab6f51eb7ce01
b_optimizations.h
ir_graph.h
ir_method_info.cc
ir_optimization.cc
ass_driver_me_opts.cc
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/target_x86.cc
erified_method.cc
erified_method.h
|
| 0d22184ec9e5b1e958c031ac92c7f053de3a13a2 |
27-Apr-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "[optimizing] Replace FP divide by power of 2""
This reverts commit 067cae2c86627d2edcf01b918ee601774bc76aeb.
Change-Id: Iaaa8772500ea7d3dce6ae0829dc0dc3bbc9c14ca
uick/mir_to_lir.h
|
| 295dda5066dfeb5bed88a4a484268f94b060c7fb |
27-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Rely on inferred types in GVN/LVN/DCE."
|
| f725550c8df90f8ec07395d9be5177a4be591c12 |
25-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Avoid unnecessary GVN work in release builds.
In GVN's post-processing phase, compare LVNs only in debug
builds as they should be equal anyway.
Remove the Gate() from GVN cleanup pass and remove the
DCHECK() from MIRGraph::GlobalValueNumberingCleanup()
to make it a no-op if the GVN didn't run.
Bug: 16398693
Change-Id: Ia4f1e7e3ecf12d0305966c86e0e7dbae61dab0b7
b_optimizations.cc
b_optimizations.h
lobal_value_numbering.cc
ir_optimization.cc
|
| a5e69e87c630c08c0de1740427e60d531ce851b9 |
24-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Rely on inferred types in GVN/LVN/DCE.
Fix LVN::GetEndingVregValueNumberImpl() to check whether
the requested wideness matches the SSA register type as
recorded in MIRGraph::reg_location_.
Add DCHECKs that the wideness matches when getting/setting
sreg values, update Phi handling in LVN/DCE to use the type
from MIRGraph::reg_location_ instead of determining it from
the sreg value maps which would now trigger the DCHECKs.
Update tests to initialize MIRGraph::reg_location_.
Reenable DCE.
Bug: 20572509
Change-Id: I1a4d4e32cd57807ca8b56d2f3ed5e1288660b82e
lobal_value_numbering_test.cc
vn_dead_code_elimination.cc
vn_dead_code_elimination_test.cc
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
uick/quick_compiler.cc
|
| 711d84008f5b3cda849611102118316c29a75b16 |
26-Apr-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix addpd opcode, add Quick x86 assembler test"
|
| c4013ea00d9e63533f3badeed0131bb2eb859c90 |
22-Apr-2015 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Fix addpd opcode, add Quick x86 assembler test
This patch fixes the addpd opcode that may be used by vectorizations,
and adds an assembler test for the Quick x86 assembler, currently
lightly testing addpd, subpd and mulpd.
Change-Id: I29455a86212829c75fd75737679280f167da7b5b
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
ir_graph.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/quick_assemble_x86_test.cc
|
| 24d65cce84165c2c3b0e02e09cdb92479ee4e479 |
25-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix missing dependency between GVN and other passes
The GVN may be turned off completely, or skip running when the
method is too complex. Turn off DCE in that case.
The dependent cleanup pass is not an optimization pass, so can't be
turned off that way. Check whether the GVN skipped in the gate function.
A possible follow-up is proper dependencies between passes.
Change-Id: I5b7951ecd6c74ebbfa5b23726a3d2f3ea1a23a47
b_optimizations.cc
b_optimizations.h
ir_optimization.cc
|
| 3c1c05a1e8eeff783f2854ee31bff8117ee274dd |
25-Apr-2015 |
Roland Levillain <rpl@google.com> |
Disable Quick's GVN-based dead code elimination.
Quick's GVN/DCE seems to trouble the builds.
Bug: 20572509
Change-Id: I1e315b4eee4443f04c7cb2cef953d8e4eff619ce
uick/quick_compiler.cc
|
| ae803f6efbe8378b5423c51ee3c5564cae0e6e59 |
24-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Fix and enable DCE and improve GVN/DCE cleanup."
|
| 5ea536aa4a6414db01beaf6f8bd8cb9adc5cfc92 |
20-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Remove ArtMethod* parameter from dex cache entry points.
Load the ArtMethod* using an optimized stack walk instead.
This reduces the size of the generated code.
Three of the entry points are called only from a slow-path
and the fourth (InitializeTypeAndVerifyAccess) is rare and
already slow enough that the one or two extra loads
(depending on whether we already have the ArtMethod* in a
register) are insignificant. And as we're starting to use
PC-relative addressing of the dex cache arrays (already
done by Quick for the boot image), having the ArtMethod* in
a register becomes less likely anyway.
Change-Id: Ib19b9d204e355e13bf386662a8b158178bf8ad28
uick/gen_common.cc
uick/mir_to_lir.h
|
| ad67727a492df635aa54dbe58d6c0de54431f600 |
20-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix and enable DCE and improve GVN/DCE cleanup.
When eliminating a move by renaming its source register,
check that it doesn't conflict with vreg usage by insns
between the defining insn and the move.
Improve the GVN/DCE cleanup so that it can handle cases
where GVN or DCE is individually disabled in the pass driver
but not in the disable_opt flags.
Bug: 19419671
Change-Id: I49bb67b81509f51fbaf90c6016c509962be43736
b_optimizations.h
vn_dead_code_elimination.cc
vn_dead_code_elimination.h
vn_dead_code_elimination_test.cc
ir_graph.h
ir_optimization.cc
ass_driver_me_opts.cc
uick/quick_compiler.cc
|
| 084f7d43f4dc38bfc71446b1a3b07af085d778bf |
23-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix out of temp regs in ArmMir2Lir::GenMulLong().
This fixes running out of temp registers for mul-long that
needs a temporary to store the result, i.e. when it's stored
to stack location [sp, #offset] with offset >= 1024. The bug
is currently not reproducible because ARM_R4_SUSPEND_FLAG is
off and thus we have the extra register available. However,
the code generation could be cleaned up and make use of that
extra register, so pre-emptively fix it anyway.
Bug: 20110806
Change-Id: I8362c349961dbe28fc3ec8a9299b66fd72f26779
uick/arm/int_arm.cc
|
| c91df2d6339dd4adf2da582372451df19ce2ff44 |
23-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "Revert "Quick: Rewrite type inference pass.""
Fix the type of the ArtMethod* SSA register.
Bug: 19419671
This reverts commit 1b717f63847de8762e7f7bdd6708fdfae9d24a67.
Change-Id: Ie4da3c03a0e0334a39a24718f6dc31f9255cfb53
lobal_value_numbering_test.cc
vn_dead_code_elimination.cc
vn_dead_code_elimination.h
ocal_value_numbering_test.cc
ir_dataflow.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.h
ir_optimization.cc
ass_driver_me_post_opt.cc
ost_opt_passes.h
uick/dex_file_method_inliner.cc
ype_inference.cc
ype_inference.h
ype_inference_test.cc
reg_analysis.cc
|
| 1b717f63847de8762e7f7bdd6708fdfae9d24a67 |
23-Apr-2015 |
Andreas Gampe <agampe@google.com> |
Revert "Quick: Rewrite type inference pass."
Breaks arm64, as the method register is not correctly flagged
as ref and thus 32bit.
Bug: 19419671
This reverts commit e490b01c12d33f3bd5c247b55b47e507cc9c8fab.
lobal_value_numbering_test.cc
vn_dead_code_elimination.cc
vn_dead_code_elimination.h
ocal_value_numbering_test.cc
ir_dataflow.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.h
ir_optimization.cc
ass_driver_me_post_opt.cc
ost_opt_passes.h
uick/dex_file_method_inliner.cc
ype_inference.cc
ype_inference.h
ype_inference_test.cc
reg_analysis.cc
|
| 2cebb24bfc3247d3e9be138a3350106737455918 |
22-Apr-2015 |
Mathieu Chartier <mathieuc@google.com> |
Replace NULL with nullptr
Also fixed some lines that were too long, and a few other minor
details.
Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
ataflow_iterator-inl.h
ataflow_iterator.h
ex_to_dex_compiler.cc
ir_analysis.cc
ir_dataflow.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.h
ir_optimization.cc
ass_driver.h
ass_driver_me.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/gen_common.cc
uick/gen_loadstore.cc
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/int_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/quick_cfi_test.cc
uick/quick_compiler.cc
uick/ralloc_util.cc
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
sa_transformation.cc
erification_results.cc
erified_method.cc
erified_method.h
|
| e490b01c12d33f3bd5c247b55b47e507cc9c8fab |
24-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Rewrite type inference pass.
Use method signatures, field types and types embedded in dex
insns for type inference. Perform the type inference in two
phases, first a simple pass that records all types implied
by individual insns, and then an iterative pass to propagate
those types further via phi, move, if-cc and aget/aput insns.
Bug: 19419671
Change-Id: Id38579d48a44fc5eadd13780afb6d370093056f9
lobal_value_numbering_test.cc
vn_dead_code_elimination.cc
vn_dead_code_elimination.h
ocal_value_numbering_test.cc
ir_dataflow.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.h
ir_optimization.cc
ass_driver_me_post_opt.cc
ost_opt_passes.h
uick/dex_file_method_inliner.cc
ype_inference.cc
ype_inference.h
ype_inference_test.cc
reg_analysis.cc
|
| fac10700fd99516e8a14f751fe35553021ce6982 |
22-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Remove broken Mir2Lir::LocToRegClass().
Its use in intrinsics has been bogus. In all other instances
it's been used under the assumption that the inferred type
matches the return type of associated calls. However, if the
type inference identifies a type mismatch, the assumption
doesn't hold and there isn't necessarily a valid value that
the function could reasonably return.
Bug: 19918641
Change-Id: I050934e6f9eb00427d0b888ee29ae9eeb509bb3f
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/dex_file_method_inliner.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
|
| 70bef0d8f6aa30b0da5c6ca56e1bc5729f74654b |
15-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Add compiled-methods
Add a dex2oat option for compiled-methods, a more granular filter
than compiled-classes. Add compiler-driver support for it.
Refactor dex2oat to reuse file reading.
Add a test to oat_test.
Change-Id: I78d0d040bce7738b4bb7aabe7768b5788d2587ac
uick/quick_cfi_test.cc
|
| f903680dd74e1f353dae0f4155163839a6386bf9 |
16-Apr-2015 |
Dan Albert <danalbert@google.com> |
Fix value used for shift in quick_cfi_test.
The spill mask bit should be shifted by the register number, not the
whole register mask.
Previously this test was shifting by values well over the width of the
type, which is undefined behavior.
Change-Id: Idf750be6d95b4487f8f4570b8c7ff9dba38be9f2
uick/quick_cfi_test.cc
|
| 8aec061f5e58876bcc892d8c0309bc13b5349f5c |
16-Apr-2015 |
Calin Juravle <calin@google.com> |
Merge "Fallback to quick in case of soft verification errors"
|
| f1c6d9e87cbfd27702103ccc7c7f08ce784dc872 |
13-Apr-2015 |
Calin Juravle <calin@google.com> |
Fallback to quick in case of soft verification errors
Add a regression test: using uninitialized values triggers a soft
verification error and optimizing should not crash.
Thanks to Stephen Kyle (stephenckyle@googlemail.com) for the bug report.
Bug: 19988704
Change-Id: I67174538eed853baff735694b3ae8eb34afe2a39
erified_method.cc
erified_method.h
|
| 69a503050fb8a7b3a79b2cd2cdc2d8fbc594575d |
14-Apr-2015 |
Zheng Xu <zheng.xu@arm.com> |
ARM64: Remove suspend register.
It also clean up build/remove frame used by JNI compiler and generates
stp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and
optimizing compiler.
Change-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d
uick/arm64/arm64_lir.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/quick_cfi_test_expected.inc
|
| 8dc7324da5bd0f2afd2ab558ab04882329a61fe8 |
12-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Add --include-cfi compiler option.
Decouple generation of CFI from the rest of debug symbols.
This makes it possible to generate oat with CFI but without
the rest of debug symbols.
This is in line with intention of the .eh_frame section.
The section does not have the .debug_ prefix because it
is considered somewhat different to the rest of debug symbols.
Change-Id: I32816ecd4f30ac4e0dc69d69a4993e349c737f96
uick/codegen_util.cc
uick/quick_cfi_test.cc
|
| 7f49e672bc943c49ca8af438ae4bd61b95fe364b |
12-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Remove the --gen-gdb-info compiler option.
It is never used. We generally use --include-debug-symbols instead.
Change-Id: I933495cd85ab4f7dfcf3ef3cd2d943d4b870ffeb
uick/quick_cfi_test.cc
|
| c785344b87221f5e4e6473e5b762e4e61fe65dcf |
27-Mar-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move ArtField to native
Add linear alloc. Moved ArtField to be native object. Changed image
writer to put ArtFields after the mirror section.
Savings:
2MB on low ram devices
4MB on normal devices
Total PSS measurements before (normal N5, 95s after shell start):
Image size: 7729152 bytes
23112 kB: .NonMoving
23212 kB: .NonMoving
22868 kB: .NonMoving
23072 kB: .NonMoving
22836 kB: .NonMoving
19618 kB: .Zygote
19850 kB: .Zygote
19623 kB: .Zygote
19924 kB: .Zygote
19612 kB: .Zygote
Avg: 42745.4 kB
After:
Image size: 7462912 bytes
17440 kB: .NonMoving
16776 kB: .NonMoving
16804 kB: .NonMoving
17812 kB: .NonMoving
16820 kB: .NonMoving
18788 kB: .Zygote
18856 kB: .Zygote
19064 kB: .Zygote
18841 kB: .Zygote
18629 kB: .Zygote
3499 kB: .LinearAlloc
3408 kB: .LinearAlloc
3424 kB: .LinearAlloc
3600 kB: .LinearAlloc
3436 kB: .LinearAlloc
Avg: 39439.4 kB
No reflection performance changes.
Bug: 19264997
Bug: 17643507
Change-Id: I10c73a37913332080aeb978c7c94713bdfe4fe1c
ex_to_dex_compiler.cc
ir_field_info.cc
erified_method.cc
|
| 3773cd046b1c34569f4711666788bf8a389c7857 |
10-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Remove WriteElf from Compiler
As Portable is gone, we only have one elf_writer left. It also
allows to put the decision for 32b vs 64b ELF into a central
point.
Change-Id: Iae67d06df85268b3f0ee5725abc65edd23eb2499
uick/quick_compiler.cc
uick/quick_compiler.h
|
| 5c9bb1fb851145c124d2bedc82c7effb586ab506 |
10-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Merge "Fix memory leaks in the CFI tests."
|
| 46325a0fae06ccbf5e0d7a7dd34d6cfe49226a40 |
09-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Fix memory leaks in the CFI tests.
Change-Id: Icb98e4995731c7ac5f99d1be20b447161ea4c4bd
uick/quick_cfi_test.cc
|
| 8f486f3d3f0215a468323f68d1ae30bc283e9bf6 |
10-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix indent in Mips backend
Change-Id: Ib8bc6f6bf36079e0b6e4b65ceab8af7dedc60efc
uick/mips/call_mips.cc
uick/mips/int_mips.cc
|
| 1751f38a8fca421b0d527dbaea3559b940451218 |
10-Apr-2015 |
Andreas Gampe <agampe@google.com> |
Merge "Fix GenDivRemLit() for Mips."
|
| 3b7b6cc6f26f1fffbad47a7279525198f4e22652 |
09-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: PC-relative loads from dex cache arrays on x86."
|
| 917f0866f66d3465fa41ddcf9ab09eba2fa78dd3 |
09-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Merge "Implement CFI for Optimizing."
|
| ba9715a8657e5a0b6cd201b2aa003685cacbb896 |
09-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Merge "Implement CFI for Quick."
|
| c6b4dd8980350aaf250f0185f73e9c42ec17cd57 |
07-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Implement CFI for Optimizing.
CFI is necessary for stack unwinding in gdb, lldb, and libunwind.
Change-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2
uick/codegen_util.cc
uick/lazy_debug_frame_opcode_writer.cc
uick/lazy_debug_frame_opcode_writer.h
|
| 1961b609bfefaedb71cee3651c4f931cc3e7393d |
08-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: PC-relative loads from dex cache arrays on x86.
Rewrite all PC-relative addressing on x86 and implement
PC-relative loads from dex cache arrays. Don't adjust the
base to point to the start of the method, let it point to
the anchor, i.e. the target of the "call +0" insn.
Change-Id: Ic22544a8bc0c5e49eb00a75154dc8f3ead816989
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 1576be32be4a99a1cffdaaf209a3cd67e8b2f88a |
08-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Clean up temp use counting."
|
| 87b7c52ac660119b8dea46967974b76c86d0750b |
08-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Clean up temp use counting.
For the boot image on arm64 and x86-64 we're using true
PC-relative addressing, so pc_rel_temp_ is nullptr and
CanUsePcRelDexCacheArrayLoad() returns true, but we're not
actually using the ArtMethod* so fix the AnalyzeMIR() to
take it into account.
Also don't count intrinsic invokes towards ArtMethod* uses.
To avoid repeated method inliner inquiries about whether a
method is intrinsic or special (requiring lock acquisition),
cache that information in MirMethodLoweringInfo. As part of
that cleanup, take quickened invokes into account for
suspend check elimination.
Change-Id: I5b4ec124221c0db1314c8e72675976c110ebe7ca
b_optimizations.h
ir_graph.h
ir_method_info.cc
ir_method_info.h
ir_optimization.cc
ir_optimization_test.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/ralloc_util.cc
|
| 1109fb3cacc8bb667979780c2b4b12ce5bb64549 |
07-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Implement CFI for Quick.
CFI is necessary for stack unwinding in gdb, lldb, and libunwind.
Change-Id: Ic3b84c9dc91c4bae80e27cda02190f3274e95ae8
ir_graph.h
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/arm64/int_arm64.cc
uick/codegen_util.cc
uick/lazy_debug_frame_opcode_writer.cc
uick/lazy_debug_frame_opcode_writer.h
uick/mips/call_mips.cc
uick/mips/target_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/quick_cfi_test.cc
uick/quick_cfi_test_expected.inc
uick/quick_compiler.cc
uick/quick_compiler.h
uick/x86/call_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| cde8e5da3e774a2494b051043130c0495eca09ef |
08-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Merge "Remove the old CFI infrastructure."
|
| c7399c82c27f85a2df2653e1eb8c0b60f2cfd934 |
08-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Remove LLVM cruft
Change-Id: I133ebed6101bf12a0642ed71e13f332c0c4f14e7
ir_graph.cc
|
| 7fa6e279dfda5b2f21e4c234f562a49a5fe5d218 |
07-Apr-2015 |
Douglas Leung <douglas.leung@imgtec.com> |
Fix GenDivRemLit() for Mips.
This bug was reported by Ingenic where the result is incorrect if
we divide a number by an unsigned 16-bit constant with its
MSB bit (bit 15) set.
Change-Id: I53d2599918cc47b1a9809160310716dca67ef243
uick/mips/int_mips.cc
|
| 40f65560b5ecd79aeaadc16b03834d11aea1e0a5 |
08-Apr-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix 64-bit ELF file support"
|
| 3c54b0023fca579aae006dfa607fb14de5846c42 |
08-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix 64-bit ELF file support
The API wasn't cross-compile-safe, 32-bit patchoat would fail for
negative delta applied to a 64-bit ELF file.
Add 64-bit ELF file output to the compilers, behind a flag, currently
off by default (preserving current behavior).
Bug: 20095017
Change-Id: I2cde7b4c7cc83413c76692d7b745868d644a604c
uick/quick_compiler.cc
|
| 8c57831b2b07185ee1986b9af68a351e1ca584c3 |
07-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Remove the old CFI infrastructure.
Change-Id: I12a17a8a1c39ffccaa499c328ebac36e4d74dc4e
uick/codegen_util.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| cc23481b66fd1f2b459d82da4852073e32f033aa |
07-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Promote pointer to dex cache arrays on arm.
Do the use-count analysis on temps (ArtMethod* and the new
PC-relative temp) in Mir2Lir, rather than MIRGraph. MIRGraph
isn't really supposed to know how the ArtMethod* is used by
the backend.
Change-Id: Iaf56a46ae203eca86281b02b54f39a80fe5cc2dd
ir_dataflow.cc
ir_graph.h
ir_optimization.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
|
| e5c76c515a481074aaa6b869aa16490a47ba98bc |
06-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
PC-relative loads from dex cache arrays for arm.
Change-Id: Ic25df4b51a901ff1d2ca356b5eec71d4acc5d9b7
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
|
| 3477307fdf93a1ef9a80d4e096125705c47e8024 |
07-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Use PC-relative dex cache array loads for SGET/SPUT.
Change-Id: I890284b73f69120ada5cf9b9ef4a717af3273cd2
uick/gen_common.cc
uick/mir_to_lir.h
|
| 65b798ea10dd716c1bb3dda029f9bf255435af72 |
06-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Enable more Clang warnings
Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
vn_dead_code_elimination.cc
uick/arm64/utility_arm64.cc
uick/mips/utility_mips.cc
|
| e8aae00fa400efbb8f998a5dbf68eb42810889c1 |
06-Apr-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Add Clang's -Wused-but-marked-unused"
|
| ca71458862be8505330b7fd5649a062f31d143dc |
04-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Add Clang's -Wused-but-marked-unused
Add detection of wrong unused annotations. Fix our codebase.
Change-Id: I85cc20f2eac71c1ec6c5c7cd6efb08454a629634
ocal_value_numbering.cc
|
| b207e1473dda1730604a28db2b4fa52f2998aeae |
02-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Pass linker patches around as const.
Change-Id: I0eabd713d29475db9eb6e186f331dbfb00e0cf6b
uick/codegen_util.cc
|
| e8a339e5058962805c2b428fedb1d6ede5aeb501 |
02-Apr-2015 |
David Srbecky <dsrbecky@google.com> |
Merge "Write .debug_line section using the new DWARF library."
|
| dc56cc509d8e1718ad321f7a91661dbe85ec8cef |
27-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
PC-relative loads from dex cache arrays for x86-64.
Change-Id: I6cfe22c7e69512b3c0f95b073aaa572db74ec189
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 6f7158927fee233255f8e96719c374694b10cad3 |
30-Mar-2015 |
David Srbecky <dsrbecky@google.com> |
Write .debug_line section using the new DWARF library.
Also simplify dex to java mapping and handle mapping
in prologues and epilogues.
Change-Id: I410f06024580f2a8788f2c93fe9bca132805029a
ompiler_enums.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/codegen_util.cc
uick/mips/call_mips.cc
uick/mir_to_lir.cc
uick/x86/call_x86.cc
|
| ef3456f872539df65c4c88ca346713f74366d803 |
31-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Cortex-A53 Erratum 843419 workaround in OatWriter."
|
| c74658b6cf6af53480b3fa07950dcc0a9231ef6a |
31-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Cortex-A53 Erratum 843419 workaround in OatWriter.
Bug: 19983916
Change-Id: I572248d035200bb04f74eb3ae065e862572628a0
uick/arm64/int_arm64.cc
|
| f93c6fe65c4c5e601cce467e87bbe71a87c5bac0 |
31-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Fixed layout for dex caches in boot image."
|
| 20f85597828194c12be10d3a927999def066555e |
19-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Fixed layout for dex caches in boot image.
Define a fixed layout for dex cache arrays (type, method,
string and field arrays) for dex caches in the boot image.
This gives those arrays fixed offsets from the boot image
code and allows PC-relative addressing of their elements.
Use the PC-relative load on arm64 for relevant instructions,
i.e. invoke-static, invoke-direct, const-string,
const-class, check-cast and instance-of. This reduces the
arm64 boot.oat on Nexus 9 by 1.1MiB.
This CL provides the infrastructure and shows on the arm64
the gains that we can achieve by having fixed dex cache
arrays' layout. To fully use this for the boot images, we
need to implement the PC-relative addressing for other
architectures. To achieve similar gains for apps, we need
to move the dex cache arrays to a .bss section of the oat
file. These changes will be implemented in subsequent CLs.
(Also remove some compiler_driver.h dependencies to reduce
incremental build times.)
Change-Id: Ib1859fa4452d01d983fd92ae22b611f45a85d69b
ir_field_info.cc
ir_graph.cc
ir_method_info.cc
uick/arm/call_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/local_optimizations.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
uick/x86/call_x86.cc
|
| 4585f876eb5dfb936bd0d6cb6acd78a1f2182ba6 |
28-Mar-2015 |
Andreas Gampe <agampe@google.com> |
ART: Some runtime cleanup
Use an enum for the compiler-callback mode.
Refactor and remove some unnecessary includes in runtime.h.
Change-Id: If2245fa470171311b8e05b677cf6bb28f209585a
uick_compiler_callbacks.h
|
| 86787d0bc2c5ad3b9c3b880b0fe2325d2b8bd672 |
28-Mar-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: PathClassLoader for compiler"
|
| 81c6f8db12b203878a7d72444ead2bc7cf5c47ad |
26-Mar-2015 |
Andreas Gampe <agampe@google.com> |
ART: PathClassLoader for compiler
Use an actual PathClassLoader when compiling apps, instead of a
side structure and cutout.
This CL sets up a minimal object 'cluster' that recreates the Java
side of a regular ClassLoader such that the Class-Linker will
recognize it and use the internal native fast-path.
This CL removes the now unnecessary compile-time-classpath and
replaces it with a single 'compiling-the-boot-image' flag in the
compiler callbacks.
Note: This functionality is *only* intended for the compiler, as
the objects have not been completely initialized.
Bug: 19781184
Change-Id: I7f36af12dd7852d21281110a25c119e8c0669c1d
uick_compiler_callbacks.h
|
| 1095793154d2ff33323ba9edaa4f83373bdb6c8e |
24-Mar-2015 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
[MIPS] Refactoring code for quick compiler
Code from compiler/dex/quick/mips64 is merged with code
in mips folder.
Change-Id: I785983c21549141306484647da86a0bb4815daaa
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mips64/assemble_mips64.cc
uick/mips64/backend_mips64.h
uick/mips64/call_mips64.cc
uick/mips64/codegen_mips64.h
uick/mips64/fp_mips64.cc
uick/mips64/int_mips64.cc
uick/mips64/mips64_lir.h
uick/mips64/target_mips64.cc
uick/mips64/utility_mips64.cc
uick/quick_compiler.cc
|
| 356a1811f2f79d98194475fdbfb5f6b7768455b5 |
27-Mar-2015 |
Pavel Vyssotski <pavel.n.vyssotski@intel.com> |
Quick: Finding upper half of kMirOpCheckPart2 should passthough empty blocks
Mir2Lir::InitReferenceVRegs trying to find throwing instruction for
kMirOpCheckPart2 should traverse possible empty blocks which compiler
optimizations could generate between them.
Change-Id: I2ab29dd36635fd4c4ef2dd81b51e571e206775e6
Signed-off-by: Pavel Vyssotski <pavel.n.vyssotski@intel.com>
uick/codegen_util.cc
|
| 410f5cfe4ff70bc8a151216afae4e204f51aff37 |
25-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Fix "select" pattern to update data used for GC maps."
|
| 6e07183e822a32856da9eb60006989496e06a9cc |
25-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix "select" pattern to update data used for GC maps.
Follow-up to
https://android-review.googlesource.com/143222
Change-Id: I1c12af9a19f76e64fd209f6cc2eaec5587b3083b
ir_optimization.cc
uick/codegen_util.cc
uick/mir_to_lir.h
|
| da4d79bc9a4aeb9da7c6259ce4c9c1c3bf545eb8 |
24-Mar-2015 |
Roland Levillain <rpl@google.com> |
Unify ART's various implementations of bit_cast.
ART had several implementations of art::bit_cast:
1. one in runtime/base/casts.h, declared as:
template <class Dest, class Source>
inline Dest bit_cast(const Source& source);
2. another one in runtime/utils.h, declared as:
template<typename U, typename V>
static inline V bit_cast(U in);
3. and a third local version, in runtime/memory_region.h,
similar to the previous one:
template<typename Source, typename Destination>
static Destination MemoryRegion::local_bit_cast(Source in);
This CL removes versions 2. and 3. and changes their callers
to use 1. instead. That version was chosen over the others
as:
- it was the oldest one in the code base; and
- its syntax was closer to the standard C++ cast operators,
as it supports the following use:
bit_cast<Destination>(source)
since `Source' can be deduced from `source'.
Change-Id: I7334fd5d55bf0b8a0c52cb33cfbae6894ff83633
uick/arm64/fp_arm64.cc
uick/gen_common.cc
|
| f6737f7ed741b15cfd60c2530dab69f897540735 |
23-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Clean up Mir2Lir codegen.
Clean up WrapPointer()/UnwrapPointer() and OpPcRelLoad().
Change-Id: I1a91f01e1e779599c77f3f6efcac2a6ad34629cf
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/mips/assemble_mips.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips64/assemble_mips64.cc
uick/mips64/codegen_mips64.h
uick/mips64/int_mips64.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 274395fe6649d83d723c4b912a46291b2987efd6 |
24-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Create GC map based on compiler data."
|
| ea379885b01d6985cff09d0efd438d03de5f9fa1 |
21-Mar-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Add Mips32r6 backend support"
|
| cd8f6377821370cb471fb21ae095dfaa204e4410 |
21-Mar-2015 |
Mathieu Chartier <mathieuc@google.com> |
Remove some spammy logging
Did not provide useful info and or was redundant.
Change-Id: I42da705debc43460cdd3fdf16e9e9ceb2c137001
ass_manager.cc
|
| 027f0ff64c2512b9a5f1f54f3fea1bec481eb0f5 |
28-Feb-2015 |
Douglas Leung <douglas.leung@imgtec.com> |
ART: Add Mips32r6 backend support
Add Mips32r6 compiler support.
Don't use deprecated Mips32r2 instructions if running in Mips32r6
mode.
Change-Id: I54e689aa8c026ccb75c4af515aa2794f471c9f67
uick/mips/assemble_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
|
| 767c752fddc64e280dba507457e4f06002b5f678 |
20-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Create GC map based on compiler data.
The Quick compiler and verifier sometimes disagree on dalvik
register types (fp/core/ref) for 0/null constants and merged
registers involving 0/null constants. Since the verifier is
more lenient it can mark a register as a reference for GC
where Quick considers it a floating point register or a dead
register (which would have a ref/fp conflict if not dead).
If the compiler used an fp register to hold the zero value,
the core register or stack location used by GC based on the
verifier data can hold an invalid value.
Previously, as a workaround we stored the fp zero value also
in the stack location or core register where GC would look
for it. This wasn't precise and may have missed some cases.
To fix this properly, we now generate GC maps based on the
compiler's notion of references if register promotion is
enabled.
Bug: https://code.google.com/p/android/issues/detail?id=147187
Change-Id: Id3a2f863b16bdb8969df7004c868773084aec421
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_loadstore.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
|
| 0b40ecf156e309aa17c72a28cd1b0237dbfb8746 |
20-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Clean up slow paths.
Change-Id: I278d42be77b02778c4a419ae9024b37929915b64
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips64/call_mips64.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/int_x86.cc
|
| d7cbf8a6629942e7bd315ffae7e1c77b082f3e11 |
19-Mar-2015 |
Mathieu Chartier <mathieuc@google.com> |
Change RETURN_VOID_BARRIER to RETURN_VOID_NO_BARRIER
We want to default to having a barrier for the case where we don't
dex to dex.
Bug: 19762303
Change-Id: I60348d89eaf0b9e1e480298afcecbb5f52e8661b
ex_to_dex_compiler.cc
ir_analysis.cc
ir_dataflow.cc
uick/mir_to_lir.cc
uick/quick_compiler.cc
|
| 22fe45de11ed7afdf21400d2de3abd23f3a62800 |
18-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Eliminate check-cast guaranteed by instance-of.
Eliminate check-cast if the result of an instance-of with
the very same type on the same value is used to branch to
the check-cast's block or a dominator of it.
Note that there already exists a verifier-based elimination
of check-cast but it excludes check-cast on interfaces. This
new optimization works for interface types and, since it's
GVN-based, it can better recognize when the same reference
is used for instance-of and check-cast.
Change-Id: Ib315199805099d1cb0534bb4a90dc51baa409685
ompiler_enums.h
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
vn_dead_code_elimination.cc
ocal_value_numbering.cc
ir_graph.h
ir_optimization.cc
uick/gen_common.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
|
| 216eaa2927f424821a03d7c4c6bf701fdb48e865 |
17-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Fall back to Quick when Optimizing cannot compile.
Currently applies when seeing unresolved types/methods/fields,
and methods with try/catch.
Change-Id: I93b12d440b39f0b9faf98f08f2bfddedfeff7182
ir_graph.cc
ir_graph.h
ass_driver_me_opts.cc
ass_driver_me_opts.h
uick/quick_compiler.cc
|
| f2674eac59c02dc2046c7080a799c03ccf66384d |
16-Mar-2015 |
Andrew Hsieh <andrewhsieh@google.com> |
Fixed maybe used uninitialized
GCC 4.9 found that ops[1].op maybe uninitialized in
ArmMir2Lir::GetEasyMultiplyTwoOps, but used unconditionally
in ArmMir2Lir::GenEasyMultiplyTwoOps
Change-Id: Icf8fdf3b888bd54ccb252e95637774889c7a0f9d
uick/arm/int_arm.cc
|
| 921d6eb3c4e12a2000fe490c4e58d0e6e0628b90 |
14-Mar-2015 |
Mathieu Chartier <mathieuc@google.com> |
Fix 32 bit loads of 64 bit direct code pointers
Fixes 64 bit problems for JIT since the JIT code cache isn't always
in the low 2GB.
(cherry picked from commit 0d2ac187be10838c008e6aaa03e5e55014e9087e)
Change-Id: Ifd37d6a86166a91be1b258da7329c888fd82e4b9
uick/arm64/call_arm64.cc
uick/mips64/call_mips64.cc
uick/x86/call_x86.cc
|
| 15b9d5274399736ac09705f0507df24fac4f00c1 |
12-Mar-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
API change in StackVisitor::GetVReg*.
- Remove GetVReg() and SetVReg() that were expecting to always succeed.
- Change Quick-only methods to take a FromQuickCode suffix.
- Change deopt to use dead values when GetVReg does not succeed:
the optimizing compiler will not have a location for uninitialized
Dex registers and potentially dead registers.
Change-Id: Ida05773a97aff8aa69e0caf42ea961f80f854b77
uick/ralloc_util.cc
|
| 091d238936809f6668ca6b7606c62bc224add430 |
06-Mar-2015 |
Mathieu Chartier <mathieuc@google.com> |
Fix incompatible class change error for JIT stress mode
There was a problem with miranda methods, when we would dequicken to
one of these, it wouldn't resolve as virtual during the method
lowering resolve. The solution is to try resolving as interface if we
fail to resolve as virtual.
Fixed a bug in dequickening where unreachable register lines with
quick invokes would cause CHECK failuers. In this case we punt to the
interpreter (test 435-try-*).
Added test regression test. Example failure:
java.lang.IncompatibleClassChangeError: The method
'void Main$TheInterface.m()' was expected to be of type virtual but
instead was found to be of type interface (declaration of
'java.lang.reflect.ArtMethod' appears in
out/host/linux-x86/framework/core-libart-hostdex.jar)
at Main.DoStuff(Main.java:37)
at Main.main(Main.java:44)
Bug: 17950037
Change-Id: I39c32cc8849bf02032a4f61a7ce57462b7fcac75
ex_to_dex_compiler.cc
ir_method_info.cc
erified_method.cc
erified_method.h
|
| 9c8d96163670c0c615daa17a55b3b91b937c12ba |
10-Mar-2015 |
Mathieu Chartier <mathieuc@google.com> |
Fix dex2dex logic
There was a bug in the dex2dex logic where would only dex2dex if
IsCandidateForCompilation was true or method verifier had check casts.
The bug was caused by not adding verification results, which caused
verification_results_->GetVerifiedMethod to not have verified methods
in most cases for interpreter-only and verify-none compilation.
Caffeinemark interpret-only before:
Sieve score = 1184
Loop score = 630
Logic score = 3519
String score = 1532
Float score = 882
Method score = 686
Overall score = 1159
After:
Sieve score = 2820
Loop score = 1942
Logic score = 4694
String score = 1679
Float score = 2288
Method score = 1294
Overall score = 2244
Bug: 17950037
Change-Id: I535ab8784b434b0a8e3f66e3ab4936d10a1b04bf
erification_results.cc
|
| 6ad40cd6f28c5d3a75929a20eb18da32ef0ab421 |
10-Mar-2015 |
Goran Jakovljevic <goran.jakovljevic@imgtec.com> |
[MIPS64] Fix GenInlinedPeek and GenInlinedPoke functions.
Change-Id: I4994bb2f9075cb3b6488e5a5b88dbed17b80595a
uick/mips64/int_mips64.cc
|
| 9b34b244ecddd8a35c922ed87bc3df0ca4db0282 |
09-Mar-2015 |
Mathieu Chartier <mathieuc@google.com> |
Trim arenas for JIT
Moved arena pool into the runtime. Added arena trimming to arena
pool. When called, this madvises the used memory.
Changed the JIT compiler to trim arenas after compilation. Changed
the arena mmap name to dalvik-LinearAlloc.
Native PSS before:
80353 kB: Native
80775 kB: Native
78116 kB: Native
After:
73357 kB: Native
70181 kB: Native
70306 kB: Native
Bug: 17950037
Bug: 17643507
Bug: 19264997
Change-Id: I63e7a898fd6e909c2c677fa57b5917a7b1398930
uick/quick_compiler.cc
|
| 6ea651f0f4c7de4580beb2e887d86802c1ae0738 |
24-Feb-2015 |
Maja Gagic <maja.gagic@imgtec.com> |
Initial support for quick compiler on MIPS64r6.
Change-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips64/assemble_mips64.cc
uick/mips64/backend_mips64.h
uick/mips64/call_mips64.cc
uick/mips64/codegen_mips64.h
uick/mips64/fp_mips64.cc
uick/mips64/int_mips64.cc
uick/mips64/mips64_lir.h
uick/mips64/target_mips64.cc
uick/mips64/utility_mips64.cc
uick/quick_compiler.cc
uick/ralloc_util.cc
|
| 66b26662ad0c52c648c9b5ea4a99149091e842b4 |
05-Mar-2015 |
Bill Buzbee <buzbee@google.com> |
Merge "ART: AddVectorReduce should store result in memory carefully"
|
| d37f91902048b23ad5fe5b20aba0ebc92e0b4896 |
04-Mar-2015 |
Andreas Gampe <agampe@google.com> |
ART: Do not produce CFI when not asked for
Insignificant time savings on the host, but also reduces native
allocation size.
Change-Id: Iea3d335e5375a0076306059d094e5b994e24b9e6
uick/codegen_util.cc
|
| 085b733d15ec09afa27b85358acb89d9bc02e843 |
24-Feb-2015 |
Maxim Kazantsev <maxim.kazantsev@intel.com> |
ART: AddVectorReduce should store result in memory carefully
When generating AddVectorReduce, in some cirsumstances we
add value reduced from vector directly to memory. We must
ensure that local LIR optimizations are aware about it.
Change-Id: I8fe19939f67dcd184b08f63026b0da18007d34b8
uick/x86/target_x86.cc
|
| e15ea086439b41a805d164d2beb07b4ba96aaa97 |
10-Feb-2015 |
Hiroshi Yamauchi <yamauchi@google.com> |
Reserve bits in the lock word for read barriers.
This prepares for the CC collector to use the standard object header
model by storing the read barrier state in the lock word.
Bug: 19355854
Bug: 12687968
Change-Id: Ia7585662dd2cebf0479a3e74f734afe5059fb70f
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
|
| 8376830b762fbe974a9ddd2d43c640655883c7ab |
27-Feb-2015 |
buzbee <buzbee@google.com> |
Merge "Handle another untyped dex CONST issue"
|
| 335c55527846fc9019246163be0ac1ac02e95057 |
04-Feb-2015 |
Ningsheng Jian <ningsheng.jian@arm.com> |
ARM: Fix LIR flags in encoding map.
Also correct memory reference type for PC relative load.
Change-Id: I7a5258f2ed718448dc3e6e7fda6569b3f0c2fe46
uick/arm/assemble_arm.cc
uick/arm/int_arm.cc
uick/arm64/assemble_arm64.cc
|
| 71ef04481d1bc1b8381f8e997a0f0f9988419e34 |
26-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Change already inline error to warning
There is a race condition in the JIT where the JIT and another
running thread can both verify the same method at the same time.
This causes the inline method to be added twice and the LOG(ERROR)
was causing occasional test failures.
Bug: 17950037
Bug: 18713034
Change-Id: I7f94384106ca5c621a5cf7d2ba36910d923d110c
uick/dex_file_method_inliner.cc
|
| 4f9bbe2a654165aedab62041101ae41d54c04e39 |
26-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Fix JIT for vmdebug test 99"
|
| 2d873b67f97c31da984c17ccbd94441c6264cafc |
20-Feb-2015 |
Nikola Veljkovic <Nikola.Veljkovic@imgtec.com> |
[MIPS] Fix mips32 trampoline problem.
Reserve argument slots (for $a0-$a3) on the stack in the
InvokeTrampoline() function, for entrypoints that contain direct
reference to native implementation. Called function may use this
space to store $a0-$a3 regs.
This fixes the Settings app crash on mips32, when navigating to:
Settings->Apps->(swipe) On SD card.
Change-Id: If53ce822fd3ef6ef9839c89b556f76fac0792190
uick/mips/utility_mips.cc
|
| c0d5f89d99c55ab63d6757fbd71dbfe95d347c1f |
25-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Fix JIT for vmdebug test 99
Test was flaky due to JIT re-compiliation after deoptimization
resulting in some invalid PC offsets.
Bug: 17950037
Change-Id: I276c84c918579259ce47ef873892c3c5dcf0c977
erification_results.cc
|
| f58c11c92df59f7ec7d9f2dfadc7e400b790883d |
14-Feb-2015 |
Douglas Leung <douglas.leung@imgtec.com> |
Fix argument register allocation for mips32.
Change-Id: Ic21b0371d7cafb9b67217b92bb2edb735a43d1b0
uick/gen_invoke.cc
|
| 7e6a233f5d2268de0bf1600eed77c05753615f52 |
24-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Delete bad DCHECK
The declaring class of a super field could be in a different dex file.
Fixes sdk build.
Change-Id: I8258d64eeff6539afb52448595f5a6ec4c71a6bc
uick/gen_common.cc
|
| e5f13e57ff8fa36342beb33830b3ec5942a61cca |
24-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Revert "Revert "Add JIT""
Added missing EntryPointToCodePointer.
This reverts commit a5ca888d715cd0c6c421313211caa1928be3e399.
Change-Id: Ia74df0ef3a7babbdcb0466fd24da28e304e3f5af
lobal_value_numbering_test.cc
vn_dead_code_elimination_test.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_analysis.cc
ir_dataflow.cc
ir_field_info.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.cc
ir_method_info.h
ir_optimization.cc
ir_optimization_test.cc
uick/dex_file_method_inliner.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.cc
uick/quick_compiler.cc
erification_results.cc
erified_method.cc
erified_method.h
reg_analysis.cc
|
| a5ca888d715cd0c6c421313211caa1928be3e399 |
24-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Add JIT"
Sorry, run-test crashes on target:
0-05 12:15:51.633 I/DEBUG (27995): Abort message: 'art/runtime/mirror/art_method.cc:349] Check failed: PcIsWithinQuickCode(reinterpret_cast<uintptr_t>(code), pc) java.lang.Throwable java.lang.Throwable.fillInStackTrace() pc=71e3366b code=0x71e3362d size=ad000000'
10-05 12:15:51.633 I/DEBUG (27995): r0 00000000 r1 0000542b r2 00000006 r3 00000000
10-05 12:15:51.633 I/DEBUG (27995): r4 00000006 r5 b6f9addc r6 00000002 r7 0000010c
10-05 12:15:51.633 I/DEBUG (27995): r8 b63fe1e8 r9 be8e1418 sl b6427400 fp b63fcce0
10-05 12:15:51.633 I/DEBUG (27995): ip 0000542b sp be8e1358 lr b6e9a27b pc b6e9c280 cpsr 40070010
10-05 12:15:51.633 I/DEBUG (27995):
Bug: 17950037
This reverts commit 2535abe7d1fcdd0e6aca782b1f1932a703ed50a4.
Change-Id: I6f88849bc6f2befed0c0aaa0b7b2a08c967a83c3
lobal_value_numbering_test.cc
vn_dead_code_elimination_test.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_analysis.cc
ir_dataflow.cc
ir_field_info.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.cc
ir_method_info.h
ir_optimization.cc
ir_optimization_test.cc
uick/dex_file_method_inliner.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.cc
uick/quick_compiler.cc
erification_results.cc
erified_method.cc
erified_method.h
reg_analysis.cc
|
| 2535abe7d1fcdd0e6aca782b1f1932a703ed50a4 |
17-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Add JIT
Currently disabled by default unless -Xjit is passed in.
The proposed JIT is a method JIT which works by utilizing interpreter
instrumentation to request compilation of hot methods async during
runtime.
JIT options:
-Xjit / -Xnojit
-Xjitcodecachesize:N
-Xjitthreshold:integervalue
The JIT has a shared copy of a compiler driver which is accessed
by worker threads to compile individual methods.
Added JIT code cache and data cache, currently sized at 2 MB
capacity by default. Most apps will only fill a small fraction of
this cache however.
Added support to the compiler for compiling interpreter quickened
byte codes.
Added test target ART_TEST_JIT=TRUE and --jit for run-test.
TODO:
Clean up code cache.
Delete compiled methods after they are added to code cache.
Add more optimizations related to runtime checks e.g. direct pointers
for invokes.
Add method recompilation.
Move instrumentation to DexFile to improve performance and reduce
memory usage.
Bug: 17950037
Change-Id: Ifa5b2684a2d5059ec5a5210733900aafa3c51bca
lobal_value_numbering_test.cc
vn_dead_code_elimination_test.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_analysis.cc
ir_dataflow.cc
ir_field_info.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.cc
ir_method_info.h
ir_optimization.cc
ir_optimization_test.cc
uick/dex_file_method_inliner.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.cc
uick/quick_compiler.cc
erification_results.cc
erified_method.cc
erified_method.h
reg_analysis.cc
|
| 4de86d0987139153ae0e2d50dbbefde2ce34ee87 |
20-Feb-2015 |
buzbee <buzbee@google.com> |
Handle another untyped dex CONST issue
The lack of typing for dex byte code instructions causes problems
for the Quick compiler's register allocation scheme. In Quick,
Dalvik virtual registers can have multiple "home locations" depending
on type. Because CONST operators are untyped and their result can
be used in multiple type contexts, the code generator must ensure
that any CONST #0 definitions of potential floating point uses
are also flushed to the associated reference view for the vreg
(if it exists) to support GC. Previously, this issue was believed
to have been fixed by c/255389 (see internal b/7250540).
However, the earlier fix failed to account for const definitions
propogating to other vregs via MOVE. This CL addresses that case by
applying the earlier workaround to MOVE operators.
Note that there are a few other places where we attempt to deal
with this general problem. First, the verifier will disable
compilation for dex code sequences which have type mismatches on non-const
operations. Second, during vreg analysis we detect type mismatches on
Phi insertion, and disable register promotion if there is a mismatch.
b.android.com/147187
Change-Id: I70f27a59e6f84a89777db91ceacaa94a42f5e952
uick/mir_to_lir.cc
|
| 55693289c9f6c616e195e7b4ea3fe8e10c0681a6 |
20-Jan-2015 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
ART: Some conditions should be stricter in GenInlinedMinMax()
When we inline Min or Max intrinsics of long data type in 32-bit
mode we should care about register overlap cases. I.e. when
result and operands share partially or entirely same registers.
We consider three cases:
a) If result is between two operands, then we fail to inline
because implementation tends to be overcomplicated.
b) Since we always copy the first operand into result, we
should check whether result and the second operand share
same registers. If so, we swap the second with the first one.
c) If operands share same registers then we just copy the
first operand into result and stop.
The algorithm requires many registers. Therefore, we try to
reuse some of them. This also needs check for overlap.
Change-Id: I1e327acedfdc63d9b434b21b41d75bb86c41f1d0
uick/x86/int_x86.cc
|
| d7a5e553e0ee0a2090c719312f7d24dae3746cec |
20-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Fix core spill mask for x86 special suspend.
Bug: 19445246
Change-Id: I7dd734e64a4bfa5980fa1be9903e3fd0c2be3749
uick/x86/call_x86.cc
|
| 6aa7fe620a95b4404a4fed451e46ebf0cdd66204 |
19-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Replace a few std::vector with ArenaVector in Mir2Lir."
|
| 80b96d1a76790527f72a660ac03d9c215eed17ce |
19-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Replace a few std::vector with ArenaVector in Mir2Lir.
Change-Id: I7867d60afc60f57cdbbfd312f02883854d65c805
uick/codegen_util.cc
uick/mir_to_lir.h
uick/x86/target_x86.cc
|
| 6561551f094f79ce569160b29131b07be7aa3363 |
19-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Move arenas into runtime"
|
| b666f4805c8ae707ea6fd7f6c7f375e0b000dba8 |
18-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move arenas into runtime
Moved arena pool into the runtime.
Motivation:
Allow GC to use arena allocators, recycle arena pool for linear alloc.
Bug: 19264997
Change-Id: I8ddbb6d55ee923a980b28fb656c758c5d7697c2f
ompiler_ir.h
lobal_value_numbering.h
vn_dead_code_elimination.h
ocal_value_numbering.h
ir_analysis.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
uick/arm/codegen_arm.h
uick/mir_to_lir.h
uick/resource_mask.cc
sa_transformation.cc
|
| 6ce3eba0f2e6e505ed408cdc40d213c8a512238d |
16-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Add suspend checks to special methods.
Generate suspend checks at the beginning of special methods.
If we need to call to runtime, go to the slow path where we
create a simplified but valid frame, spill all arguments,
call art_quick_test_suspend, restore necessary arguments and
return back to the fast path. This keeps the fast path
overhead to a minimum.
Bug: 19245639
Change-Id: I3de5aee783943941322a49c4cf2c4c94411dbaa2
ir_graph.cc
ir_graph.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| 2ee8837c49680fa0c928fb5d5fc6ef7ae6532eea |
19-Feb-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Templatize IsInt & IsUint"
|
| ab1eb0d1d047e3478ebb891e5259d2f1d1dd78bd |
14-Feb-2015 |
Andreas Gampe <agampe@google.com> |
ART: Templatize IsInt & IsUint
Ensure that things are used correctly.
Change-Id: I76f082b32dcee28bbfb4c519daa401ac595873b3
ex_to_dex_compiler.cc
uick/mips/utility_mips.cc
|
| 698e4a8942b6f6005dd247a73347f8086c8e7e6e |
18-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Distinguish FP and integral constants in LVN."
|
| a5c81189a5075c53d649135e0417fc075eeead5a |
18-Feb-2015 |
Bill Buzbee <buzbee@google.com> |
Merge "ART: Fix InsertCaseLabel to return boundary_lir always"
|
| 3dbce6f822cc9fa49505adde0a556fd67996268e |
18-Feb-2015 |
Bill Buzbee <buzbee@google.com> |
Merge "ART: Promoted register may be wrong after the load of zero fp constant"
|
| 22c7f5bc70d0c8f3e5915b7fb98c9f9930cfdff0 |
18-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Distinguish FP and integral constants in LVN.
Change-Id: I31a58ff19fb95a2f56420359e50332c1dce6cbc7
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
|
| 37e05bf384e21a031455c00b5fec668c187acd8d |
18-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Disable DCE until we fix FP/Core reg mismatches.
GVN and TypeInference can miss some FP/Core register
mismatch:
const v0, #X ; marked as float
invoke-virtual v0, void foo(float)
const v0, #X ; marked as core
aput v0, v1, v2 ; float[] not used
The second const is eliminated by the DCE because it writes
the same value to the same dalvik reg. We replace the SSA
register name defined by the first const and used by the
invoke-virtual with the one defined by the second const.
When we generate code for the invoke-virtual, we get a core
location and may need a temporary to set up the FP argument
and we may not have an available temporary.
This may affect the bug below (more investigation needed).
Bug: 19419671
Change-Id: I44abd390706b980c346b36c9828a3bcb4e96726d
uick/quick_compiler.cc
|
| 0d5fd49f222541d0f8857646bbc51a79ef0439f9 |
11-Feb-2015 |
Vladimir <vladimir.a.ivanov@intel.com> |
ART: Promoted register may be wrong after the load of zero fp constant
Because of Dalvik byte code's lack of immediate typing,
the same vreg may be used in core, ref and fp operations.
To properly support GC, we must ensure that if a constant zero is loaded
into a fp view of a vreg, it must also be loaded into the core/ref view.
The code that was responsible for ensuring this failed to handle the case
of a vreg having a non-promoted fp view and a promoted core/ref view.
Change-Id: If77295aa93317e749ceacc8c1dd9e582122c368f
Signed-off-by: Vladimir <vladimir.a.ivanov@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/gen_loadstore.cc
|
| afba696823ec7c019de72f17cd198e91edd3bf4f |
17-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Dead code elimination based on GVN results."
|
| 7a01dc2107d4255b445c32867d15d45fcebb3acd |
02-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Dead code elimination based on GVN results.
Change-Id: I5b77411a8f088f0b561da14b123cf6b0501c9db5
b_optimizations.h
ex_flags.h
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
vn_dead_code_elimination.cc
vn_dead_code_elimination.h
vn_dead_code_elimination_test.cc
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_dataflow.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_optimization.cc
ass_driver_me_opts.cc
uick/quick_compiler.cc
|
| d532f006f621b65d2a390f9fd946acb39dfd2e8d |
13-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Add tests for wide constants in LVN.
Follow up to
https://android-review.googlesource.com/132210
Change-Id: I4e29483fb9931ae5670539954b69cdb078843e72
ocal_value_numbering_test.cc
|
| bce889940f10319bf67bdc5630c84dd7f6e5c246 |
13-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Clean up Scoped-/ArenaAlocator array allocations."
|
| e4fcc5ba2284c201c022b52d27f7a1201d696324 |
13-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Clean up Scoped-/ArenaAlocator array allocations.
Change-Id: Id718f8a4450adf1608306286fa4e6b9194022532
lobal_value_numbering.h
lobal_value_numbering_test.cc
ocal_value_numbering_test.cc
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ir_optimization_test.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
sa_transformation.cc
reg_analysis.cc
|
| 47d2e48092717f2439b41d36430b5e1da9f8915e |
06-Feb-2015 |
Serguei Katkov <serguei.i.katkov@intel.com> |
LVN handles const-wide/32 incorrectly
Redundant shift to 16 bit should be eliminated otherwise any
32 bit shift of 32 bit constant will result in 0.
Change-Id: I4969b54357bc2d9a836e89dd7919199fff966684
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
ocal_value_numbering.cc
|
| a78ef44266c38cc4895554e973156a7c7896dd87 |
12-Feb-2015 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Fix InsertCaseLabel to return boundary_lir always
This patch doesn't return new_label when cu_->verbose, because
we will not assign offsets to new_label at this stage.
Change-Id: Ie7f625848b0cf7cabfbba694b5c20b0784bc8501
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/codegen_util.cc
|
| aa874e0bbfb21aec0661b93cb1c2ce065bc20302 |
10-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Rewrite Phi node insertion."
|
| 69c37c3b5bc868003115898a3d1754604bb6db96 |
10-Feb-2015 |
Jeff Hao <jeffhao@google.com> |
Merge "Revert "Revert "Allow preopted apps to have sharpened calls for non-x86 architectures."""
|
| 6a8946ba3d170fee0ff06de42209be4b14e6aff3 |
09-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Rewrite Phi node insertion.
Delay Phi node insertion to the SSAConversion pass to allow
updating the vreg_to_ssa_map_ with INVALID_SREG when we omit
a Phi in the pruned SSA form.
Change-Id: I450dee21f7dc4353d25fc66f4d0ee01671de6e0e
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ass_driver_me_post_opt.cc
ost_opt_passes.h
sa_transformation.cc
|
| 72f53af0307b9109a1cfc0671675ce5d45c66d3a |
12-Nov-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Remove MIRGraph::dex_pc_to_block_map_
This patch removes MIRGraph::dex_pc_to_block_map_, adds a local
variable dex_pc_to_block_map inside MIRGraph::InlineMethod(), and
updates several functions to pass dex_pc_to_block_map.
The goal is to limit the scope of dex_pc_to_block_map and
the usage of FindBlock, so that various compiler optimizations
cannot rely on dex pc to look up basic blocks to avoid
duplicated dex pc issues.
Also, this patch changes quick targets to use successor blocks
for switch case target generation at Mir2Lir::InstallSwitchTables().
Change-Id: I9f571efebd2706b4e1606279bd61f3b406ecd1c4
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
ir_graph.cc
ir_graph.h
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/codegen_util.cc
uick/mips/call_mips.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| a0acc2d5dbf8764b346da3d9e6ce1a91427fc4b5 |
27-Jan-2015 |
Jeff Hao <jeffhao@google.com> |
Revert "Revert "Allow preopted apps to have sharpened calls for non-x86 architectures.""
Should really say it allows pre-linked calls instead of sharpened calls.
Bug: 19100762
Change-Id: Ia2045a9eda92255e87a7f6187de18d6370b8f060
uick/arm64/call_arm64.cc
|
| 7d3186247cd382c4f7cf8093961795e8565b00e0 |
04-Feb-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Pass Options should be strings instead of integers"
|
| f4b24f7ea507ff41db39154a1e6a681a582e224a |
04-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "ART: Change x86 long param ABI (Quick/JNI/Opt)"
|
| 98a26e17bb7ecfcd5c9b96394fdeca0a67cafcb3 |
20-Jan-2015 |
Jean-Philippe Halimi <jean-philippe.halimi@intel.com> |
ART: Pass Options should be strings instead of integers
This patch modifies the pass options to handle string
values as well as integers. This will allow for more
verbose pass customization.
Change-Id: Iaf9507ceaae2cef317a23f0783404bacfdcad023
Signed-off-by: Jean-Philippe Halimi <jean-philippe.halimi@intel.com>
ompiler_ir.h
ass_driver_me.h
ass_me.h
|
| 900e7b36057410cb12cc3c1a066dca04db3c2d45 |
03-Feb-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ARM/ARM64: Dump thread offset."
|
| a34e760fa5cc3102ce1998f10816d380c37f43aa |
02-Feb-2015 |
Zheng Xu <zheng.xu@arm.com> |
ARM/ARM64: Dump thread offset.
Dump thread offset in compiler verbose log for arm32/arm64 and
oatdump for arm64.
Before patch :
0x4e: ldr lr, [rSELF, #604]
After patch :
0x4e: ldr lr, [rSELF, #604] ; pTestSuspend
Change-Id: I514e69dc44b1cf4c8a8fa085b31f93cf6a1b7c91
uick/arm/target_arm.cc
uick/arm64/target_arm64.cc
|
| b3cdf93d70256c4b0a9f6ed55ba4601f8c70bad4 |
27-Jan-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Fix to X86Mir2Lir::GenReduceVector
When generating the result to memory, the existing code didn't set the
aliasing correctly.
Mark the result as going to a Dalvik VR, and mark it as only a write.
Change-Id: I12f3156b7f84548b320a4fc142ff5a87a14e73d1
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/target_x86.cc
|
| cc6bb730e9bed0ca2d2f4999d73b9bfccf0fe961 |
02-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "AdvanceMIR does not know how to passthrough the empty block"
|
| ea392161b862f2cb93dffa019a32ec7dff47f21f |
29-Jan-2015 |
Serguei Katkov <serguei.i.katkov@intel.com> |
AdvanceMIR does not know how to passthrough the empty block
AdvanceMIR utility function could easily traverse the empty
blocks to find the next bytecode.
Change-Id: I037710b567275799f940b5b9766bcafec570b70e
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
ir_optimization.cc
|
| 14247b687562003721c18aecf3f7aecf2e53d6ce |
01-Feb-2015 |
Brian Carlstrom <bdc@google.com> |
Revert "Allow preopted apps to have sharpened calls for non-x86 architectures."
This reverts commit 1e3dfff2b73e142c568625a0310c1764658218c4.
uick/arm64/call_arm64.cc
|
| 3e6a3bf797e49b7f449256455c7e522e888687d8 |
19-Jan-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Change x86 long param ABI (Quick/JNI/Opt)
Ensure that we don't pass a long parameter across the last register
and the stack: skip the register and allocate it only on the stack.
This was requested to simplify the optimizing compiler code
generation for x86.
Optimizing (Baseline) compiler support for x86 longs:
- Remove QuickParameter from Location, as there are no longer any uses
of it.
Bump oat.h version because we changed an ABI again.
I changed IsParamALong() to return false for argument 0 (this argument).
I am not sure why it differed from all other tests.
I have not tested on ARM. I followed Nicolas's suggestions for setting
the value of kSplitPairAcrossRegisterAndStack for different
architectures.
Change-Id: I2f16b33c1dac58dd4f4f503e9c2309d845f5fb7a
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/target_x86.cc
|
| 6407d3c115a524986e0ef21182d0ee87039a9a17 |
29-Jan-2015 |
Jeff Hao <jeffhao@google.com> |
Merge "Allow preopted apps to have sharpened calls for non-x86 architectures."
|
| 5bdab12d8b48ca4c395d9d2c506ebff0df01b734 |
27-Jan-2015 |
Mathieu Chartier <mathieuc@google.com> |
Clean up pass driver
Added pass manager to hold the state which used to be in global
variables.
Static variables caused issues with Runtime.exit since they are
destroyed by the global destructors while threads are still
executing.
Bug: 17950037
Change-Id: Ie0e4546dc9e48909c8df996a5c135be682d50044
ir_graph.cc
ass_driver.h
ass_driver_me.h
ass_driver_me_opts.cc
ass_driver_me_opts.h
ass_driver_me_post_opt.cc
ass_driver_me_post_opt.h
ass_manager.cc
ass_manager.h
ass_me.h
uick/quick_compiler.cc
uick/quick_compiler.h
uick/quick_compiler_factory.h
|
| 763abfd0d803f8169e97d3da944043c2464aac0a |
28-Jan-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Even more Quick cleanup"
|
| 9c462086269324350516b3394d478f1d71a4b5d1 |
27-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Even more Quick cleanup
Remove Backend.
Change-Id: I247cc65ccda6a362ba1a8f5e73e7f12ecd980a87
ackend.h
ompiler_ir.cc
ompiler_ir.h
uick/codegen_util.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
|
| 966c3ae95d3c699ee9fbdbccc1acdaaf02325faf |
27-Jan-2015 |
Mark P Mendell <mark.p.mendell@intel.com> |
Revert "Revert "ART: Implement X86 hard float (Quick/JNI/Baseline)""
This reverts commit 949c91fb91f40a4a80b2b492913cf8541008975e.
This time, don't clobber EBX before saving it.
Redo some of the macros to make register usage explicit.
Change-Id: I8db8662877cd006816e16a28f42444ab7c36bfef
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 1e3dfff2b73e142c568625a0310c1764658218c4 |
27-Jan-2015 |
Jeff Hao <jeffhao@google.com> |
Allow preopted apps to have sharpened calls for non-x86 architectures.
Bug: 19100762
Change-Id: Idce391a06a85b881ce138756155b36e3ed7319c1
uick/arm64/call_arm64.cc
|
| eb6e852e1ed2b1c13e7b92a38a842dd42d60e82a |
27-Jan-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: More Quick cleanup"
|
| 949c91fb91f40a4a80b2b492913cf8541008975e |
27-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "ART: Implement X86 hard float (Quick/JNI/Baseline)"
And the 3 Mac build fixes. Fix conflicts in context_x86.* .
This reverts commits
3d2c8e74c27efee58e24ec31441124f3f21384b9 ,
34eda1dd66b92a361797c63d57fa19e83c08a1b4 ,
f601d1954348b71186fa160a0ae6a1f4f1c5aee6 ,
bc503348a1da573488503cc2819c9e30807bea31 .
Bug: 19150481
Change-Id: I6650ee30a7d261159380fe2119e14379e4dc9970
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 0e92f4fa0079dad6d1df69abd13054a9885cba98 |
27-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: More Quick cleanup
Remove frontend, move code to QuickCompiler.
Fix some includes.
Change-Id: Iedd8f339ec76635e48b166e285f7fc571fc948ac
rontend.cc
rontend.h
uick/quick_compiler.cc
|
| a2e18ed9397f21c96eae4a26df9ca35a6a97341d |
27-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix inlining of Mir2Lir
Missed -inl includes.
Change-Id: I39e6d603c7f5d36693aca3816653594488bff63f
uick/arm/assemble_arm.cc
uick/arm64/assemble_arm64.cc
uick/mips/assemble_mips.cc
|
| 8c1a3a22542bbe6f42649f1af7c579ddbb8134b2 |
27-Jan-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Some Quick cleanup"
|
| 0b9203e7996ee1856f620f95d95d8a273c43a3df |
23-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Some Quick cleanup
Make several fields const in CompilationUnit. May benefit some Mir2Lir
code that repeats tests, and in general immutability is good.
Remove compiler_internals.h and refactor some other headers to reduce
overly broad imports (and thus forced recompiles on changes).
Change-Id: I898405907c68923581373b5981d8a85d2e5d185a
b_optimizations.h
ompiler_internals.h
ompiler_ir.cc
ompiler_ir.h
ataflow_iterator.h
ex_flags.h
ex_types.h
rontend.cc
rontend.h
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_optimization.cc
ir_optimization_test.cc
ass.h
ass_driver.h
ass_driver_me.h
ass_driver_me_opts.cc
ass_driver_me_post_opt.cc
ass_me.h
ost_opt_passes.cc
ost_opt_passes.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/local_optimizations.cc
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
uick/ralloc_util.cc
uick/resource_mask.cc
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_location.h
sa_transformation.cc
erification_results.cc
erified_method.cc
reg_analysis.cc
|
| f80b64121d2a138c3863898ec14942fe27c0270e |
26-Jan-2015 |
Mathieu Chartier <mathieuc@google.com> |
Add missing EndTiming in CompileMethod
DCHECK failure when running tests with JIT.
Bug: 17950037
Change-Id: I4f886758b2a9322c2d7a8e8449e84c9a1709c813
rontend.cc
|
| 00ca84730a21578dcc6b47bd8e08b78ab9b2dded |
26-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix range check for intrinsic String.charAt() on x86.
Bug: 19125146
Change-Id: I274190a7a60cd2e29a854738ed1ec99a9e611969
uick/x86/target_x86.cc
|
| 3d2c8e74c27efee58e24ec31441124f3f21384b9 |
13-Jan-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Implement X86 hard float (Quick/JNI/Baseline)
Use XMM0-XMM3 as parameter registers for float/double on X86. X86_64
already uses XMM0-XMM7 for parameters.
Change the 'hidden' argument register from XMM0 to XMM7 to avoid a
conflict.
Add support for FPR save/restore in runtime/arch/x86.
Minimal support for Optimizing baseline compiler.
Bump the version in runtime/oat.h because this is an ABI change.
Change-Id: Ia6fe150e8488b9e582b0178c0dda65fc81d5a8ba
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| ff87d7bdc2c06bece8ea783dd4979360f1d51103 |
20-Jan-2015 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Fix GenInlined functions
This patch fixes Mir2Lir::GenInlinedReverseBytes,
Mir2Lir::GenInlinedAbsInt, Mir2Lir::GenInlinedAbsLong,
Mir2Lir::GenInlinedFloatCvt, Mir2Lir::GenInlinedDoubleCvt,
X86Mir2Lir::GenInlinedSqrt, X86Mir2Lir::GenInlinedMinMaxFP,
X86Mir2Lir::GenInlinedMinMax, X86Mir2Lir::GenInlinedPeek,
and X86Mir2Lir::GenInlinedReverseBits to generate no code, when results
are unused.
New calls without assignments are added to 082-inline-execute.
Change-Id: I7076e9ddbea43545315f2aeb677c63a8a6e95224
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/gen_invoke.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
|
| 582f541b35f40b75f2629a41259d2162608647d5 |
21-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix arm64 backend
Fix a register size problem after previous commit
f681570077563bb529a30f9e7c572b837cecfb83.
Change-Id: If04e647324bcd6fe279c25e70214a9f7c5b816ec
uick/arm64/utility_arm64.cc
|
| f681570077563bb529a30f9e7c572b837cecfb83 |
20-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Make some helpers non-virtual in Mir2Lir
These don't need to be virtual.
Change-Id: Idca3c0a4e8b5e045d354974bd993492d6c0e70ba
uick/arm64/codegen_arm64.h
uick/arm64/utility_arm64.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| 97d9f286971a4c1eec70e08f9f18f990d21780d5 |
20-Jan-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Some Quick cleanup"
|
| d500b53ff8742f76b63c9f7593082d9e8114b85f |
17-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Some Quick cleanup
Move some definitions around. In case a method is already virtual,
avoid instruction-set tests.
Change-Id: I8d98f098e55ade1bc0cfa32bb2aad006caccd07d
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.h
|
| ddf05aa4c4ed4a86ac51fd5eca87739c3164fd9c |
14-Jan-2015 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
ART: Fix compiler warning at arm/int_arm.cc:644
Clang can report warning:
int_arm.cc:644:89: error: 'ops.art::ArmMir2Lir::EasyMultiplyOp::shift'
may be used uninitialized in this function
OpRegRegRegShift(kOpRsub, r_tmp1, r_src, r_src, EncodeShift(kArmLsl, ops[0].shift));
That warning becomes blocker for libart-compiler.so compilation.
This patch fixes the only case where 'shift' member was uninitialized.
Change-Id: I6428170994c9f97e7a3d85d752b97dfcdff0c8a4
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/arm/int_arm.cc
|
| 066f9e4b87d875f02a10fd43d8a251b3c17a64a3 |
16-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Clean up optimization pass order.
Move the TypeInference pass to post-opt passes and make it
a PassMEMirSsaRep as we need to rerun the pass if the SSA
representation has changed. (Though we currently don't have
any pass that would require it.)
The results of MethodUseCount and ConstantPropagation passes
are used only in the BBOptimization and codegen and stay
valid across BBOptimization and SuspendCheckElimination, so
move them out of post-opt passes to just before the BBOpt
(and reverse the dependency between ConstantPropagation and
init reg locations passes).
Change-Id: If02c087107cef48d5f9f7c18b0a0ace370fe2647
b_optimizations.cc
b_optimizations.h
ir_optimization.cc
ass_driver_me_opts.cc
ass_driver_me_post_opt.cc
ost_opt_passes.cc
ost_opt_passes.h
reg_analysis.cc
|
| 71fb52fee246b7d511f520febbd73dc7a9bbca79 |
30-Dec-2014 |
Andreas Gampe <agampe@google.com> |
ART: Optimizing compiler intrinsics
Add intrinsics infrastructure to the optimizing compiler.
Add almost all intrinsics supported by Quick to the x86-64 backend.
Further intrinsics require more assembler support.
Change-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807
uick/dex_file_method_inliner.cc
|
| 8ebdc2bdbbae5dd014bce8d438f0eca02bad9ff9 |
14-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix indentation in Mips backend
Fix the indentation to be standard.
Change-Id: I39a16716be3429dfef6df0a585e24423b46363a2
uick/mips/assemble_mips.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
|
| ea1c64dba97cb367e6594332f2e542bfcf30e295 |
14-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix wide volatile IGET/IPUT on ARM without atomic ldrd/strd."
|
| ee5e273e4d0dd91b480c8d5dbcccad15c1b7353c |
13-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Fix wide volatile IGET/IPUT on ARM without atomic ldrd/strd.
If ldrd/strd isn't atomic, IPUT_WIDE uses ldrexd+strexd and
we need to record the safepoint for the ldrexd rather than
strexd. IGET_WIDE was simply missing the memory barrier.
Bug: 18993519
Change-Id: I4e9270b994f413c1a047c1c4bb9cce5f29e42cb4
uick/arm/utility_arm.cc
uick/gen_common.cc
|
| 7774edf4c19734922669fa888923e8c7d7385ea3 |
14-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Skip r1 on arm if first parameter is a long."
|
| 8d36591d93920e7b7830c3ffee3759b561f5339e |
13-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Use jalr instead of jr for Mips
Use the jalr instruction instead of jr in stubs and compiled code.
Change-Id: Idacc5167a5bb0113dc2e7716e4767e5ed07b5e0b
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/utility_mips.cc
|
| 69c15d340e7e76821bbc5d4494d4cef383774dee |
13-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Skip r1 on arm if first parameter is a long.
Change-Id: I16d927ee0a0b55031ade4c92c0095fd74e18ed5b
uick/arm/target_arm.cc
|
| 6650de241f63f725830560ec09c5e1f13c0d8488 |
12-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "Revert "ART: Implement hard float for X86""
|
| 0f9b03c65e0ee8bdc5ddf58af100f5fc356cc98b |
12-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "ART: Implement hard float for X86"
This reverts commit 59b9cf7ec0ccc13df91be0bd5c723b8c52410739.
Change-Id: I08333b528032480def474286dc368d916a07e17f
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 13428670585d9a7f6b24273fb26c721c2ff6c551 |
12-Jan-2015 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Implement hard float for X86"
|
| 59b9cf7ec0ccc13df91be0bd5c723b8c52410739 |
09-Jan-2015 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Implement hard float for X86
Use XMM0-XMM3 as parameter registers for float/double on X86. X86_64
already uses XMM0-XMM7 for parameters.
Change the 'hidden' argument register from XMM0 to XMM7 to avoid a
conflict.
This change was requested to simplify the Optimizing compiler
implementation.
Change-Id: I89ba8ade99b9a8a5b1ad1ee5f5cbfd33d656bfaa
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 425f239c291d435f519a1cf4bdd9ccc9a2c0c070 |
08-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix handling of long argument spanning register/memory.
Comment in arm_lir.h says:
* If a 64-bit argument would span the register/memory argument
* boundary, it will instead be fully passed in the frame.
This change implements such logic for all platforms. We still need
to pass the low part in register as well because I haven't ported
the jni compilers (x86 and mips) to it.
Once the jni compilers are updated, we can remove the register
assignment.
Note that this greatly simplifies optimizing's register allocator
by not having to understand a long spanning register and memory.
Change-Id: I59706ca5d47269fc46e5489ac99bd6576e87e7f3
uick/gen_invoke.cc
|
| d30feca670d0af02783bbdfd4a29c5078c18bdc5 |
06-Jan-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Remove LowestSetBit and IsPowerOfTwo"
|
| cfe71e59c667abb35bc2363c49af7f8b549c44d0 |
06-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix divide-by-zero for ARM
There was an infinite loop in the code generation for a divide
by literal zero.
Bug: 18887754
Change-Id: Ibd481918d3c6d7bc62fdd1a6807042009f561d95
uick/arm/int_arm.cc
|
| 7e499925f8b4da46ae51040e9322690f3df992e6 |
06-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Remove LowestSetBit and IsPowerOfTwo
Remove those functions from Mir2Lir and replace with functionality
from utils.h.
Change-Id: Ieb67092b22d5d460b5241c7c7931c15b9faf2815
uick/arm/call_arm.cc
uick/arm/int_arm.cc
uick/arm64/int_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/mir_to_lir.h
uick/resource_mask.cc
uick/x86/int_x86.cc
|
| 3d5872eb090a04a9444b5621d381eec3846f47a3 |
05-Jan-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Reorder entrypoint argument order"
|
| 43a725cde37740f0384f3f73227c54249ba4fe4f |
02-Jan-2015 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Cut filename for DumpCFG"
|
| 23149ac231d754647e536ff7c274d05f2fb729e2 |
02-Jan-2015 |
Bill Buzbee <buzbee@google.com> |
Merge "ART: Ensure FP GET/PUT doesn't use Core register"
|
| 1cc7dbabd03e0a6c09d68161417a21bd6f9df371 |
18-Dec-2014 |
Andreas Gampe <agampe@google.com> |
ART: Reorder entrypoint argument order
Shuffle the ArtMethod* referrer backwards for easier removal.
Clean up ARM & MIPS assembly code.
Change some macros to make future changes easier.
Change-Id: Ie2862b68bd6e519438e83eecd9e1611df51d7945
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| cee97e51ed45401c274cd67bfa6216624a995f6f |
20-Dec-2014 |
Andreas Gampe <agampe@google.com> |
ART: Cut filename for DumpCFG
If the name/path is too long, we'd silently fail dumping. Cut the
name when it's too long, and write an error message if we still
fail opening.
Change-Id: Id439a3367a8fdb50027959dd8c183913d074e669
ir_graph.cc
|
| 5c79aec9d53d1320041d5a52e5115d78d16035b7 |
22-Dec-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Swap-space in the compiler"
|
| e21dc3db191df04c100620965bee4617b3b24397 |
09-Dec-2014 |
Andreas Gampe <agampe@google.com> |
ART: Swap-space in the compiler
Introduce a swap-space and corresponding allocator to transparently
switch native allocations to memory backed by a file.
Bug: 18596910
(cherry picked from commit 62746d8d9c4400e4764f162b22bfb1a32be287a9)
Change-Id: I131448f3907115054a592af73db86d2b9257ea33
uick/codegen_util.cc
uick/mir_to_lir.h
|
| bfe400bb1a28cde991cdb3e39bc27bae6b04b8c2 |
19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Fix running out of temps when storing invoke-interface result.
On ARM, after emitting invoke-interface we didn't have any
free temps to use for storing the result, so we would crash
if the result was an unpromoted dalvik register with stack
location too far from SP.
Bug: 18769895
(cherry picked from commit d6bd06c713e8ec69de96510ef57bdf7adb4781ed)
Change-Id: Id88f6f3788eaf6ecbc7bd68880b445423f6e4f94
uick/arm/target_arm.cc
uick/arm64/target_arm64.cc
uick/gen_invoke.cc
uick/mips/target_mips.cc
uick/x86/target_x86.cc
|
| 1c6ea4483982803b3bc3635b7dd71744c1fe1cef |
19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Move two members out of MIRGraph::temp_::ssa.
It turns out they are used outside the SSA transformation
by the x86 back-end.
This is a partial revert of
https://android-review.googlesource.com/120571
Change-Id: Ia5cb2988ab0625d8519901124bd4fc184d5f0886
ir_dataflow.cc
ir_graph.cc
ir_graph.h
sa_transformation.cc
|
| a64d0142edd7c325c0a59d170d8c82c8176faa03 |
19-Dec-2014 |
Bill Buzbee <buzbee@google.com> |
Merge "ART: Implement FP packed reduce for x86"
|
| db75f3c7999395eeeded417e7db06194bf2dc608 |
19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Clean up dead loops before suspend check elimination."
|
| 202eaaf26ac4ec67fab479e181dbd2507737ff65 |
19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Clean up post-opt passes, perform only those we need."
|
| 341e425599ba32f0776bcd294882e1e30cafa10f |
19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up dead loops before suspend check elimination.
Get rid of BasicBlock::KillUnreachable() and just Kill()
unreachable blocks from the DFS order calculation.
Bug: 18718277
Change-Id: Icaf7b9c2320530e950f87e1e2e2bd1fa5f53cb98
b_optimizations.h
ir_graph.cc
ir_graph.h
ir_optimization.cc
|
| c146d498a184243d9100e94861f519a7378bfa68 |
19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Clean up MIRGraph::CanThrow()."
|
| 315cc20c2146b777c278d43987b2eeb61035d6a6 |
18-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up MIRGraph::CanThrow().
Merge with the code from CombineBlocks().
Change-Id: I73c71286acba1b6042f85f0bd19c525450ce9c05
ir_optimization.cc
|
| ffda4993af78484feb7a4ce5497c1796463c0ba1 |
18-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up post-opt passes, perform only those we need.
Change-Id: If802074d780d91151d236ef52236b6f33ca47258
b_optimizations.cc
b_optimizations.h
lobal_value_numbering_test.cc
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_optimization.cc
ir_optimization_test.cc
ass_driver_me_post_opt.cc
ost_opt_passes.h
sa_transformation.cc
|
| 52c489645b6e9ae33623f1ec24143cde5444906e |
16-Dec-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add support for volatile
- for backends: arm, x86, x86_64
- added necessary instructions to assemblies
- clean up code gen for field set/get
- fixed InstructionDataEquals for some instructions
- fixed comments in compiler_enums
* 003-opcode test verifies basic volatile functionality
Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
ompiler_enums.h
|
| 6c170c9e884e9dddf61d963d403042ee2a399e7d |
17-Dec-2014 |
Andreas Gampe <agampe@google.com> |
ART: Punt to the interpreter for VerifiedMethod errors
In case that the GC map can't be created (because of size restrictions),
do not fail the class. Instead punt to the interpreter.
Bug: 17791183
(cherry picked from commit f535c69f115c61ffadca1bd2706244d0aa30f9aa)
Change-Id: I348bb306dbfc85c235fa93c0c527fba6627551fe
erification_results.cc
erified_method.cc
|
| ee690a3dd364c025ebc1767d9f84097bb7473eec |
01-Dec-2014 |
David Brazdil <dbrazdil@google.com> |
ART: Added Checker, a pattern matching test engine
This patch adds a Python script which implements a domain-specific
mini-language similar to that of LLVM's FileCheck. It is primarily
intended for writing tests for the optimizing compiler but could be
configured for other use cases too. It is implemented from scratch in
order to avoid dependency on LLVM.
Checker tests are written in Java and dex2oat is invoked with a flag
which dumps the CFG before and after each pass of the optimizing
compiler. The output is then compared against assertions in the
test's comments parsed by Checker. See comments in tools/checker.py
for more details about the currently supported language features.
This initial CL implements only one type of assertion - whether the
output contains lines matching a desired pattern in the given order -
but supports both plain text and regex matching and allows for
equivalency testing by matching for the outcome of a previous match.
See the tests in compiler/optimizing/test/ConstantFolding.java for
examples.
Change-Id: I1ad7431b399c38dc0391ccee74d2c643ba0b0675
uick/quick_compiler.cc
|
| 6f5f5d05caed8465ad15ca5728e2a30c7a080d94 |
07-Dec-2014 |
Maxim Kazantsev <maxim.kazantsev@intel.com> |
ART: Implement FP packed reduce for x86
This patch implements correct FP vector reduction by index.
Previous implementation corresponded to packed add reduction.
Change-Id: I02a9bcb8e8945937ba7a511b723f23ec30667d34
uick/x86/target_x86.cc
|
| 55037f186fff482084cd5659ff747339eb17ba4e |
12-Dec-2014 |
Elliott Hughes <enh@google.com> |
Merge "Remove portable."
|
| 956af0f0cb05422e38c1d22cbef309d16b8a1a12 |
11-Dec-2014 |
Elliott Hughes <enh@google.com> |
Remove portable.
Change-Id: I3bf3250fa866fd2265f1b115d52fa5dedc48a7fc
rontend.cc
rontend.h
ir_optimization.cc
ortable/mir_to_gbc.cc
ortable/mir_to_gbc.h
uick/quick_compiler.cc
erification_results.cc
|
| dce6539817ce0ec198af549f2a89475fd88a07d3 |
12-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "AArch64: Fix incorrect use of preceding LIR."
|
| eb54d850cc713a64e8260d12db03bfd15b42584c |
10-Dec-2014 |
Ningsheng Jian <ningsheng.jian@arm.com> |
AArch64: Fix incorrect use of preceding LIR.
In Cortex-A53 erratum 835769 fixup, we should check the LIR for
previous emitted instruction, skipping pseudo LIRs and other
non-emitting LIRs.
Change-Id: I908f4c638650d7ad9c91112b74095bba2d81612e
uick/arm64/assemble_arm64.cc
|
| 36b58f5ebb85d58f8b5966b8577a6dfe720d1e16 |
10-Dec-2014 |
Mathieu Chartier <mathieuc@google.com> |
Add verifier support for dequickening
Also some cleanup.
Bug: 17950037
Change-Id: I1f50fe07f1558e9c4f78953b7afa639d7f310b3c
erified_method.cc
erified_method.h
|
| a262f7707330dccfb50af6345813083182b61043 |
25-Nov-2014 |
Ningsheng Jian <ningsheng.jian@arm.com> |
ARM: Combine multiply accumulate operations.
Try to combine integer multiply and add(sub) into a MAC operation.
For AArch64, also try to combine long type multiply and add(sub).
Change-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e
ompiler_enums.h
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
|
| ffc605cd817e79d6c7602a87543bb31f24d3a99f |
10-Dec-2014 |
Mathieu Chartier <mathieuc@google.com> |
Add missing iget quick for bool, byte, char, short
Bug: 17791557
Bug: 17671806
Change-Id: Ifac4fbfba6c3a3f97131e85914b24756fb7f9722
ex_to_dex_compiler.cc
uick/quick_compiler.cc
|
| 6bb3919e4413ad50f9b7e009829bba292b609e03 |
09-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Redefine the notion of back-egdes."
|
| 8b858e16563ebf8e522df026a6ab409f1bd9b3de |
27-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Redefine the notion of back-egdes.
Redefine a back-edge to really mean an edge to a loop head
instead of comparing instruction offsets. Generate suspend
checks also on fall-through to a loop head; insert an extra
GOTO for these edges.
Add suspend checks to fused cmp instructions.
Rewrite suspend check elimination to track whether there is
an invoke on each path from the loop head to a given back
edge, instead of using domination info to look for a basic
block with invoke that must be on each path. Ignore invokes
to intrinsics and move the optimization to a its own pass.
The new loops in 109-suspend-check should prevent intrinsics
and fused cmp-related regressions.
Bug: 18522004
Change-Id: I96ac818f76ccf9419a6e70e9ec00555f9d487a9e
b_optimizations.h
rontend.cc
rontend.h
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ir_optimization_test.cc
ass_driver_me_opts.cc
uick/gen_common.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
sa_transformation.cc
|
| ca5413403192022d734ce76fda9a84aa63eb9148 |
15-Oct-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Ensure FP GET/PUT doesn't use Core register
Routine void org.jbox2d.collision.AABB.combine(
org.jbox2d.collision.AABB, org.jbox2d.collision.AABB)
in the icyrocks application generated code for an iget of a FP field
that was loaded into a Core register, and then into an XMM register.
This was caused by the Dex code:
0x0030: iget v2, v2, F org.jbox2d.common.Vec2.x // field@3747
I traced this to GenIGet using a reg_class of kAnyReg, and EvalLoc
finding that v2 was available in EDX. Since kAnyReg is compatible
with EDX, The iget loaded the FP value into EDX, and then into an XMM
register for subsequent use.
Fix: Pass kSingle/kDouble into IGET/IPUT/SGET/SPUT/AGET/APUT when the
source/destination is FP. Change X86Mir2Lir::RegClassForFieldLoadStore
to return kFPReg for those cases. This causes EvalLoc to return an XMM
register, and the load is done right to the XMM register.
Change-Id: Ifbcc9e4d80bc6da8ea4ebf7e6cebaaf672a2766e
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/mir_to_lir.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 52222d132e500235aeaa427e2f4139dc20ed9288 |
08-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Kill unreachable blocks instead of just hiding them."
|
| 6c964c98400b8c0949d5e369968da2d4809b772f |
08-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Re-factor Quick ABI support"
|
| cb873d8fd06b7dde4b69c5987b4eaf541d345a50 |
08-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Kill unreachable blocks instead of just hiding them.
This changes the block type from kDalvikByteCode to kDead
and properly cleans up predecessors and MIRGraph::catches_.
Bug: 18626174
Change-Id: I268bf68f7947604bcb82caf95ee79c6831ee6e2a
ir_graph.cc
ir_graph.h
sa_transformation.cc
|
| 717a3e447c6f7a922cf9c3efe522747a187a045d |
13-Nov-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Re-factor Quick ABI support
Now every architecture must provide a mapper between
VRs parameters and physical registers. Additionally as
a helper function architecture can provide a bulk copy
helper for GenDalvikArgs utility.
All other things becomes a common code stuff:
GetArgMappingToPhysicalReg, GenDalvikArgsNoRange,
GenDalvikArgsRange, FlushIns.
Mapper now uses shorty representation of input
parameters. This is required due to location are not
enough to detect the type of parameter (fp or core).
For the details
see https://android-review.googlesource.com/#/c/113936/.
Change-Id: Ie762b921e0acaa936518ee6b63c9a9d25f83e434
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
ir_graph.cc
ir_graph.h
uick/arm/codegen_arm.h
uick/arm/target_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| b218c858606641050d13f35a2365168b89b44841 |
08-Dec-2014 |
Zheng Xu <zheng.xu@arm.com> |
ART: Clear use count for unused VRs.
The use count of temp VR should be cleared when we replace
"CMP_XXX vA, vB, vC" and "IF_XXX vA" with "kMirOpFusedCmpXXX vB, vC".
Otherwise, the backend may allocate a physical register for the unused vA.
Change-Id: I43ad37d0e7161ec3de154de8888caa94603f7715
ir_optimization.cc
|
| 9af6929d12d843ef1891fc0733746f7fa7ecedd4 |
05-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix code layout pass; don't terminate too early.
Change-Id: I0c417fdc2ee8213672a7568fe228e5e2f1c1ab61
ir_optimization.cc
|
| 27dee8bcd7b4a53840b60818da8d2c819ef199bd |
02-Dec-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86_64 QBE: use RIP addressing
Take advantage of RIP addressing in 64 bit mode to improve the code
generation for accesses to the constant area as well as packed switches.
Avoid computing the address of the start of the method, which is needed
in 32 bit mode.
To do this, we add a new 'pseudo-register' kRIPReg to minimize the
changes needed to get the new addressing mode to be generated.
Change-Id: Ia28c93f98b09939806d91ff0bd7392e58996d108
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
ompiler_enums.h
uick/codegen_util.cc
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 989210eb453898bd94bf3527f18f6146b07aa4bb |
04-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Use fewer insns for ARM LDR/STR with large offsets."
|
| aed3ad734c47fdccf179ff65971284a0d38583cd |
03-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Use fewer insns for ARM LDR/STR with large offsets.
LDR with large offset is frequently used for reading from
DexCache arrays, for example for static and direct invokes.
STR with large offset is rarely used but it's updated for
consistency.
Change-Id: I75871416cecbfd7fe7de590922cea0376a2f4019
uick/arm/utility_arm.cc
|
| ab972ef472001fa113d54486d7592979e33480b3 |
04-Dec-2014 |
Mathieu Chartier <mathieuc@google.com> |
Remove method verification results right after compiling a method
This saves memory since it allows the code arrays from methods
compiled in future methods to use the ram we just freed from the
verification results.
GmsCore.apk:
Before: dex2oat took 77.383s (threads: 2) arena alloc=6MB java alloc=30MB native alloc=77MB free=13KB
After: dex2oat took 72.180s (threads: 2) arena alloc=6MB java alloc=30MB native alloc=60MB free=13KB
Bug: 18596910
Change-Id: I5d6df380e4fe58751a2b304202083f4d30b33b7c
(cherry picked from commit 25fda92083d5b93b38cc1f6b12ac6a44d992d6a4)
uick/codegen_util.cc
erification_results.cc
erification_results.h
|
| a29f698b1754ee0ea2f46b6f5900e0da840dff79 |
25-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Implement InexpensiveConstantInt(., opcode) for ARM.
Fix kThumb2{Add,Sub}RRI12 to be used for their full range.
Add ORN for completeness.
Change-Id: I49a51541fa9ea085d4674b9131d8dd94da5337f3
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
|
| dde815ab8e1a1997ad01cb7f63dd10ef26597f46 |
01-Dec-2014 |
Bill Buzbee <buzbee@google.com> |
Merge "ART: x86 specific clearing higher bits when converting long to int"
|
| 758662e9d02727d9a88be395a92b476843c44d36 |
01-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Fix neg-long on ARM for overlapping regs."
|
| 05d5810c2b20ac83da82cef9a9677884af81147d |
01-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Refactor handling of conditional branches with known result."
|
| 0a080978fc822c51f06cb615662ee9ddcba4f677 |
01-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Use 16-bit conditional branch in Thumb2."
|
| 2f340a843ea5b3413c901f8c2365243b68864468 |
01-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix neg-long on ARM for overlapping regs.
Bug: 18569347
Change-Id: I764a4648b7ea5fd92f1ffbb9038b9d101b50d137
uick/arm/int_arm.cc
|
| 7ab2fce83cd72c0963128b098a78606e77ea15d5 |
28-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Refactor handling of conditional branches with known result.
Detect IF_cc and IF_ccZ instructions with known results in
the basic block optimization phase (instead for the codegen
phase) and replace them with GOTO/NOP. Kill blocks that are
unreachable as a result.
Change-Id: I169c2fa6f1e8af685f4f3a7fe622f5da862ce329
ir_optimization.cc
uick/codegen_util.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
|
| 6af820639c74e769ffc1f54930f6ebc11364f894 |
26-Nov-2014 |
Yevgeny Rouban <yevgeny.y.rouban@intel.com> |
ART: x86 specific clearing higher bits when converting long to int
The following problem description is taken from
https://android-review.googlesource.com/107261
If destination and source of long-to-int is the same physical
register on 64-bit then we do not emit any instructions but
consider that destination is a 32-bit view of source register.
As a result high part contains garbage. If the destination is
used later as index to array access then this garbage is used
in computation of address because address is 64-bit. For all
other cases garbage is just ignored.
A generic solution (113023) for all hw platforms was suggested
but rejected later for the sake of HW specific solution:
https://android-review.googlesource.com/113023
https://android-review.googlesource.com/114436
This patch is a rework of patch 113023 to stick with x86_64
specific changes: for 64-bit target this patch forces generating
reg-to-reg copy if the src and dest are the same physical
registers. This makes the higher bits be zeroed by 32-bit move
instruction.
Change-Id: Id29af839506ff9319ffba08b2e86e240fef4dafd
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
uick/gen_common.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 174636dad59068fc6e879b147ae02ac932f38c6f |
26-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Use 16-bit conditional branch in Thumb2.
We were using the 32-bit version because the compilation
time impact of having to change the instruction length and
reassemble instructions when the target is out of range was
too high. However, the assembly phase has been rewritten
since making that decision and the compile time impact is
now insignificant, so we prefer to save space.
Change-Id: Ib90f90d3f4e0c4e310267af272e3b16611026bbe
uick/arm/utility_arm.cc
|
| 9d5c25acdd1e9635fde8f8bf52a126b4d371dabd |
26-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Use 16-bit Thumb2 PUSH/POP when possible.
Generate correct PUSH/POP in Gen{Entry,Exit}Sequence()
to avoid extra processing during insn fixup.
Change-Id: I396168e2a42faee6980d40779c7de9657531867b
ompiler_enums.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
|
| eace45873190a27302b3644c32ec82854b59d299 |
25-Nov-2014 |
Mathieu Chartier <mathieuc@google.com> |
Move dexCacheStrings from ArtMethod to Class
Adds one load for const strings which are not direct.
Saves >= 60KB of memory avg per app.
Image size: -350KB.
Bug: 17643507
Change-Id: I2d1a3253d9de09682be9bc6b420a29513d592cc8
(cherry picked from commit f521f423b66e952f746885dd9f6cf8ef2788955d)
uick/gen_common.cc
|
| 6489d22a44ea7d135c142ee94925570d0333d5e7 |
25-Nov-2014 |
buzbee <buzbee@google.com> |
Quick compiler: handle embedded switch data
Although switch data is generally placed at the end of a dex
file by dx, it can occur elsewhere (and does via obsfucators).
This CL fixes a parsing error related to embedded switch data by
ensuring valid dex instructions following the embedded data appear
in their own basic blocks.
AOSP b/80600
Change-Id: I91ead6b398386bcf168b1088c5bc13a53b18f26e
ir_graph.cc
|
| 79d43fd465a302252062b1d6dbd32c8a7d79f266 |
25-Nov-2014 |
Bill Buzbee <buzbee@google.com> |
Merge "ART: GenLongArith has to clobber same operands for 2-op instr"
|
| 071beedcca66eac4032aa74327aa580a97ee3871 |
25-Nov-2014 |
Bill Buzbee <buzbee@google.com> |
Merge "ART: Generate switch targets from successor blocks"
|
| 55c5c3c26baac946750f5b91e8701bfb204d1ce6 |
25-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Skip null check in MarkGCCard() for known non-null values."
|
| ce41062ca468ae3abda9580098b4664b6474f605 |
24-Nov-2014 |
Andreas Gampe <agampe@google.com> |
Revert "ART: Remove wrong DCHECK"
This reverts commit 5be30072c5a750617dc3f9380776d074f26d9f32.
The underlying computation was fixed in AOSP before.
Bug: 17772057
Bug: 17763227
Bug: 17762845
uick/arm64/int_arm64.cc
|
| 743b98cd3d7db1cfd6b3d7f7795e8abd9d07a42d |
24-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Skip null check in MarkGCCard() for known non-null values.
Use GVN's knowledge of non-null values to set a new MIR flag
for IPUT/SPUT/APUT to skip the value null check.
Change-Id: I97a8d1447acb530c9bbbf7b362add366d1486ee1
ompiler_enums.h
ocal_value_numbering.cc
ocal_value_numbering_test.cc
ir_graph.h
uick/arm/int_arm.cc
uick/arm64/int_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/int_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/int_x86.cc
|
| 321b987ef037c44c0ed4e0e82661c88959a6239f |
24-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Further cleanup using dex_instruction_utils.h.
Change-Id: I85aa9e7d744b37ee3d2531c50470cd3fa87dc864
lobal_value_numbering.cc
ocal_value_numbering.cc
ocal_value_numbering.h
uick/dex_file_method_inliner.cc
reg_analysis.cc
|
| d7a6f48736d9ed27d8bab42237ee700a2737db8e |
24-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Eliminate suspend checks on back-edges to return insn."
|
| 26e7d454b9924f3673b075b05e4c604ad658a062 |
24-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Eliminate suspend checks on back-edges to return insn.
This optimization seems to have been broken for a long time.
Change-Id: I62ec85c71bb5253917ad9465a952911e917f6b52
lobal_value_numbering.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
|
| 1c51b2b01f7ac9d64838f46d895a534ea243f625 |
24-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Add div-zero check elimination to LVN/GVN"
|
| c2155048075b4916536f3aa23a88cd483b0f64a2 |
24-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Fix NullCheckElimination, BBCombine, and SplitBlock"
|
| c12da2d91c26e74786a32e7583d996416a2f3494 |
24-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Rewrite GVN's field id and field type handling."
|
| c7a77bfecb77c7a4538775411049e76eb853641c |
30-Oct-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Fix NullCheckElimination, BBCombine, and SplitBlock
NullCheckElimination had one issue and one assumption that could be
broken:
-It ignored that compiler temps may hold references.
-Assumed there are no phi nodes even though algorithm can be run even
after phi nodes are inserted.
BBCombine also had issue in that it did not properly maintain the
instruction links. The logic has been updated to use utility methods.
SplitBlock has an issue with being called after extended instructions
are inserted. Namely, in the case in question, it was called after
SpecialMethodInliner was through and although it was doing semantically
correct thing, it was hitting dcheck due to the kMirOpNullCheck.
Change-Id: Id5863ddb0762064e74bf1d9173b8db5cb47cf3b9
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_graph.cc
ir_optimization.cc
|
| da96aeda912ff317de2c41e5a49bd244427238ac |
27-Oct-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Generate switch targets from successor blocks
This patch relies on the successor blocks to generate switch targets
in GenSmallPackedSwitch and GenSmallSparseSwitch for all quick targets.
In x86, we create a new packed switch table by storing basic block
ids instead of dex offsets, and we override MarkPackedCaseLabels and
InsertCaseLabel to avoid calling FindBlock.
Change-Id: Ibb5983db582f0965aba787b520bd106522453564
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/gen_common.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| e0951144d71a4791a5319ec507d84fce373018e0 |
14-Nov-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Add div-zero check elimination to LVN/GVN
GVN has been updated to also consider div/rem zero check elimination.
This means that whenever a divisor is used in two sequential divisions,
the second division will surely not throw exception.
The algorithm has been updated to work on global level by considering
splits and merges. Obviously, if "div_zero" checked on one path but
not the other, at merge point consider that division has not been
eliminated.
One big deficiency of this algorithm is that it does not consider
literals in the divisor. Namely, in cases where the operand is a literal
or a constant (literal created by another bytecode), it does not mark as
divide by zero checked. However, in reality this is not an issue
because none of the backends generate the divide by zero check when
the constant value is known.
Issue: CAR-868
Category: device enablement
Domain: AOSP.ART-ME
Origin: internal
Upstream-Candidate: yes
Change-Id: I617569055c73a45e13e2a83392b99b48f4e33362
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_graph.cc
|
| f41b92c7a2fcdd411b9edd7070e4729ea18e0ba6 |
13-Oct-2014 |
Vladimir <vladimir.a.ivanov@intel.com> |
Fix possible array access issue
The issue with possible array access in the DisassembleExtendedInstr
method should be fixed. The input opcode should be extended one.
Additional check for it was added.
Also additional CHECK for memory allocation should be added.
Change-Id: If114572a5bc99587d5effd588e7bd955c16d8318
Signed-off-by: Vladimir <vladimir.a.ivanov@intel.com>
ir_graph.cc
|
| 819b3c05b1553dfd9fbde5fdb8f4cf77b5689682 |
22-Nov-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Fix crash with unreachable void check-cast"
|
| 2cfbccdc41a75694cf83c034f66b049d42a83ed6 |
22-Nov-2014 |
Ian Rogers <irogers@google.com> |
Merge "LSRA: Fix X86 shuffle flags"
|
| 6b9356cf0feb2a4100798481869fd4d18180c29f |
13-Nov-2014 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
ART: GenLongArith has to clobber same operands for 2-op instr
When we generate code for 'add-long/2addr v4, v4' and v4 is in
memory, we load v4 in a physical register, do operation and
store result in memory. After that, we should clobber the
physical register because it is not valid anymore.
Change-Id: I80903a831040bbfdf8a07810b6b2e8090fe1158c
Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com>
uick/x86/int_x86.cc
|
| b72c723bfb21e05cb9b0a7999db805df93fcaee8 |
29-Oct-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: X86 vectorized reduce may use incorrect extract index
In the case of reduction to memory VR, the extract index is ignored.
However, it should not be ignored because it is needed for pextr instruction.
Change-Id: I46a0c76218a0553e677225e403786522c079d27d
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_graph.cc
uick/x86/target_x86.cc
|
| af6925b7fe5dc5a3c8d52ee3370e86e75400f873 |
31-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite GVN's field id and field type handling.
Create a helper unit for dex insn classification and cache
dex field type (as encoded in the insn) in the MirFieldInfo.
Use this for cleanup and a few additional DCHECKs.
Change the GVN's field id to match the field lowering info
index (MIR::meta::{i,s}field_lowering_info), except where
multiple indexes refer to the same field and we use the
lowest of the applicable indexes. Use the MirMethodInfo from
MIRGraph to retrieve field type for GVN using this index.
This slightly reduces GVN compilation time and prepares for
further compilation time improvements.
Change-Id: I1b1247cdb8e8b6897254e2180f3230f10159bed5
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
ocal_value_numbering.cc
ocal_value_numbering_test.cc
ir_analysis.cc
ir_field_info.cc
ir_field_info.h
ir_graph.h
ir_optimization.cc
ir_optimization_test.cc
uick/gen_common.cc
|
| f585e549682a98eec12f92033e9634dc162b7df8 |
21-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up MIRGraph pass temporaries.
Create a union of pass-specific structs with temporaries
instead of shared temporaries with common names.
Change-Id: Id80d3b12c48139af1580b0839c21e07e7afd0ed5
ir_graph.cc
ir_graph.h
ir_optimization.cc
sa_transformation.cc
|
| 4514d2ac529064819d4f02699527764afa140008 |
21-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Add card mark to filled-new-array."
|
| bf535be514570fc33fc0a6347a87dcd9097d9bfd |
19-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Add card mark to filled-new-array.
Bug: 18032332
Change-Id: I35576b27f9115e4d0b02a11afc5e483b9e93a04a
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/codegen_util.cc
uick/gen_common.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| 8366ca0d7ba3b80a2d5be65ba436446cc32440bd |
17-Nov-2014 |
Elliott Hughes <enh@google.com> |
Fix the last users of TARGET_CPU_SMP.
Everyone else assumes SMP.
Change-Id: I7ff7faef46fbec6c67d6e446812d599e473cba39
uick/arm/int_arm.cc
uick/arm64/int_arm64.cc
uick/x86/target_x86.cc
|
| 8542ff31bfa778a06316511672dc113a3f19ae5b |
19-Nov-2014 |
Ian Rogers <irogers@google.com> |
Merge "AArch64: Addressing Cortex-A53 erratum 835769."
|
| cee552a858ed2b819f6440e555cc7165200dc0af |
19-Nov-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: X86Mir2Lir::OpRegRegReg should expect kOpMul for r_dest == r_src2 case"
|
| d79ac38df2a5e56b8929501803183f70053494bf |
19-Nov-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: fix x86 special identity"
|
| 4ee71b2df9eb74531d44528d028378bf0e90ecd7 |
18-Nov-2014 |
Pavel Vyssotski <pavel.n.vyssotski@intel.com> |
ART: X86Mir2Lir::OpRegRegReg should expect kOpMul for r_dest == r_src2 case
OpRegRegReg in case of r_dest == r_src2 does not expect kOpMul as valid operation.
This provokes abort compiling instruction like "mul-int v0, v1, v0" if both
operands are arriving in registers.
The fix is to expect kOpMul as comutative operation.
Change-Id: I259e49edea4b8b08ca4ed1c61033bbc2b2229078
Signed-off-by: Pavel Vyssotski <pavel.n.vyssotski@intel.com>
uick/x86/utility_x86.cc
|
| e8f74e58b476520cfc53970304c67b800994e33d |
19-Nov-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix x86 special identity
The Quick compiler recognizes and specially handles a set of
small methods - including those that simply return one of their
arguments. For x86, special identity was broken if the returned
argument was a double that was passed half in register and half
in memory.
internal b/17325447
Change-Id: I3a766977cdc0b4216d8ad65a9870c3250b32471e
uick/mir_to_lir.cc
|
| 130914ed7175797c4cb851368200c22a6a17fdec |
19-Nov-2014 |
Mathieu Chartier <mathieuc@google.com> |
Fix no relocate host tests
Change-Id: I905bf0327685d2119a2a5d157795e0e3f16286a7
uick/quick_compiler.cc
|
| 2d7210188805292e463be4bcf7a133b654d7e0ea |
10-Nov-2014 |
Mathieu Chartier <mathieuc@google.com> |
Change 64 bit ArtMethod fields to be pointer sized
Changed the 64 bit entrypoint and gc map fields in ArtMethod to be
pointer sized. This saves a large amount of memory on 32 bit systems.
Reduces ArtMethod size by 16 bytes on 32 bit.
Total number of ArtMethod on low memory mako: 169957
Image size: 49203 methods -> 787248 image size reduction.
Zygote space size: 1070 methods -> 17120 size reduction.
App methods: ~120k -> 2 MB savings.
Savings per app on low memory mako: 125K+ per app
(less active apps -> more image methods per app).
Savings depend on how often the shared methods are on dirty pages vs
shared.
TODO in another CL, delete gc map field from ArtMethod since we
should be able to get it from the Oat method header.
Bug: 17643507
Change-Id: Ie9508f05907a9f693882d4d32a564460bf273ee8
(cherry picked from commit e832e64a7e82d7f72aedbd7d798fb929d458ee8f)
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/gen_invoke.cc
uick/x86/target_x86.cc
|
| f18b92f1ae57e6eba6b18bee4c34ddbbd8bda74d |
14-Nov-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
LSRA: Fix X86 shuffle flags
The shuffle opcodes for X86 have incorrect flags. Fix them.
Clean up a couple of the printable string names too to remove an extra
"kX86".
Change-Id: I52a0ebdb1334cf0904bc2399eaf28b7cda041112
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
|
| 65420b244f18a3492a342ee3edaefeb26aed4230 |
27-Oct-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Addressing Cortex-A53 erratum 835769.
Some early revisions of the Cortex-A53 have an erratum (835769) whereby
it is possible for a 64-bit multiply-accumulate instruction in AArch64
state to generate an incorrect result. The conditions which a portion
of code must satisfy in order for the issue to be observed are somewhat
complex, but all cases end with a memory (load, store, or prefetch)
instruction followed immediately by the multiply-accumulate operation.
This commit makes sure to insert a nop instruction before a 64-bit msub
instruction, whenever the latter is preceded by a memory instruction.
This behaviour should make it impossible for the Arm64 backend to
generate a sequence of instructions which matches the erratum
conditions.
Change-Id: I0022eccd41180183c20231dab6e2671d001a204c
ompiler_enums.h
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/int_arm64.cc
|
| 5d99e333bcb454add372fe776a00d3172146bd6b |
17-Nov-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: copy dalvikInsn back on throw instruction processing"
|
| 2431452a13829996a440d7cdc30542e77d622b98 |
12-Nov-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Small improvements.
Remove useless branches (branch to the next instruction).
Change the implicit stack overflow check to do a 32-bit rather than a
64-bit load. Also put the result in wzr, as we do not need it.
Change-Id: I2d29fc62cb757ac5443fdd09282871f734deeef9
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
|
| 4594ad627a48e249ee1680e954558dea15f0d133 |
14-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Fix arm64 AGET/APUT to use 32-bit index."
|
| d582fa4ea62083a7598dded5b82dc2198b3daac7 |
06-Nov-2014 |
Ian Rogers <irogers@google.com> |
Instruction set features for ARM64, MIPS and X86.
Also, refactor how feature strings are handled so they are additive or
subtractive.
Make MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler
rather than #ifdefs that wouldn't have worked in cross-compilation.
Add SIMD features for x86/x86-64 proposed in:
https://android-review.googlesource.com/#/c/112370/
Bug: 18056890
Change-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666
uick/arm/utility_arm.cc
uick/gen_common.cc
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.h
|
| f20076ff813b8012096ff31af236d59db3c0f4e1 |
14-Nov-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Implicit null check should break def tracking"
|
| 172808c14506f4b46ebf0765e066306b7301760f |
13-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Use correct register class for refs"
|
| 9c3617a8f7413bb1181e72bc1f7086d986a86e18 |
13-Nov-2014 |
Pavel Vyssotski <pavel.n.vyssotski@intel.com> |
ART: Implicit null check should break def tracking
Implicit null check can provoke exception that needs to be sure all VRs are saved on stack.
The fix is to reset the def tracking system at the moment of adding an implicit null check.
Change-Id: Ie8a32b727086438e04e745d4a3f87f096ff36cac
Signed-off-by: Pavel Vyssotski <pavel.n.vyssotski@intel.com>
uick/gen_common.cc
|
| e08785bd2601d2d62567aacd51e99165120a9c53 |
07-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix arm64 AGET/APUT to use 32-bit index.
Change-Id: Iaa230024c934fc0ff7e45dcbebeb6c0e94e1af63
uick/arm64/int_arm64.cc
|
| 27503548bc8945da875240751dcd4b1495584669 |
06-Nov-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Use correct register class for refs
LoadValue requires thar ref location should reguest kRefReg
register class. The patch fixes GenFilledNewArray to specify
the register class correctly.
This is a fix for the crash of dex2oat on 412-new-array unit test.
This is a second attempt with an additional fix for arm64.
Change-Id: I9f0bb098cd1d1721ef03e8976c1460f8fa49aa2a
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/gen_common.cc
|
| 81ea72beefbf304cdc02942d131f5a5dab69e648 |
12-Nov-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Fix clobbering low part in 32-bit version of X86Mir2Lir::GenNegDouble"
|
| e49e9a08aef6f05c39912aeaa7e60bf61980670c |
12-Nov-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: GenNegLong incorrectly handled register overlap for x86"
|
| 570570e0edaf8e3c4e93f2a30c13e78b7301d512 |
11-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Revert "Use correct register class for refs""
|
| 29b55354f5856c353c0717ce2b570fabbec550ee |
11-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Revert "Use correct register class for refs"
This reverts commit 5c2555407d823356fb55ea3ffdf281aac00a583e.
Change-Id: I0490e9b1a9470e429f31911c9a4f28f71df78cc1
uick/gen_common.cc
|
| dbc30bc0e1f0dfcd09cb45ecf883dae51aaf853b |
11-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Use correct register class for refs"
|
| 5c2555407d823356fb55ea3ffdf281aac00a583e |
06-Nov-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Use correct register class for refs
LoadValue requires thar ref location should reguest kRefReg
register class. The patch fixes GenFilledNewArray to specify
the register class correctly.
This is a fix for the crash of dex2oat on 412-new-array unit test.
Change-Id: I58d969ddac0d84d4024bf686b5b0c12337ca9a37
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/gen_common.cc
|
| a9284c40e4a7621a086326273ef5e3cf87605000 |
11-Nov-2014 |
Ian Rogers <irogers@google.com> |
Merge "Fix CombineBlocks optimization"
|
| d4812a97de5d54d29c2964b2db7c2d52217be60e |
10-Nov-2014 |
Pavel Vyssotski <pavel.n.vyssotski@intel.com> |
ART: Fix clobbering low part in 32-bit version of X86Mir2Lir::GenNegDouble
If source registers overlap destination registers the low part of result can be clobbered in current implementation.
For example, for 'neg-double v5, v6' bytecode compiler can generates the following instructions:
lea ecx, [edx + 0x80000000]
mov eax, ecx
The fix forces source registers to be temp so there is no need to copy the low part.
Change-Id: I986ca17d1dc45c9e9d44a66e501cd354af496fde
Signed-off-by: Pavel Vyssotski <pavel.n.vyssotski@intel.com>
uick/x86/fp_x86.cc
|
| 08794a9481dec1da98f1a0c668c6dab3907b342a |
06-Nov-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Fix CombineBlocks optimization
(df_attributes & DF_DA) means Get not Put.
The patch fixes the condition to eliminate catch block for
get/put operations.
Change-Id: I48036f3614de5116e27c0d6e9a7a342432c9a828
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
ir_optimization.cc
|
| c35cda8fc5bb891eb9726a093f5764b75f44ab54 |
11-Nov-2014 |
Ian Rogers <irogers@google.com> |
Fix parentheses, tidy code.
Change-Id: I1ce671fa8a402aed3552102cadc96f277346f443
uick/mir_to_lir.cc
|
| d24c9346138b7b8723461d94d9866762a59929d9 |
10-Nov-2014 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
ART: GenNegLong incorrectly handled register overlap for x86
There is a bug in the GenNegLong: it should invoke
OpRegCopy(temp_reg, rl_result.reg.GetHigh());
instead of
OpRegCopy(temp_reg, rl_result.reg);
But, anyway there is no need to handle the overlap
anymore because it is already handled in OpRegCopyWide()
which is invoked from StoreValueWide().
Change-Id: I379ed23434c72a91e875e753708387be6502bc57
Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com>
uick/x86/int_x86.cc
|
| d45f76e59bf8342491ca02d64721537e06c79f43 |
09-Nov-2014 |
Ian Rogers <irogers@google.com> |
Merge "Tidy RegStorage for X86."
|
| b28c1c06236751aa5c9e64dcb68b3c940341e496 |
08-Nov-2014 |
Ian Rogers <irogers@google.com> |
Tidy RegStorage for X86.
Don't use global variables initialized in constructors to hold onto constant
values, instead use the TargetReg32 helper. Improve this helper with the use
of lookup tables. Elsewhere prefer to use constexpr values as they will have
less runtime cost.
Add an ostream operator to RegStorage for CHECK_EQ and use.
Change-Id: Ib8d092d46c10dac5909ecdff3cc1e18b7e9b1633
ompiler_enums.h
uick/arm/utility_arm.cc
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/mips/utility_mips.cc
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_storage.h
|
| aaf29b32d1aefd10980820a67b2f36f168e68ca8 |
08-Nov-2014 |
Ian Rogers <irogers@google.com> |
Tidy some uses of IsCompilationEnabled.
We should be checking IsCompilationEnabled in the compiler, we wouldn't be in
the compiler were compilation disabled.
Change-Id: Ib498fb6d610e4ed517494df01efa4b64a8c12528
rontend.cc
ir_analysis.cc
|
| 40d3518414202f33c9569ddd8daceabb30208fc2 |
03-Oct-2014 |
Stephen Kyle <stephen.kyle@arm.com> |
ART: Fix crash with unreachable void check-cast
return-void
check-cast v0, V
return-void
The above code sequence will not be rejected for the check-cast of a
void type because the check-cast is not reachable. However, when
GenerateSafeCastSet() is called from the compiler, this will cause
IsAssignableFrom(Conflict, Undefined) to be called, as it scans for all
check-casts across the code, regardless of its reachableness.
RegType::AssignableFrom() has been changed to handle a Conflict type,
whereas previously this would break the check that the lhs type is a
ReferenceType.
Additionally, GenerateSafeCastSet has been changed to never assess
instructions that weren't visited during verification.
Included is a new test DEX file, 801-VoidCheckCast, that uses this code
sequence.
Change-Id: I600055ab670ee48a075ffa867b46d2e74f5aa9c0
Signed-off-by: Stephen Kyle <stephen.kyle@arm.com>
erified_method.cc
|
| 648c7f61a26da49f929f412cf769e002bc6db488 |
06-Nov-2014 |
Ian Rogers <irogers@google.com> |
am 1991fed6: Merge "Don\'t enable ARM_R4_SUSPEND_FLAG."
* commit '1991fed6e39fc97c2dd4d55af33818008b3906a1':
Don't enable ARM_R4_SUSPEND_FLAG.
|
| 8ba17f6ce3853d4bdeee7527c9900e018781cf24 |
28-Oct-2014 |
Ian Rogers <irogers@google.com> |
Don't enable ARM_R4_SUSPEND_FLAG.
Bug: 17953517
Change-Id: I4578f1ffbfc987d5d178c7586b6bb99882ed19bb
uick/arm/arm_lir.h
uick/arm/int_arm.cc
|
| cae6e6b25be4ee7b7730cc3ddf5b7e8a490f6b6d |
05-Nov-2014 |
Ian Rogers <irogers@google.com> |
am 77dbcdd2: Merge "Fix LoadValue{Wide} to free temp when reg classes are not matched"
* commit '77dbcdd24fc99938c37ab0a32373466838ec8880':
Fix LoadValue{Wide} to free temp when reg classes are not matched
|
| 77dbcdd24fc99938c37ab0a32373466838ec8880 |
05-Nov-2014 |
Ian Rogers <irogers@google.com> |
Merge "Fix LoadValue{Wide} to free temp when reg classes are not matched"
|
| 5087696175b1c8808cd94dca1a0ed2e6fe591870 |
05-Nov-2014 |
Ian Rogers <irogers@google.com> |
am 40845d26: Merge "ARM: Strength reduction for floating-point division"
* commit '40845d266e1152a846858d94cee70c33b136de68':
ARM: Strength reduction for floating-point division
|
| 68347e807109afb3efd6239623fb7c67eda0b033 |
05-Nov-2014 |
Ian Rogers <irogers@google.com> |
am 211d45e0: Merge "X86 QBE: Mark kX86StartOfMethod as defining reg 0"
* commit '211d45e059935a7874a1ec89846f03d35ffba29f':
X86 QBE: Mark kX86StartOfMethod as defining reg 0
|
| 675e09b2753c2fcd521bd8f0230a0abf06e9b0e9 |
23-Oct-2014 |
Ningsheng Jian <ningsheng.jian@arm.com> |
ARM: Strength reduction for floating-point division
For floating-point division by power of two constants, generate
multiplication by the reciprocal instead.
Change-Id: I39c79eeb26b60cc754ad42045362b79498c755be
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
|
| 211d45e059935a7874a1ec89846f03d35ffba29f |
05-Nov-2014 |
Ian Rogers <irogers@google.com> |
Merge "X86 QBE: Mark kX86StartOfMethod as defining reg 0"
|
| 9913c84a5d1803b6d81d45774d3e2ebead215ba4 |
05-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
am 970a25ca: Merge "Clean up arena objects in Mir2Lir."
* commit '970a25ca627fe13ab381bc4c639868179a3c8f1f':
Clean up arena objects in Mir2Lir.
|
| 080dd413e133ae357ab9572d924f7a884315d535 |
05-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up arena objects in Mir2Lir.
Change-Id: I93fca37be2ae100ddebf80b6ba7a561b187e8886
uick/mir_to_lir.h
|
| 02c637e8d6952aba19a432e01fc94cece5071e2f |
29-Oct-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Fix LoadValue{Wide} to free temp when reg classes are not matched
If the current register mapping does not match the required one we
are allocating a new temp and make a copy. After that we are clobbering
the old mapping of VR to physical register. However we can also free it
for future allocations as soon as it will not used more.
This is a fix of the bug I met. The reason of the dex2oat crash was that
GenInlinedMinMaxFP loaded two sources to fp registers. It appeared that
both of them were live in two pairs of core regs. As a result after
loading of them all 4 temps available for x86 platfrom are marked as in use.
As a result after an attempt to allocate new temp to load a constant
required by GenInlinedMinMaxFP register allocator reported that there is
no available temp registers.
Change-Id: I9233012e39de1e574761f3d9bd3cad80d743e522
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/gen_loadstore.cc
|
| ae1a434fa1740791ba479da668e8372ca3dcb2a6 |
05-Nov-2014 |
Andreas Gampe <agampe@google.com> |
am 78a32333: Merge "ART: More warnings"
* commit '78a3233313260665fe82ba56257855e043bca3d4':
ART: More warnings
|
| 277ccbd200ea43590dfc06a93ae184a765327ad0 |
04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: More warnings
Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,
and -Wunused-but-set-parameter for GCC builds.
Change-Id: I81bbdd762213444673c65d85edae594a523836e5
ocal_value_numbering.cc
uick/arm/utility_arm.cc
uick/arm64/assemble_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/assemble_mips.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
sa_transformation.cc
|
| cdd98385e84a332c1a92b1b4497393dcf314693d |
04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
am ad17d418: Merge "ART: Replace COMPILE_ASSERT with static_assert (compiler)"
* commit 'ad17d41841ba1fb177fb0bf175ec0e9f5e1412b3':
ART: Replace COMPILE_ASSERT with static_assert (compiler)
|
| ad17d41841ba1fb177fb0bf175ec0e9f5e1412b3 |
04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Replace COMPILE_ASSERT with static_assert (compiler)"
|
| 785d2f2116bb57418d81bb55b55a087afee11053 |
04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: Replace COMPILE_ASSERT with static_assert (compiler)
Replace all occurrences of COMPILE_ASSERT in the compiler tree.
Change-Id: Icc40a38c8bdeaaf7305ab3352a838a2cd7e7d840
ocal_value_numbering.h
ir_field_info.h
ir_graph.h
ir_method_info.h
ir_optimization.cc
uick/arm/target_arm.cc
uick/arm64/assemble_arm64.cc
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
uick/resource_mask.cc
|
| 1525ed874f8611368ef34a9fc5556cc9130ccee6 |
04-Nov-2014 |
Ian Rogers <irogers@google.com> |
am a10a8b56: Merge "Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags."
* commit 'a10a8b56a01be95b3ec13022d3a155e163a11673':
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.
|
| 6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f |
31-Oct-2014 |
Ian Rogers <irogers@google.com> |
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.
Fix associated errors about unused paramenters and implict sign conversions.
For sign conversion this was largely in the area of enums, so add ostream
operators for the effected enums and fix tools/generate-operator-out.py.
Tidy arena allocation code and arena allocated data types, rather than fixing
new and delete operators.
Remove dead code.
Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
ackend.h
ompiler_enums.h
ex_to_dex_compiler.cc
lobal_value_numbering.h
ocal_value_numbering.cc
ocal_value_numbering.h
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ass.h
ass_me.h
ortable/mir_to_gbc.h
uick/arm/arm_lir.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
uick/ralloc_util.cc
uick/resource_mask.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_storage.h
erification_results.cc
|
| 56e8e608647133ae248acfec36e704c54c40c620 |
30-Oct-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: copy dalvikInsn back on throw instruction processing
The potentially throwing instructions in ART are splitted into
CHECK and work portions. On the Mir-To-Lir phase ART copies the
instruction info from the work part to CHECK and uses the CHECK
part for LIR emitting. But in some cases dalvik registers of the
work part might be changed and it may lead to incorrect
calculations.
This patch adds copying of the whole dalvikInsn structure, instead
of the operand field.
Change-Id: I17466169ec86e74f9f202785f1c57c0de9e56d06
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/mir_to_lir.cc
|
| 8ed5c9cbc26e013c1d92592f5adfaef949ca4dd3 |
31-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
am a9014f97: Merge "Support for CONST_STRING in optimizing compiler."
* commit 'a9014f977ae90373f5bad4cf812c2bda810b10f8':
Support for CONST_STRING in optimizing compiler.
|
| a9014f977ae90373f5bad4cf812c2bda810b10f8 |
31-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Support for CONST_STRING in optimizing compiler."
|
| b5f62b3dc5ac2731ba8ad53cdf3d9bdb14fbf86b |
30-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support for CONST_STRING in optimizing compiler.
Change-Id: Iab8517bdadd1d15ffbe570010f093660be7c51aa
rontend.cc
|
| ed54f6a95bc81e4e8f987e3955731d00c297c480 |
31-Oct-2014 |
Ian Rogers <irogers@google.com> |
am 45664c99: Merge "Avoid signed integer overflow."
* commit '45664c995b99e81f6d425206d7a43cb3b898daab':
Avoid signed integer overflow.
|
| 7d4ecd5edba1e4d4147692d67d9177154958801c |
30-Oct-2014 |
Ian Rogers <irogers@google.com> |
Avoid signed integer overflow.
Caught by -ftrapv there is a benign integer overflow if a switch has the
value max int within it (as in run-test 095).
Change-Id: I86bb8ce2f9097cb367c031ec51d58d01b31313e2
uick/gen_common.cc
|
| 5f70c79c81f171ff0aa126d58bfbe98772ab7e33 |
29-Oct-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86 QBE: Mark kX86StartOfMethod as defining reg 0
kX86StartOfMethod should be marked as writing to register 0, as that is
the destination register for the instruction.
Change-Id: I99cf24afa4c11d9ccdd4295f3481351e9eb4ee1f
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
|
| 9fe60107e9323434b1b2d6ee005854ca4e5108fa |
29-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 7c049c1f: Merge "Remove useless suspend points from arm/arm64 AGET/APUT."
* commit '7c049c1f34220b0dc1a7f68f3b30f388bae7bdb9':
Remove useless suspend points from arm/arm64 AGET/APUT.
|
| fb311f8a0d0eafd535f8d25d262dcea35a8feaa4 |
28-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Remove useless suspend points from arm/arm64 AGET/APUT.
Change-Id: Ib17da0c02599b943cb62582a8a25f187272d423b
uick/arm/int_arm.cc
uick/arm64/int_arm64.cc
|
| a229421dae3659f794a7c82f7dab3effe8badd12 |
28-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 4985fdf0: Merge "Rewrite class initialization check elimination."
* commit '4985fdf030e8e78f1c05266e989534cb26812bff':
Rewrite class initialization check elimination.
|
| 3e5c2ff35885165691ea3ae08186efaabfb4046b |
28-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 1ef3495a: Merge "Quick: Fix wide Phi detection in GVN, clean up INVOKEs."
* commit '1ef3495abfa2a858b3cc7a1844383c8e7dff0b60':
Quick: Fix wide Phi detection in GVN, clean up INVOKEs.
|
| 0e7217d74914d4feba6bd1c197c883177ea6867c |
28-Oct-2014 |
Ian Rogers <irogers@google.com> |
am 3e3364e2: Merge "Tidy logging code not using UNIMPLEMENTED."
* commit '3e3364e267117462894e0c3b7d9b413b25d28057':
Tidy logging code not using UNIMPLEMENTED.
|
| a660fc15d682912c9dc054f4b7cf53b8d90f337b |
28-Oct-2014 |
Ian Rogers <irogers@google.com> |
am c57a66d5: Merge "ARM: Use hardfp calling convention between java to java call."
* commit 'c57a66d5aadfd682c63e34ec1b1f304260f8c333':
ARM: Use hardfp calling convention between java to java call.
|
| d3ea207df0e26c4e041cbac8770a04e7f58d1c75 |
28-Oct-2014 |
Ian Rogers <irogers@google.com> |
am b62ff579: Merge "ART: Add div/rem zero check elimination flag"
* commit 'b62ff579cd870b0bf213765b07d7b404d15ece7b':
ART: Add div/rem zero check elimination flag
|
| f815266efc0bdc6c3466c341766104ddf84f0a0b |
28-Oct-2014 |
Ian Rogers <irogers@google.com> |
am c6c9e5d4: Merge "ART: Prevent float inference back to SSA in-regs."
* commit 'c6c9e5d4511f2b23cab09f9d6f535f96fe33cb9b':
ART: Prevent float inference back to SSA in-regs.
|
| 66c6d7bdfdd535e6ecf4461bba3804f1a7794fcd |
16-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite class initialization check elimination.
Split the notion of type being in dex cache away from the
class being initialized. Include static invokes in the class
initialization elimination pass.
Change-Id: Ie3760d8fd55b987f9507f32ef51456a57d79e3fb
ompiler_enums.h
lobal_value_numbering_test.cc
ocal_value_numbering.cc
ocal_value_numbering_test.cc
ir_dataflow.cc
ir_field_info.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.cc
ir_method_info.h
ir_optimization.cc
ir_optimization_test.cc
uick/gen_common.cc
|
| 1ef3495abfa2a858b3cc7a1844383c8e7dff0b60 |
27-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Fix wide Phi detection in GVN, clean up INVOKEs."
|
| 3e3364e267117462894e0c3b7d9b413b25d28057 |
25-Oct-2014 |
Ian Rogers <irogers@google.com> |
Merge "Tidy logging code not using UNIMPLEMENTED."
|
| 5667fdbb6e441dee7534ade18b628ed396daf593 |
23-Oct-2014 |
Zheng Xu <zheng.xu@arm.com> |
ARM: Use hardfp calling convention between java to java call.
This patch default to use hardfp calling convention. Softfp can be enabled
by setting kArm32QuickCodeUseSoftFloat to true.
We get about -1 ~ +5% performance improvement with different benchmark
tests. Hopefully, we should be able to get more performance by address the left
TODOs, as some part of the code takes the original assumption which is not
optimal.
DONE:
1. Interpreter to quick code
2. Quick code to interpreter
3. Transition assembly and callee-saves
4. Trampoline(generic jni, resolution, invoke with access check and etc.)
5. Pass fp arg reg following aapcs(gpr and stack do not follow aapcs)
6. Quick helper assembly routines to handle ABI differences
7. Quick code method entry
8. Quick code method invocation
9. JNI compiler
TODO:
10. Rework ArgMap, FlushIn, GenDalvikArgs and affected common code.
11. Rework CallRuntimeHelperXXX().
Change-Id: I9965d8a007f4829f2560b63bcbbde271bdcf6ec2
ompiler_enums.h
uick/arm/arm_lir.h
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
|
| b62ff579cd870b0bf213765b07d7b404d15ece7b |
25-Oct-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Add div/rem zero check elimination flag"
|
| 8fe0e35c546921a3576411948efffb3c813ef686 |
16-Oct-2014 |
Stephen Kyle <stephen.kyle@arm.com> |
ART: Prevent float inference back to SSA in-regs.
.method public static getInt(I)I
.registers 2
const/4 v0, 0x0
if-ne v0, v0, :after
float-to-int v0, v0
:exit
add-int/2addr v0, v1
return v0
:after
move v1, v0
goto :exit
.end method
In this code sample, v1 is the single parameter to this method. In one
of the phi-nodes inserted between :exit and add-int/2addr, v1's two
incoming SSA regs are:
- the initial def of v1 as a parameter
- the v1 def'd at move v1, v0.
During type inference, because the 2nd def is a float (because of the
earlier float-to-int v0, v0) this will change the type of the 1st def to a
float as well, which is incorrect since the first parameter is known to be
non-float.
This fix checks during phi-node type-inference if an SSA reg that is the
initial def of a parameter vreg is about to be set as float when it was
not previously, and skips the inference if so.
In this case, when using a hard-float ABI, having the in-reg v1 set as
float causes FlushIns() to read the argument to the method from an FP reg,
when the argument will be passed in a core reg by any caller.
Also included is a smali test for this bug: compare difference between
./run-test --64 800
./run-test --64 --interpreter 800
when the vreg_analysis patch has not been applied.
(Requires 64-bit because 32-bit ARM currently does not use hard-float.)
getInt(I)I should return its argument, but it returns an incorrect
value.
Change-Id: I1d4b5be6a931fe853279e89dd820820f29823da1
Signed-off-by: Stephen Kyle <stephen.kyle@arm.com>
reg_analysis.cc
|
| 2c4257be8191c5eefde744e8965fcefc80a0a97d |
24-Oct-2014 |
Ian Rogers <irogers@google.com> |
Tidy logging code not using UNIMPLEMENTED.
Change-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe
uick/arm64/utility_arm64.cc
|
| 4799e0d90003b3ac60e204fc254a97fbf0104bd1 |
24-Oct-2014 |
Ian Rogers <irogers@google.com> |
am aea6888b: Merge "Tidy up logging."
* commit 'aea6888b056be21adf762e066c7f33b8939b8a06':
Tidy up logging.
|
| ab9e1ce005d6b5b8777a8bb9db0fef35891c18a5 |
24-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am b08f4dcf: Merge "X86 Long Min/Max: Avoid calling SRegToVReg with -1"
* commit 'b08f4dcf90215ed49e0b796ab3e609bd605be8ba':
X86 Long Min/Max: Avoid calling SRegToVReg with -1
|
| a4426cff8a81e6af05aa8cc44c162110ccf2d397 |
22-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix wide Phi detection in GVN, clean up INVOKEs.
The detection of a wide Phi has been incorrectly looking at
the current LVN's wide sreg value map but we only intersect
live values and thus very often lose the information. This
results in failure to identify identical values, i.e.
potential missed optimizations. It also caused the bloating
of the global value map with values we would not use.
Rewrite the wide Phi detection to use the first merged LVN's
notion of wide sreg. For this to work we also need to use
the method's shorty to mark wide arguments.
Also clean up INVOKEs' processing to avoid another source
of bloating the global value map.
Bug: 16398693
Change-Id: I76718af7d62a8c6883ef43e4f47058f7eaf479e1
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
ocal_value_numbering.cc
ocal_value_numbering.h
|
| aea6888b056be21adf762e066c7f33b8939b8a06 |
22-Oct-2014 |
Ian Rogers <irogers@google.com> |
Merge "Tidy up logging."
|
| c7dd295a4e0cc1d15c0c96088e55a85389bade74 |
22-Oct-2014 |
Ian Rogers <irogers@google.com> |
Tidy up logging.
Move gVerboseMethods to CompilerOptions. Now "--verbose-methods=" option to
dex2oat rather than runtime argument "-verbose-methods:".
Move ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc
except for a forward declaration.
Remove ConstDumpable as Dump methods are all const (and make this so if not
currently true).
Make LogSeverity an enum and improve compile time assertions and type checking.
Remove log_severity.h that's only used in logging.h.
With system headers gone from logging.h, go add to .cc files missing system
header includes.
Also, make operator new in ValueObject private for compile time instantiation
checking.
Change-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641
ompiler_ir.cc
rontend.cc
|
| a65c1dbb8d3511da6c0804f8063c453f744629c2 |
21-Oct-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86 Long Min/Max: Avoid calling SRegToVReg with -1
It is possible that the result of a call to min/max can't be combined
with the following move. In that case, the destination will use the
default long return value (EAX/EDX), with a s_reg_low value of -1.
A debug compiler will assert fail in that case.
Fix: A result with no s_reg_low must be unused. Just return with no
code generated, like X86 GenInlinedAbsFloat().
Seen compiling GmsCore.apk on the host with a debug backend.
Change-Id: I8006e822e8dcb2112d86e4047bb2e3037ba6fece
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/int_x86.cc
|
| e15f5204642ad7c09b5c41021656379018080818 |
17-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 0008a6fa: Merge "Quick: In GVN, apply modifications early if outside loop."
* commit '0008a6fac0843bf8b86cfed76872d4a935bc7a9b':
Quick: In GVN, apply modifications early if outside loop.
|
| 415ac88a6471792a28cf2b457fe4ba9dc099396e |
30-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: In GVN, apply modifications early if outside loop.
To improve GVN performance, apply modifications to blocks
outside loops during the initial convergence phase. During
the post processing phase, apply modifications only to the
blocks belonging to loops.
Also clean up the check whether to run the LVN and add the
capability to limit the maximum number of nested loops we
allow the GVN to process.
Change-Id: Ie7f1254f91a442397c06a325d5d314d8f58e5012
b_optimizations.h
ataflow_iterator-inl.h
ataflow_iterator.h
rontend.cc
rontend.h
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
ocal_value_numbering.cc
ocal_value_numbering_test.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ass_driver_me.h
ass_me.h
|
| 54b3aa6b8da05b4cccea2cf56dc1d4eafbb9f765 |
17-Oct-2014 |
Ian Rogers <irogers@google.com> |
am b3f18cf7: Merge "Make ART compile with GCC -O0 again."
* commit 'b3f18cf7466f85e15c6b7f005f544867a4d6847a':
Make ART compile with GCC -O0 again.
|
| b3f18cf7466f85e15c6b7f005f544867a4d6847a |
17-Oct-2014 |
Ian Rogers <irogers@google.com> |
Merge "Make ART compile with GCC -O0 again."
|
| 6f3dbbadf4ce66982eb3d400e0a74cb73eb034f3 |
15-Oct-2014 |
Ian Rogers <irogers@google.com> |
Make ART compile with GCC -O0 again.
Tidy up InstructionSetFeatures so that it has a type hierarchy dependent on
architecture.
Add to instruction_set_test to warn when InstructionSetFeatures don't agree
with ones from system properties, AT_HWCAP and /proc/cpuinfo.
Clean-up class linker entry point logic to not return entry points but to
test whether the passed code is the particular entrypoint. This works around
image trampolines that replicate entrypoints.
Bug: 17993736
Change-Id: I5f4b49e88c3b02a79f9bee04f83395146ed7be23
ompiler_ir.h
uick/arm/utility_arm.cc
uick/gen_common.cc
|
| d06e989089c49bef7c08e704747625f9d86e72bd |
16-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 4ffed256: Merge "Quick: Avoid node iteration for passes that don\'t need it."
* commit '4ffed256cfae742e36ee735f806137f0d4a2f4b6':
Quick: Avoid node iteration for passes that don't need it.
|
| 2ba01fd23e418018c44c45d94d711e12c9ba6435 |
16-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 9ab7816a: Merge "Quick: Handle kMirOpNullCheck in LVN/GVN."
* commit '9ab7816aec7264d79750e93021ab8714822a038f':
Quick: Handle kMirOpNullCheck in LVN/GVN.
|
| 4ffed256cfae742e36ee735f806137f0d4a2f4b6 |
16-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Avoid node iteration for passes that don't need it."
|
| a78e66a2c0fb1ce75e3a4edaf0d70c0d1647dbad |
16-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Handle kMirOpNullCheck in LVN/GVN.
Change-Id: I0274e98cc61ccd1dbe0bd3e50deeb7d62bd1cb22
ocal_value_numbering.cc
|
| c6d1cba59b0d8401cb448a0c2e1f36e35beab3ba |
16-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am f1eb1002: Merge "Quick: Improve the BBCombine pass."
* commit 'f1eb10024d616c15af3b0cd81acabe59131be918':
Quick: Improve the BBCombine pass.
|
| d20557ac06a67e35cda4a865b8382672ab908b55 |
16-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 8fc5acfd: Merge "Rewrite null check elimination to work on dalvik regs."
* commit '8fc5acfd382bdc0d7920e8a13439b64344a8988a':
Rewrite null check elimination to work on dalvik regs.
|
| 312eb25273dc0e2f8880d80f00c5b0998febaf7b |
07-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Improve the BBCombine pass.
Eliminate exception edges for insns that cannot throw even
when inside a try-block. Run the BBCombine pass before the
SSA transformation to reduce the compilation time.
Bug: 16398693
Change-Id: I8e91df593e316c994679b9d482b0ae20700b9499
b_optimizations.h
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ass_driver_me_opts.cc
ass_driver_me_post_opt.cc
ost_opt_passes.h
sa_transformation.cc
|
| 7baa6f8783b12bb4b159ed4648145be5912215f2 |
09-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite null check elimination to work on dalvik regs.
And move the null check and class init check elimination
before the SSA transformation. The new pass ordering is in
anticipation of subsequent changes. (An improved class init
check elimination can benefit special method inlining. An
improved block combination pass before SSA transformation
can improve compilation time.)
Also add tests for the NCE.
Change-Id: Ie4fb1880e06334a703295aef454b437d58a3e878
b_optimizations.h
ir_dataflow.cc
ir_field_info.h
ir_graph.h
ir_optimization.cc
ir_optimization_test.cc
ass_driver_me_opts.cc
ass_driver_me_post_opt.cc
sa_transformation.cc
|
| 13f4c622077052011a8e2d4514abcfbd4a34c261 |
15-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 5c5efc25: Merge "ART: NullCheckElimination should converge with MIR_IGNORE_NULL_CHECK"
* commit '5c5efc253507eb43265997c9afcd778f72b6cef4':
ART: NullCheckElimination should converge with MIR_IGNORE_NULL_CHECK
|
| aa7b8a329561c6e1f05938ddc5e9c4be795cd8a5 |
15-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Avoid node iteration for passes that don't need it.
Change-Id: Ic1f6796a29ba861cee37a31193e07b497b84eb3f
ass.h
ost_opt_passes.h
|
| 423b137214debfa066522763a8e78511d300c8c9 |
15-Oct-2014 |
Yevgeny Rouban <yevgeny.y.rouban@intel.com> |
ART: NullCheckElimination should converge with MIR_IGNORE_NULL_CHECK
If the MIRGraph::EliminateNullChecksAndInferTypes() function managed
to prove that some regs are non-null then it sets the flag
MIR_IGNORE_NULL_CHECK and resets this flag for all the other regs.
If some previous optimizations have already set MIR_IGNORE_NULL_CHECK
then it can be reset by EliminateNullChecksAndInferTypes. This way
NullCheckElimination discards some optimization efforts.
Optimization passes should not reset MIR_IGNORE_NULL_CHECK unless
they 100% sure NullCheck is needed.
This patch makes the NCE_TypeInference pass merge its own
calculated MIR_IGNORE_NULL_CHECK with the one came from previous
optimizations. Technically NCE_TypeInference calculates the flag
in a temporary MIR_MARK-th bit by preserving MIR_IGNORE_NULL_CHECK.
Then at the end of NCE pass MIR_MARK is or-ed with
MIR_IGNORE_NULL_CHECK.
Change-Id: Ib26997c70ecf2c158f61496dee9b1fe45c812096
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
ompiler_enums.h
ir_graph.h
ir_optimization.cc
|
| 5c5676b26a08454b3f0133783778991bbe5dd681 |
30-Sep-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Add div/rem zero check elimination flag
Just as with other throwing bytecodes, it is possible to prove in some cases
that a divide/remainder won't throw ArithmeticException. For example, in case
two divides with same denominator are in order, then provably the second one
cannot throw if the first one did not.
This patch adds the elimination flag and updates the signature of several
Mir2Lir methods to take the instruction optimization flags into account.
Change-Id: I0b078cf7f29899f0f059db1f14b65a37444b84e8
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ompiler_enums.h
ir_graph.h
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 61357e47ca5381621d73abf3d5683cfd6af4fa78 |
14-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am c39eb4ae: Merge "Add regression test for null check elimination."
* commit 'c39eb4aef19b7fe64283fb3ae7ce6d13cd6c8294':
Add regression test for null check elimination.
|
| cc4f8f96227b7d2065103ab775e7e7c9a762e624 |
14-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 72ab3cad: Merge "Revert "ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK""
* commit '72ab3cadce5002163783d7b76781b9f26413b773':
Revert "ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK"
|
| 7cd01f5d496c384874ea8c21eafb2b6479833e6a |
13-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Add regression test for null check elimination.
Prompted by
https://android-review.googlesource.com/110090
Bug: 17969907
Change-Id: I938c27cda0681b9431d69baf4eafa7ca2f9b5c9c
ir_optimization.cc
|
| 72ab3cadce5002163783d7b76781b9f26413b773 |
13-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Revert "ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK""
|
| cb46ee13a5683c2973244da964887a448e61b6ec |
13-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Revert "ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK"
This reverts commit 504b7882fbb841787e350f2da54b1fa9171ce82a.
Change-Id: I41c7a03c49f7904370a64c6ececc89146ff735c8
ir_optimization.cc
|
| 528c78b28f08425b9eac5773523a3f7889c7fef9 |
10-Oct-2014 |
Ian Rogers <irogers@google.com> |
am 6b0518f6: Merge "Enable -Wimplicit-fallthrough."
* commit '6b0518f6cfa79b35c067d8bc4d50d054cfc6656c':
Enable -Wimplicit-fallthrough.
|
| fc787ecd91127b2c8458afd94e5148e2ae51a1f5 |
10-Oct-2014 |
Ian Rogers <irogers@google.com> |
Enable -Wimplicit-fallthrough.
Falling through switch cases on a clang build must now annotate the fallthrough
with the FALLTHROUGH_INTENDED macro.
Bug: 17731372
Change-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324
ocal_value_numbering.cc
ir_graph.cc
uick/arm/assemble_arm.cc
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/arm64/assemble_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/assemble_mips.cc
uick/mir_to_lir.cc
uick/x86/int_x86.cc
uick/x86/utility_x86.cc
|
| f625fd5f0257cfa8fef58e94e8544f4a7b55595d |
10-Oct-2014 |
Ian Rogers <irogers@google.com> |
am 182c9f66: Merge "stdint types all the way!"
* commit '182c9f660993abf05825a2d532fe5bba420f11f0':
stdint types all the way!
|
| 13735955f39b3b304c37d2b2840663c131262c18 |
08-Oct-2014 |
Ian Rogers <irogers@google.com> |
stdint types all the way!
Change-Id: I4e4ef3a2002fc59ebd9097087f150eaf3f2a7e08
ir_graph.cc
|
| 8e64ab3941329f7b384ddc1dc68afb4e765273c7 |
09-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
am 4ecaf87a: Merge "ART: X86: GenLongArith should handle overlapped VRs"
* commit '4ecaf87a2b62f4e51ee4c1f8b32aaea1473187a2':
ART: X86: GenLongArith should handle overlapped VRs
|
| d8c3e3608a7b47e82186e4f8118541ef06d9eab2 |
08-Oct-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: X86: GenLongArith should handle overlapped VRs
In a case, when src and dest VRs are overlapped when we called
GenLongArith it may cause the incorrect use of regs.
The solution is to map src to an physical reg and work with this
reg instead of mem.
Renamed BadOverlap() to PartiallyIntersects() for consistency.
Change-Id: Ia3fc7f741f0a92556e1b2a1b084506662ef04c9d
Signed-off-by: Katkov, Serguei I <serguei.i.katkov@intel.com>
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/arm/int_arm.cc
uick/codegen_util.cc
uick/mir_to_lir.h
uick/x86/int_x86.cc
|
| 1d574adbc331bfe4cd0238345600a2d734a08846 |
09-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 51205042: Merge "Quick: Reduce memory usage and improve compile time."
* commit '51205042343fa4852e01919de01fdcf261af510b':
Quick: Reduce memory usage and improve compile time.
|
| e7ee7ad455a4a6688eb175d944526a3d0a10808c |
09-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 2da74f2d: Merge "Quick: Separate null check elimination and type inference."
* commit '2da74f2de211b7ecb39464e641fa9794dc1b67f4':
Quick: Separate null check elimination and type inference.
|
| 5229cf17e3240d55f043c0a9308e22d967f897dc |
09-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Reduce memory usage and improve compile time.
Move the def-block-matrix from Arena to ScopedArena. Remove
BasicBlockDataFlow::ending_check_v and use a temporary bit
matrix instead. Remove unused BasicBlockDataFlow::phi_v.
Avoid some BitVector::Copy() at the end of null and clinit
check elimination passes when the contents of the source
BitVector is no longer needed.
Change-Id: I8111b2f8a51e63075aa124b528d61b79b6933274
ir_graph.cc
ir_graph.h
ir_optimization.cc
sa_transformation.cc
|
| 67c72b8882f539afd1c8643396fce417cadb85d5 |
09-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Separate null check elimination and type inference.
Change-Id: I4566ae9354c91ca935481cb4f5b729bba05c1592
b_optimizations.h
ir_graph.h
ir_optimization.cc
ass_driver_me_opts.cc
|
| c401ff06f38975a9680fa61f84e93b42187bd716 |
09-Oct-2014 |
Ian Rogers <irogers@google.com> |
am a9b09744: Merge "Don\'t copy fill array data to quick literal pool."
* commit 'a9b097443f26a6df1a322a8fef50fdd1f26a410b':
Don't copy fill array data to quick literal pool.
|
| 832336b3c9eb892045a8de1bb12c9361112ca3c5 |
09-Oct-2014 |
Ian Rogers <irogers@google.com> |
Don't copy fill array data to quick literal pool.
Currently quick copies the fill array data from the dex file to the literal
pool. It then has to go through hoops to pass this PC relative address down
to out-of-line code. Instead, pass the offset of the table to the out-of-line
code and use the CodeItem data associated with the ArtMethod. This reduces
the size of oat code while greatly simplifying it.
Unify the FillArrayData implementation in quick, portable and the interpreters.
Change-Id: I9c6971cf46285fbf197856627368c0185fdc98ca
ir_graph.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/gen_common.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| 5bf66fd9e6541d6386235b584d0a3f0c0dc06370 |
08-Oct-2014 |
Ian Rogers <irogers@google.com> |
am 175b2732: Merge "Header file clean up."
* commit '175b2732f7e55a07094c30aa08d946189b4af97e':
Header file clean up.
|
| 7e70b002c4552347ed1af8c002a0e13f08864f20 |
08-Oct-2014 |
Ian Rogers <irogers@google.com> |
Header file clean up.
Remove runtime.h from object.h.
Move TypeStaticIf to its own header file to avoid bringing utils.h into
allocator.h.
Move Array::DataOffset into -inl.h as it now has a utils.h dependency.
Fix include issues arising from this.
Change-Id: I4605b1aa4ff5f8dc15706a0132e15df03c7c8ba0
uick/arm/int_arm.cc
uick/arm64/int_arm64.cc
uick/mips/int_mips.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 35d013f642be175b3baf78cd28582aebe9beb69a |
08-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
am edc34c88: Merge "ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK"
* commit 'edc34c88b8f8abd04f9c4668787403608cf0b2d4':
ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK
|
| 176336d0343fc250647d754331b421e154b8b525 |
08-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
am 254aa0d3: Merge "ART: Fix SelectKind to work with nullptr"
* commit '254aa0d3f58b56b227077ef32b4606ebc25eaae4':
ART: Fix SelectKind to work with nullptr
|
| 32a74a44ee462ff27a3640c8d3bfc856a5b5bba9 |
08-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
am 1293b6b2: Merge "ART: Fix issues with SplitBlock"
* commit '1293b6b2adba33e8b5eca5632dd90c9835b2ef42':
ART: Fix issues with SplitBlock
|
| 26cce4cd1e83f626e5a90a7fa2ae7b2f7d47e4c4 |
08-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
am 893e8558: Merge "Fix to MirGraph::GetSSANameWithConst()"
* commit '893e855864b7535f7da92f3942d3f88aaa584dd8':
Fix to MirGraph::GetSSANameWithConst()
|
| edc34c88b8f8abd04f9c4668787403608cf0b2d4 |
08-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK"
|
| 254aa0d3f58b56b227077ef32b4606ebc25eaae4 |
08-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Fix SelectKind to work with nullptr"
|
| 1293b6b2adba33e8b5eca5632dd90c9835b2ef42 |
08-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Fix issues with SplitBlock"
|
| 893e855864b7535f7da92f3942d3f88aaa584dd8 |
08-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Fix to MirGraph::GetSSANameWithConst()"
|
| 33c17021c74b4e1911851ca89d634d15ed811d8d |
15-Sep-2014 |
Mathew Zaleski <mathew.zaleski@intel.com> |
ART: Fix issues with SplitBlock
The SplitBlock is a public interface from MIRGraph to be able to create two
blocks from one. This interface can be called not just during the control
flow graph building phase, but later. At that later point, extended instructions
may have already been inserted.
For example, SpecialMethodInliner can insert kMirOpNullCheck and kMirOpNop,
and then another pass tries to split block that contains this. The DCHECK
will fail even though the split is semantically correct.
Signed-off-by: Mathew Zaleski <mathew.zaleski@intel.com>
Conflicts:
compiler/dex/mir_graph.cc
Change-Id: I8bb3551407907909cda444a3379da2eb9331b9ff
ir_graph.cc
|
| 54083fb36485e74fdea4ddafb1de4f8686905eee |
08-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 50940ea8: Merge "Implement method calls using relative BL on ARM64."
* commit '50940ea8fe668a80c15920d98cae228851ceb990':
Implement method calls using relative BL on ARM64.
|
| 50940ea8fe668a80c15920d98cae228851ceb990 |
08-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Implement method calls using relative BL on ARM64."
|
| 9c14053a2a6529667c15de00f10f5251bf9f1a59 |
07-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 0d6102a8: Merge "Propagate optimization flags to kMirOpCheck."
* commit '0d6102a80ec741d701788decfb701a657d7a98f7':
Propagate optimization flags to kMirOpCheck.
|
| 504b7882fbb841787e350f2da54b1fa9171ce82a |
01-Oct-2014 |
Yevgeny Rouban <yevgeny.y.rouban@intel.com> |
ART: fix NullCheckElimination to preserve MIR_IGNORE_NULL_CHECK
If the MIRGraph::EliminateNullChecksAndInferTypes() function managed
to prove that some regs are non-null then it sets the flag
MIR_IGNORE_NULL_CHECK and resets this flag for all the other regs.
If some previous optimizations have already set MIR_IGNORE_NULL_CHECK
then it can be reset by EliminateNullChecksAndInferTypes. This way
NullCheckElimination discards some optimization efforts.
Optimization passes should not reset MIR_IGNORE_NULL_CHECK unless
they 100% sure NullCheck is needed.
This patch makes the NCE_TypeInference pass be conservative in
resetting MIR_IGNORE_NULL_CHECK.
Change-Id: I4ea74020968b5c5bd8e3af48211ffd4c6afd7f80
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
ir_optimization.cc
|
| 9944b3b792103cb72df1953b5502ced9bf128305 |
06-Oct-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Fix to MirGraph::GetSSANameWithConst()
Don't call ConstantValueWide() for a wide constant if high_word is set,
as it will DCHECK if you try to get the value for the high word.
Change-Id: I046ee3e6833ceb556a3c2dbc95699882d30d65f9
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
ir_graph.cc
|
| cc8cc7c7e2ba24667c0765b29c4417a5bf1d91c4 |
06-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Propagate optimization flags to kMirOpCheck.
Bug: 17751474
Change-Id: I9561b641d956e21dac686c7cd414fa0c6a176147
uick/mir_to_lir.cc
|
| c9ed6e64f910a3fb3afa34df36c9f8f56691164c |
03-Oct-2014 |
buzbee <buzbee@google.com> |
am dfaf4c39: Merge "Quick compiler: Fix ambiguous LoadValue()"
* commit 'dfaf4c39809035bca7af85d2c51a8bd2f381e58e':
Quick compiler: Fix ambiguous LoadValue()
|
| dfaf4c39809035bca7af85d2c51a8bd2f381e58e |
03-Oct-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: Fix ambiguous LoadValue()"
|
| 7c02e918e752ab36f0b6cab7528f10c0cf55a4ee |
03-Oct-2014 |
buzbee <buzbee@google.com> |
Quick compiler: Fix ambiguous LoadValue()
Internal b/17790197 & hat tip to Stephen Kyle
The following custom-edited dex program demonstrated
incorrect code generation caused by type confusion.
In the example, the constant held in v0 is used in both
float and int contexts, and the register class gets
confused at the if-eq.
.method private static getInt()I
.registers 4
const/16 v0, 100
const/4 v1, 1
const/4 v2, 7
:loop
if-eq v2, v0, :done
add-int v2, v2, v1
goto :loop
:done
add-float v3, v0, v1
return v2
.end method
The bug was introduced in c/96499, "Quick compiler: reference cleanup"
That CL created a convenience variant of LoadValue which selected the
target register type based on the type of the RegLocation. It should
not have done so. The type of a RegLocation is the compiler's best
guess of the Dalvik type - and Dalvik allows constants to be used
in multiple type contexts. All code generation utilities must specify
desired register class based on the capabilities of the instructions
to be emitted. In the failing case, OpCmpImmBranch (and
GenCompareZeroAndBranch) will be using core registers, so the
LoadValue must specify either kCoreReg or kRefReg.
The CL deletes the dangerous LoadValue() variant.
Change-Id: Ie4ec6e51b19676dbbb9628c72c8b3473a419e7ec
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mir_to_lir.h
uick/x86/int_x86.cc
|
| 7c2ad5af0bdd3cc1069038f8e3422d99aeb5f44c |
24-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Implement method calls using relative BL on ARM64.
Change-Id: I9e5d0b6c100b6cddd6bbb7ab07cff77ab104ea31
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/gen_invoke.cc
|
| 0bc0f416279207214f070a6c88db9b158c15c48a |
03-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 63462448: Merge "AArch64: oat patches should be 32-bit ints."
* commit '63462448ca4e377074a10a4720aa22f71154dbe9':
AArch64: oat patches should be 32-bit ints.
|
| 63462448ca4e377074a10a4720aa22f71154dbe9 |
03-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "AArch64: oat patches should be 32-bit ints."
|
| 12c35535d03dd3140ee75ebadb72e60eecd99c43 |
03-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 20810995: Merge "Remove all uses of MIR_INLINED."
* commit '20810995a11f29b8220658ab829791db0810eb9d':
Remove all uses of MIR_INLINED.
|
| 27cc09337cdff14f592f4e22fd235809ebe0d6a7 |
08-Sep-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: oat patches should be 32-bit ints.
This makes the arm64 backend consistent with the behaviour of the code
in oat_writer.cc and in the patchoat tool.
It also reduces the size of boot.oat by 1.6% (aosp_arm64-eng build).
Change-Id: Ia0b96737159c08955cd7b776ee396ff578cd58f6
uick/arm64/int_arm64.cc
uick/codegen_util.cc
|
| ff0ac4772d489d8780bbb6bb271dc6d5333cca7c |
02-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Remove all uses of MIR_INLINED.
They are not needed since
https://android-review.googlesource.com/103763
Change-Id: I1dffe5e219db615be9d9aaceb72ad9bd7c69b58e
ocal_value_numbering.cc
ir_dataflow.cc
uick/dex_file_method_inliner.cc
uick/gen_invoke.cc
uick/mir_to_lir.cc
uick/x86/utility_x86.cc
|
| 374e48cf5c68fd3423f3eaa830d8dfa655e945e5 |
02-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 6e301ec8: Merge "Fix build_all_egdes in MIRGraph::ProcessCanThrow()."
* commit '6e301ec84ff8cd55a29386cff9b3b00d51675b64':
Fix build_all_egdes in MIRGraph::ProcessCanThrow().
|
| 6e301ec84ff8cd55a29386cff9b3b00d51675b64 |
02-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix build_all_egdes in MIRGraph::ProcessCanThrow()."
|
| 6f5fab543da14df3769bebe1163e832a73bb54bd |
02-Oct-2014 |
Andreas Gampe <agampe@google.com> |
am 5be30072: ART: Remove wrong DCHECK
* commit '5be30072c5a750617dc3f9380776d074f26d9f32':
ART: Remove wrong DCHECK
|
| 5be30072c5a750617dc3f9380776d074f26d9f32 |
02-Oct-2014 |
Andreas Gampe <agampe@google.com> |
ART: Remove wrong DCHECK
Bug: 17772057
Bug: 17763227
Bug: 17762845
Change-Id: If5d35b8e3e156173f2e47ae86ff48ebfc01ca02d
uick/arm64/int_arm64.cc
|
| 8ac41af13c8e48ede6a7c8a3bf2fb1a414326038 |
02-Oct-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Fix SelectKind to work with nullptr
This patch fixes SelectKind to return kSelectNone
when MIR is nullptr to avoid segmentation fault.
Change-Id: I174ff5c153e03c1a1e2ef8bc68f7fb50e8a9bf3f
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
ir_optimization.cc
|
| dadd95ca1cd1e2152c2ae14e9c8e5b6768f2adcf |
01-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
am 37241e5c: Merge "Quick: Fix LVN/GVN handling of acquire operations."
* commit '37241e5c70aa599ff7383ad18af5ddf5694a7144':
Quick: Fix LVN/GVN handling of acquire operations.
|
| 37241e5c70aa599ff7383ad18af5ddf5694a7144 |
01-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Quick: Fix LVN/GVN handling of acquire operations."
|
| e767f6ce3997f7634b26e7651bc7b90c060d3965 |
01-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Fix build_all_egdes in MIRGraph::ProcessCanThrow().
Calculate build_all_edges only after in_try_block has
received its final value. This was a minor omission in
https://android-review.googlesource.com/100505
Change-Id: Icc9189d2092bbd29fcf1706e4d6074a6d915cebe
ir_graph.cc
|
| fa23645319cca1f1c4a7c208f931820f6783b1a4 |
29-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Quick: Fix LVN/GVN handling of acquire operations.
Acquire operations, i.e. MONITOR_ENTER and volatile GETs,
change the thread's view of the memory, so subsequent loads
must get new value names in LVN/GVN. Release operations do
not affect this thread's view of the memory, they the only
push the modifications for other threads to see.
Bug: 17689750
Change-Id: I9442d89b1d2c5252b99b02851b71bb85f871d734
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
|
| 228f9251668efe5ab303f9fb78841ed138954acb |
01-Oct-2014 |
Bill Buzbee <buzbee@google.com> |
Merge "ART: Overflow of bound check in ArrayCopy intrinsic" into lmp-dev
|
| 359e437b3dbc2e53b2f8db5a9a8135feade572cc |
01-Oct-2014 |
Ian Rogers <irogers@google.com> |
am 8283e079: Merge "Enable -Wunreachable-code"
* commit '8283e079a209e81caafd123a12a525922368fd34':
Enable -Wunreachable-code
|
| c9feb6af8497ff3060b62bf5ecbf9168295e3a76 |
01-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
am f9098ea6: Merge "ART: Fix GenReduceVector and GenSetVector"
* commit 'f9098ea6d7326b4d8de2860d18adf74046b80855':
ART: Fix GenReduceVector and GenSetVector
|
| 48aa8a091eae2c220d3883aed97945b14c6dd9e0 |
01-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
am 955af682: Merge "ART: Reset bb id to the last list mir"
* commit '955af682a64bcf4e66c33efc671325054c25a648':
ART: Reset bb id to the last list mir
|
| 466e978e81c9f2c184b25753184d32450edc1f07 |
01-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
am f4ae8d89: Merge "ART: Allow overridable calculation of basic block dataflow"
* commit 'f4ae8d8976abd1dcbb33824ced27775bff73f600':
ART: Allow overridable calculation of basic block dataflow
|
| d1e799e371e486b326970ac416d58e1c0980dd6e |
01-Oct-2014 |
Bill Buzbee <buzbee@android.com> |
am a2a91086: Merge "Update maximum number of reachable blocks in last step"
* commit 'a2a91086feb01c1465f063e10da70b7fa37a19eb':
Update maximum number of reachable blocks in last step
|
| 07140838a3ee44a6056cacdc78f2930e019107da |
01-Oct-2014 |
Ian Rogers <irogers@google.com> |
Enable -Wunreachable-code
Caught bugs in DeoptimizeStackVisitor and assemble_x86 SIB encoding.
Add UNREACHABLE macro to document code expected to be unreachable.
Bug: 17731047
Change-Id: I2e363fe5b38a1246354d98be18c902a6031c0b9e
uick/x86/assemble_x86.cc
|
| f9098ea6d7326b4d8de2860d18adf74046b80855 |
30-Sep-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Fix GenReduceVector and GenSetVector"
|
| 955af682a64bcf4e66c33efc671325054c25a648 |
30-Sep-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Reset bb id to the last list mir"
|
| f4ae8d8976abd1dcbb33824ced27775bff73f600 |
30-Sep-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Allow overridable calculation of basic block dataflow"
|
| a2a91086feb01c1465f063e10da70b7fa37a19eb |
30-Sep-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Update maximum number of reachable blocks in last step"
|
| 6f4dcae28c23a9ac42fd1283ea1c2462f5e1e210 |
29-Sep-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Allow overridable calculation of basic block dataflow
Currently dataflow information is not calculated for catch blocks in order to
reduce overhead. However, this makes assumption that the lack of this
information is only preventing local optimizations to catch block. But in
reality this problematic for global optimizations.
However, since no optimizations need complete information for now, simply
leave logic same but factor it out in separate method.
Change-Id: I5c13344c18409bd172a5d9b07577b4a1353cc733
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_dataflow.cc
ir_graph.h
|
| 6a49776cc11d8daf078d1f6243a4932cd88246e6 |
30-Sep-2014 |
Andreas Gampe <agampe@google.com> |
am 00ade1e5: Merge "ART: Fix some -Wpedantic errors"
* commit '00ade1e5eb76318790aad096ded1b7c4e9638785':
ART: Fix some -Wpedantic errors
|
| 00ade1e5eb76318790aad096ded1b7c4e9638785 |
30-Sep-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix some -Wpedantic errors"
|
| db7239ccce7748f2b494fb3b91c128b37019a093 |
17-Sep-2014 |
avignate <aleksey.v.ignatenko@intel.com> |
ART: Overflow of bound check in ArrayCopy intrinsic
System.arraycopy method is implemented as intrinsic on x86. It has
bound check which has a bug to overflow in certain conditions
when summ of array offset and number elements to be copied are
more than MAX_INT. For the methods like CarArrayBuffer.get it
means no OutOfBound exception to be thrown. The proposed
solution fixed that.
b/17711775
Signed-off-by: avignate <aleksey.v.ignatenko@intel.com>
(cherry picked from commit f9f0ed401f7fe4138a71b36719423b908a3b7bfb)
Change-Id: I1d4ca900df262d483a94ebea8fa686ea361772c8
uick/x86/target_x86.cc
|
| 2f8ffda4fa2a2c8002a7cc799ed23fa85cc706ee |
30-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
resolved conflicts for merge of 79705f99 to lmp-dev-plus-aosp
Change-Id: I6a87d6f2364ba3ac86d13faaf161dcc65990e4bb
|
| 4163c53ce38a0f1f88bf3e8d26de9914da38498b |
15-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: address some outstanding TODOs.
Fix comments in arm64_lir.h. Rename Arm* to A64* and replace FWIDE,
FUNWIDE, ... with WIDE, UNWIDE, ...
Change-Id: I4900902e28463ea5e00e34ea40ddfc15704c0bfa
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
|
| a1b3453a9ac5c7580de523d980f43ea1f5b4ab47 |
30-Sep-2014 |
Ian Rogers <irogers@google.com> |
am cc6b59ee: Merge "ART: Fix movnti assembler"
* commit 'cc6b59ee25d7b9782cc971687715d664a97b05bd':
ART: Fix movnti assembler
|
| cc6b59ee25d7b9782cc971687715d664a97b05bd |
30-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Fix movnti assembler"
|
| c8ccf68b805c92674545f63e0341ba47e8d9701c |
30-Sep-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix some -Wpedantic errors
Remove extra semicolons.
Dollar signs in C++ identifiers are an extension.
Named variadic macros are an extension.
Binary literals are a C++14 feature.
Enum re-declarations are not allowed.
Overflow.
Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
lobal_value_numbering.h
ocal_value_numbering.h
uick/quick_compiler.cc
|
| 775bbef0904b9169334714e8df2e3e2d76927a5b |
29-Sep-2014 |
Ian Rogers <irogers@google.com> |
am 1edf6380: Merge "ART: Deprecate CompilationUnit\'s code_item"
* commit '1edf638010c4b15b87f865d180c3b95026827e9a':
ART: Deprecate CompilationUnit's code_item
|
| 343157d5e5f3cb9f7004618f19b65b6af6143636 |
29-Sep-2014 |
Ian Rogers <irogers@google.com> |
am 1ee1458d: Merge "Reduce scope of MIR analysis attributes."
* commit '1ee1458dab818d5c44b7eba712918a5071df5d5b':
Reduce scope of MIR analysis attributes.
|
| 02ff2d4187249d26fabe8e5eacc27b99984ee353 |
04-Sep-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
AddIntrinsicSlowPath with resume requires clobbering
AddIntrinsicSlowPath with resume results in a call.
So all temps must be clobbered at the point where
AddIntrinsicSlowPath returns.
(cherry-picked from 9863daf4fdc1a08339edac794452dbc719aef4f1)
Change-Id: If9eb887e295ff5e59920f4da1cef63258ad490b0
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/arm/int_arm.cc
uick/arm64/int_arm64.cc
uick/gen_invoke.cc
uick/x86/target_x86.cc
|
| 1edf638010c4b15b87f865d180c3b95026827e9a |
29-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Deprecate CompilationUnit's code_item"
|
| 750359753444498d509a756fa9a042e9f3c432df |
12-Sep-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Deprecate CompilationUnit's code_item
The code_item field is tracked in both the CompilationUnit and the MIRGraph.
However, the existence of this field in CompilationUnit promotes bad practice
because it creates assumption only a single code_item can be part of method.
This patch deprecates this field and updates MIRGraph methods to make it
easy to get same information as before. Part of this is the update to
interface GetNumDalvikInsn which ensures to count all code_items in MIRGraph.
Some dead code was also removed because it was not friendly to these updates.
Change-Id: Ie979be73cc56350321506cfea58f06d688a7fe99
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ompiler_ir.cc
ompiler_ir.h
lobal_value_numbering_test.cc
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_optimization.cc
ir_optimization_test.cc
ortable/mir_to_gbc.cc
uick/arm/int_arm.cc
uick/codegen_util.cc
uick/ralloc_util.cc
|
| 584cc791cd0e352fb54ad54e72ba002a35dc758f |
29-Sep-2014 |
Ian Rogers <irogers@google.com> |
Reduce scope of MIR analysis attributes.
MIR analaysis attributes are only used in MIRGraph::AnalyzeBlock. Reduce the
scope to just the file that defines that function.
Reduce the size of the attributes from int32 to int16.
Remove the use of #defines in favor of enums.
Change-Id: I45ba3aa08beae67240507917b584d537a029838e
ir_analysis.cc
ir_graph.h
|
| ae9f3e6ef9f97f47416f829448e5281e9a57d8b8 |
23-Sep-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Fix movnti assembler
Movnti was receiving rex prefix before its opcode. Additionally,
the 64-bit version was missing the rex.w prefix.
Change-Id: Ie5c3bbe109765a0b990cafeeea1ee30329daabd0
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
|
| ed184b759d8a7f9cfd212e5c9418ee8ddbb86543 |
27-Sep-2014 |
buzbee <buzbee@google.com> |
am ed34f59c: Merge "Quick compiler: aarch64 codegen & long_min literal" into lmp-dev
* commit 'ed34f59c30f97e51e517d8dfb0741ed059014ff6':
Quick compiler: aarch64 codegen & long_min literal
|
| b504d2f89fdd5c01816bcbad752797cb78de0e99 |
27-Sep-2014 |
buzbee <buzbee@google.com> |
Quick compiler: aarch64 codegen & long_min literal
Int64 overflow during instruction selection caused incorrect
code patterns to emitted in some cases of long operations with
an immediate value of 0x8000000000000000.
The code in question was attempting to determine if the immediate
operand would fit in aarch64 immediate instruction variants.
Internal b/17630605
Change-Id: I8177021b73e51302bc1032387d83b1dd567ed6db
uick/arm64/utility_arm64.cc
|
| 53cec00aa6789382621a53b33b13f45bd27148ca |
26-Sep-2014 |
Udayan Banerji <udayan.banerji@intel.com> |
ART: Fix GenReduceVector and GenSetVector
For GenReduceVector:
We now correctly load non-wide values for non-wide destination registers,
and generate reg-reg and reg-mem forms of pextr correctly.
For GenSetVector:
We use the correct opcode from loading into an xmm from a 64-bit GPR
Change-Id: I0a01d1f0b12b32a0dee8f79a0139ffcf6d6cb4d5
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
uick/x86/target_x86.cc
|
| d282d59b482b6c3ecdb6af06eabaa7fd4bae975f |
26-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "Elimination of redundant instructuion"
|
| f4da675bbc4615c5f854c81964cac9dd1153baea |
01-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Implement method calls using relative BL on ARM.
Store the linker patches with each CompiledMethod instead of
keeping them in CompilerDriver. Reorganize oat file creation
to apply the patches as we're writing the method code. Add
framework for platform-specific relative call patches in the
OatWriter. Implement relative call patches for ARM.
Change-Id: Ie2effb3d92b61ac8f356140eba09dc37d62290f8
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/target_arm.cc
uick/codegen_util.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| db273aa1fc12a0e8a0d5a608df540e5d46a16b78 |
07-Sep-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86: evaluation destination should be after load of source in RA [DO NOT MERGE]
In almost most cases working with Register Allocator we must first
load source and then evaluate the destination. In this particular case
for byte-code shl-int/2addr v10, v10 we first find a destination (memory)
then load source (v10 -> physical register) and generate a shift operation
on memory. This is ok for this bytecode but RA thinks that v10 is in register
(we loaded source) and this is incorrect because updated value in memory
and physycal register is not up to date.
Change-Id: Ib4c71f70dcbf78b76ca89897e3bd605a89d77d08
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
(cherry picked from commit a464466fea8df617a50055230cfe7a16ea52cc14)
uick/x86/int_x86.cc
|
| 590c6a4ded1deb378baa253c86070d8eeffdc820 |
23-Sep-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Reset bb id to the last list mir
This patch fixes a bug in RemoveMIRList() to reset bb id to
the last list mir.
Change-Id: I0384d8d22e357b69725f455772f55296c50bc1d3
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
ir_graph.cc
|
| e39c54ea575ec710d5e84277fcdcc049f8acb3c9 |
22-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Deprecate GrowableArray, use ArenaVector instead.
Purge GrowableArray from Quick and Portable.
Remove GrowableArray<T>::Iterator.
Change-Id: I92157d3a6ea5975f295662809585b2dc15caa1c6
ataflow_iterator-inl.h
ataflow_iterator.h
lobal_value_numbering.cc
lobal_value_numbering_test.cc
ocal_value_numbering_test.cc
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_optimization.cc
ir_optimization_test.cc
ortable/mir_to_gbc.cc
ortable/mir_to_gbc.h
ost_opt_passes.cc
uick/arm/call_arm.cc
uick/arm/target_arm.cc
uick/arm64/call_arm64.cc
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/mips/call_mips.cc
uick/mips/target_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
sa_transformation.cc
|
| b7e9e3207577861030f0d5816baa523ef6bcd1bb |
22-Sep-2014 |
Anton Shamin <anton.shamin@intel.com> |
Elimination of redundant instructuion
Elimination of storing offset in phys register (while it's already
stored in ECX by default) from two address shift operation.
Change-Id: Iaf9abde65f505ab855f73f9da7bd13fa46c64fbb
Signed-off-by: Anton Shamin <anton.shamin@intel.com>
uick/x86/int_x86.cc
|
| 04db94656e4316fe84a19856452c6ca037799d11 |
20-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Address three issues with x86 assembler before enabling load store elimination."
|
| 8147dcb6b149ba5bba0915fdf0cbcb2dd18d431e |
19-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Overflow of bound check in ArrayCopy intrinsic"
|
| 87258edd817672daefc1d262af4cfdf732d4e454 |
19-Sep-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Slow path should break def tracking"
|
| 8d050d8cccaa4e7d4a3fde863ccb0411337c9c98 |
19-Sep-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AddIntrinsicSlowPath with resume requires clobbering"
|
| d872b7945ea07ba93ff984cb42b7388e0551a16c |
19-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Fix instruction flags of kMirOpCheck and kMirOpCheckPart2"
|
| f33e4d419e90b9a8514c040e5c8b5780965dd538 |
19-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "X86 QBE: Make some X86 routines virtual"
|
| b7fc629dc562ee9f3df04a112a70b7868664f94d |
10-Sep-2014 |
Udayan Banerji <udayan.banerji@intel.com> |
ART: Fix instruction flags of kMirOpCheck and kMirOpCheckPart2
Since they are just wrappers for correct modeling, it was believed
that these instructions do not need flags. However, the flags
are needed to correctly reflect their semantic behavior in a manner
consistent with all other instructions.
Also, missing flags for new extended instructions have also been added.
Change-Id: I2282eebf4b9c82b82e26722914645fcc0be49c82
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_graph.cc
|
| 497d62e65e703a8875ca5001b34a9740ec93b36f |
17-Sep-2014 |
buzbee <buzbee@google.com> |
ART: skip compilation of huge methods.
Besides not being worthwhile to compile, it huge methods could cause
overflow of some internal compiler structures.
internal b/17524219
(cherry picked from commit bf5d818f7e59ce33521ad81bbab68b1e7a09e0ba)
Change-Id: If99b47c3191c69feee319c9d73537e827ba0cc1d
rontend.cc
|
| bf5d818f7e59ce33521ad81bbab68b1e7a09e0ba |
17-Sep-2014 |
buzbee <buzbee@google.com> |
ART: skip compilation of huge methods.
Besides not being worthwhile to compile, it huge methods could cause
overflow of some internal compiler structures.
internal b/17524219
Change-Id: I0e47ff4757eec265809598830a2616ac367af77d
rontend.cc
|
| f9f0ed401f7fe4138a71b36719423b908a3b7bfb |
17-Sep-2014 |
avignate <aleksey.v.ignatenko@intel.com> |
ART: Overflow of bound check in ArrayCopy intrinsic
System.arraycopy method is implemented as intrinsic on x86. It has
bound check which has a bug to overflow in certain conditions
when summ of array offset and number elements to be copied are
more than MAX_INT. For the methods like CarArrayBuffer.get it
means no OutOfBound exception to be thrown. The proposed
solution fixed that.
Change-Id: Id16a26163a61d934b862a8729a52ca5c1a56caec
Signed-off-by: avignate <aleksey.v.ignatenko@intel.com>
uick/x86/target_x86.cc
|
| 88157efc1e16707d4ae10775d4acb15121c50fe7 |
12-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add the "time" compilation filter and output compilation stats.
A "time" compiler filter means the compiler optimizes for
compile time.
Change-Id: Id1a207ceb2d95f3548aae5e45d51b80695da2029
ir_analysis.cc
|
| 0a1174efd81fc25110ad106a84063c62af9ce7e5 |
11-Sep-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86 QBE: Make some X86 routines virtual
Add virtual in one place, and move some code into a virtual routine.
This allows subclassing and overriding for my purposes.
Change-Id: Ie415df943b17b56ad1f057513b2df2a31801a72f
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| c80605d6f13b0f1e5ac5446c755e6d210f06b19a |
11-Sep-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Consider clinit elimination for inlining
Currently inliner rejects inlining method if class initialization is needed.
However, if it has been proven already that it was done, then inlining
can safely proceed.
Change-Id: Iaf1638fcfffff1bcf66010dc39090c77e009a1bb
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_optimization.cc
|
| ebab3bbcaa09b644acd50ec18d79cb0d239bf347 |
13-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "Compile time performance improvements focusing on interpret-only."
|
| 7b078e8c04f3e1451dbdd18543c8b9692b5b067e |
10-Sep-2014 |
Ian Rogers <irogers@google.com> |
Compile time performance improvements focusing on interpret-only.
Reduce virtual method dispatch in the method verifier and make more code
inline-able.
Add a StringPiece with const char* equality operator to avoid redundant
StringPieces and strlens.
Remove back link from register line to verifier and pass as argument to reduce
size of RegisterLine.
Remove instruction length from instruction flags and compute from the
instruction, again to reduce size.
Add suspend checks to resolve and verify to allow for more easy monitor
inflation and reduce contention on Locks::thread_list_suspend_thread_lock_.
Change ThrowEarlierClassFailure to throw pre-allocated exception.
Avoid calls to Thread::Current() by passing self.
Template specialize IsValidClassName.
Make ANR reporting with SIGQUIT run using checkpoints rather than suspending
all threads. This makes the stack/lock analysis less lock error prone.
Extra Barrier assertions and condition variable time out is now returned as a
boolean both from Barrier and ConditionVariable::Wait.
2 threaded host x86-64 interpret-only numbers from 341 samples:
Before change: Avg 176.137ms 99% CI 3.468ms to 1060.770ms
After change: Avg 139.163% 99% CI 3.027ms to 838.257ms
Reduction in average compile time after change is 20.9%.
Slow-down without change is 26.5%.
Bug: 17471626 - Fix bug where RegTypeCache::JavaLangObject/String/Class/Throwable
could return unresolved type when class loading is disabled.
Bug: 17398101
Change-Id: Id59ce3cc520701c6ecf612f7152498107bc40684
erified_method.cc
|
| 98cb689a57882ecef33967b7804f98b8f8fc76f3 |
12-Sep-2014 |
buzbee <buzbee@google.com> |
Quick compiler (arm64) Fix inline Math.round()
Math.round is detected and inlined for arm64. However, the
arm64 backend incorrectly modified a source operand in place
during the round sequence. Depending on how registers are
allocated, that modification could persist. Changed to use a
temp register for the intermediate result.
Internal b/17411468
Change-Id: I7c636f985e193f8ff838768fde3b741e443bb1bb
uick/arm64/fp_arm64.cc
|
| 98216e53f8d538b4386b80b896edfa20e9734827 |
12-Sep-2014 |
buzbee <buzbee@google.com> |
Quick compiler (arm64) Fix inline Math.round()
Math.round is detected and inlined for arm64. However, the
arm64 backend incorrectly modified a source operand in place
during the round sequence. Depending on how registers are
allocated, that modification could persist. Changed to use a
temp register for the intermediate result.
Internal b/17411468
Change-Id: I7c636f985e193f8ff838768fde3b741e443bb1bb
uick/arm64/fp_arm64.cc
|
| a870bc5495b20a830ebd8342b49ef148bbff72dd |
09-Sep-2014 |
Haitao Feng <haitao.feng@intel.com> |
ART: Address three issues with x86 assembler before enabling load store elimination.
1) Remove the IS_LOAD attribute from LEA instructions.
2) Change the attribute of fp stack instructions from IS_UNARY_OP to IS_BINARY_OP as
operands[1] will be used to compute GetInstructionOffset.
3) Add IS_MOVE attribute for general register move instructions.
Change-Id: I7054df47956f2acecf579ff7acfde385fd8ac194
Signed-off-by: Haitao Feng <haitao.feng@intel.com>
uick/mir_to_lir-inl.h
uick/x86/assemble_x86.cc
|
| 589e046c483ca0dbee6c28fb617997f43ee28b94 |
05-Sep-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Slow path should break def tracking
Slow path usually results in invocation of runtime. Runtime
should be ensured that all VR on stack are up to date.
To do this we reset def tracking system at the moment of
adding slow path and as a result actual writes to stack
for all VRs will not be optimized away.
The decision is conservative to be safe however
probably not all runtime calls can potentially require VRs
to be on stack. In this case we will need insert reset def
tracking in all places where dangerous slow path is used.
Change-Id: I2cb7698a12c17354060fdbb944e1da1fb922c23b
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/codegen_util.cc
|
| 9863daf4fdc1a08339edac794452dbc719aef4f1 |
04-Sep-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
AddIntrinsicSlowPath with resume requires clobbering
AddIntrinsicSlowPath with resume results in a call.
So all temps must be clobbered at the point where
AddIntrinsicSlowPath returns.
Change-Id: If9eb887e295ff5e59920f4da1cef63258ad490b0
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/arm/int_arm.cc
uick/arm64/int_arm64.cc
uick/gen_invoke.cc
uick/x86/target_x86.cc
|
| a87a7950ee79f42351992d211517f9f22e9393ee |
11-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "Revert "Add read barriers for the roots in the verifier.""
|
| be428b4da47339409aac0cfa153888c384dfaef7 |
11-Sep-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Fix variable formatting and CodeLayout's multiple visits"
|
| d8f69b086baf6717ce949d1c4de90d73b91083b0 |
10-Sep-2014 |
Ian Rogers <irogers@google.com> |
Revert "Add read barriers for the roots in the verifier."
This reverts commit 7da9586b559290e1c16207c6513ffe485de61655.
Bug: 17398101
Change-Id: I1d6110fdf0d3a3c9241c8e7e7f4b85a298f9dd8e
erified_method.cc
|
| 75bcc3780bc40dd7c265e150aff5b891135ff6e3 |
04-Sep-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Fix variable formatting and CodeLayout's multiple visits
The CodeLayout pass visits multiple times the same BasicBlock. This patch
fixes that issue to reduce its overhead.
The patch also fixes cUnit to c_unit in the bb_optimization files.
Change-Id: I76afa73dc79b9ee9993223c066a974ca81adf203
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
b_optimizations.h
ir_optimization.cc
|
| b5477f0f8080cef4cb8a9dcea4367344ea7cdab4 |
10-Sep-2014 |
Junmo Park <junmoz.park@samsung.com> |
Fix kThumb2Vldrd definition to set correct flag.
kThumb2Vldrd shoud be set IS_LOAD_OFF4 not IS_LOAD_OFF.
Change-Id: I6b8ec3c54513f687a846ba7f3a817f6e439abcc9
Signed-off-by: Junmo Park <junmoz.park@samsung.com>
uick/arm/assemble_arm.cc
|
| 4e67841e99e4a206133e7010653ccd132682296a |
09-Sep-2014 |
Mathieu Chartier <mathieuc@google.com> |
Change Reference.get() intrinsic to Reference.getReferent().
The reference intrinsic was incorrectly inlining
PhantomReference.get(). We now get around this by adding a
layer of indirection. Reference.get() now calls getReferent()
which is intrinsified and inlined.
Requires:
https://android-review.googlesource.com/#/c/107100/
Bug: 17429865
(cherry picked from commit cd48f2d86197d4fe87cc88077bc4af5ba66e5295)
Change-Id: Ie91e70abf43cedf3c707c7bb8a5059e19d2a2577
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| cd48f2d86197d4fe87cc88077bc4af5ba66e5295 |
09-Sep-2014 |
Mathieu Chartier <mathieuc@google.com> |
Change Reference.get() intrinsic to Reference.getReferent().
The reference intrinsic was incorrectly inlining
PhantomReference.get(). We now get around this by adding a
layer of indirection. Reference.get() now calls getReferent()
which is intrinsified and inlined.
Requires:
https://android-review.googlesource.com/#/c/107100/
Bug: 17429865
Change-Id: Ie91e70abf43cedf3c707c7bb8a5059e19d2a2577
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| a464466fea8df617a50055230cfe7a16ea52cc14 |
07-Sep-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86: evaluation destination should be after load of source in RA
In almost most cases working with Register Allocator we must first
load source and then evaluate the destination. In this particular case
for byte-code shl-int/2addr v10, v10 we first find a destination (memory)
then load source (v10 -> physical register) and generate a shift operation
on memory. This is ok for this bytecode but RA thinks that v10 is in register
(we loaded source) and this is incorrect because updated value in memory
and physycal register is not up to date.
Change-Id: Ib4c71f70dcbf78b76ca89897e3bd605a89d77d08
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/int_x86.cc
|
| 90a21f8e76028b9f89e91c436fc6fe9e9a354694 |
07-Sep-2014 |
buzbee <buzbee@google.com> |
Quick compiler: Fix handling of unused returns
As part of the inlining process, the quick compiler will attempt
to eliminate MOVE_RESULT instructions and deliver the result of
the inlined function directly to the eventual use.
The type of the returned value is determined by the subsequent
use (which had already been typed via the size and type
inference pass). However, if a method result is never used the code
just defaulted to assigning dummy core sink register[s]. This
caused a DCHECK failure on some 64-bit systems for methods returning
an unused reference (although the generated code was correct).
This CL selects sink registers for the unused return case based
on the type of the inlined method, and adds another DCHECK to
verify that the result of the size & type inference pass matches
with the inlined method's type.
Internal b/17328561
Change-Id: I9803ad604fe1bdcf9ff9a1d310cf022a7b6deae2
uick/gen_invoke.cc
|
| 9b868cbfa6d74387a80ce52a426f9a5bc3ddbbaf |
07-Sep-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Make the dominator bitvectors expandable"
|
| eacc5f015fab4d6607f72165b0902f49f7d18763 |
01-Sep-2014 |
Junmo Park <junmoz.park@samsung.com> |
Fix Thumb2Stm, ldm definition of EncodingMap for arm
Thumb2Stm instruction can save r0-r12,r14.
But the definition of EncodingMap only set r0-r12.
So it is fixed likes Thumb2Stmia.
Add new assembler formats kFmtLdmRegList and kFmtStmRegList.
Change-Id: Id03118d602f9d49d9d916f3dd9f3198f24ab9c37
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
|
| 007a065ac5dbb41a271c5cc117fccb6b04b323ae |
06-Sep-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Make the dominator bitvectors expandable
The dominator based bitvectors are not expandable. However, if we wish
to add BasicBlocks and recalculate, it is required to make them expandable.
Change-Id: I250684783c233eca31bb40a5bc971c97fcf7c42d
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
sa_transformation.cc
|
| 3a91f442218339709bab1b5ae189de40fb546c93 |
02-Sep-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: X86: Improve multiply in div/rem by literal
Rewrite the multiplication of the magic number by the dividend to save
one instruction by multiplying directly from the dividend, rather than
loading the dividend into EAX/RAX first.
Change-Id: I7934243d90c0739a7f11a8d70f6fb2c000144587
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/int_x86.cc
|
| 57f2bbda741d2d3d769a50268b4e0b9b54959684 |
04-Sep-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Fix x86_64 GenSelect case when destination is Ref
Reference in x86_64 is a 64-bit solo register. As a result, the invocation
of OpRegImm results in an error when Select opcode of the kind:
ref = boolean ? null : null;
because opRegImm does not support 64-bit destination for OpMov.
The case above is only possible for ref because no one other constant except
null is possible.
Bug: 17327895
Change-Id: I7541e744ec1c8619711712fd17be72764efcf3a8
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
(cherry picked from commit 3f51e7d942c22edaab3a7e703a1e6a2dd6a26f77)
uick/x86/int_x86.cc
|
| 3f51e7d942c22edaab3a7e703a1e6a2dd6a26f77 |
04-Sep-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Fix x86_64 GenSelect case when destination is Ref
Reference in x86_64 is a 64-bit solo register. As a result, the invocation
of OpRegImm results in an error when Select opcode of the kind:
ref = boolean ? null : null;
because opRegImm does not support 64-bit destination for OpMov.
The case above is only possible for ref because no one other constant except
null is possible.
Bug: 17327895
Change-Id: I7541e744ec1c8619711712fd17be72764efcf3a8
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/int_x86.cc
|
| 6dccdc2511c9f22d3cc2ea83386ce9db2688fa19 |
18-Aug-2014 |
Maxim Kazantsev <maxim.kazantsev@intel.com> |
ART: Reduce LockCallTemps usage
Using FlushAllRegs/LockCallTemps in integer arithmetics causes
excess register flushing and clobbering. This patch adds API that
allows to flush, clobber and lock only those registers we really
need for calculations.
Change-Id: Idabaa4fff4d18a33e5040a80f66f2df6432f8be0
Signed-off-by: Max Kazantsev <maxim.kazantsev@intel.com>
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 328c430e923ce8d18532d0fdd26cd233e73763dd |
04-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Vectorization opcode implementation fixes"
|
| d73f52b1b9bea825d98830a906511a9e97ab277d |
04-Sep-2014 |
Ian Rogers <irogers@google.com> |
Merge "Add numerator check for integer divide and modulo"
|
| fbebc696cb4a6dd7cfaeb978076330ae34ffffac |
02-Sep-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Only call CalculateBasicBlockInformation once
CalculateBasicBlockInformation gets called twice now when dirty is true.
Change-Id: I8aa0569e4c00ea884a45ecea957a4ae06a328969
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ass_driver_me_opts.cc
|
| b3a84e2f308b3ed7d17b8e96fc7adfcac36ebe77 |
28-Jul-2014 |
Lupusoru, Razvan A <razvan.a.lupusoru@intel.com> |
ART: Vectorization opcode implementation fixes
This patch fixes the implementation of the x86 vectorization opcodes.
Change-Id: I0028d54a9fa6edce791b7e3a053002d076798748
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Signed-off-by: Philbert Lin <philbert.lin@intel.com>
ackend.h
ompiler_enums.h
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| ff4cfe07009ac0b0f07475ef2aa91d9aaf9ab291 |
30-Aug-2014 |
Junmo Park <junmoz.park@samsung.com> |
Fix SetupResourceMasks to pass correct parameters
Calling SetupTargetResourceMasks function with correct parameter.
SetupTargetResourceMasks(lir, flags, use_mask, def_mask) is correct order.
b/17369806
(cherry-picked from commit sha 2a09504334a3a3b4c47100197df0827cc6740433)
Change-Id: I49118c3f2d3d06fac83fa3d5014b7fdaff6a2b00
uick/mir_to_lir-inl.h
|
| f72fd02c4ea0f1aa610b8a4f9f51ef86c285b1cf |
03-Sep-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: disable GVN DO NOT MERGE" into lmp-dev
|
| 2a09504334a3a3b4c47100197df0827cc6740433 |
03-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix SetupResourceMasks to pass correct parameters"
|
| 4c4f4daafbac15b856da91118d9ea55c9eefa54b |
03-Sep-2014 |
buzbee <buzbee@google.com> |
Quick compiler: disable GVN DO NOT MERGE
Disable global value numbering optimization for lmp (but
keep on for master).
b/16398693
Change-Id: I125c588c987a81db54a15da1eec9dee2b009956f
rontend.cc
|
| 4a9467959d4693f805c39536eed3c3bc5e8bbfd8 |
03-Sep-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler, aarch64: Insane sanity checker"
|
| de0b996661351450fa4d918706c5322e001c29c9 |
27-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix read-out-of-bounds in the compiler
In case of a wide dalvik register, asking for the constant value
can lead to a read out of bounds.
Bug: 17302671
(cherry picked from commit ade731854d18839823e57fb2d3d67238c5467d15)
Change-Id: Ie1849cd67cc418c97cbd7a8524f027f9b66e4c96
ir_graph.h
uick/codegen_util.cc
|
| 4d05d931d3d608f5047e0d9dfb422df018ace716 |
03-Sep-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix read-out-of-bounds in the compiler" into lmp-dev
|
| aa839cc299acd0eaa21e80cc6da6142c5e2dec7e |
30-Aug-2014 |
Junmo Park <junmoz.park@samsung.com> |
Fix SetupResourceMasks to pass correct parameters
Calling SetupTargetResourceMasks function with correct parameter.
SetupTargetResourceMasks(lir, flags, use_mask, def_mask) is correct order.
Change-Id: I49118c3f2d3d06fac83fa3d5014b7fdaff6a2b00
Signed-off-by: Junmo Park <junmoz.park@samsung.com>
uick/mir_to_lir-inl.h
|
| f77e977b04f1a73a52ea7965789cbda39d7734c4 |
03-Sep-2014 |
buzbee <buzbee@google.com> |
Quick compiler, aarch64: Insane sanity checker
Fix bit-mask generation used in the sanity checking code
for long division by small constants via multiplication. The
failing case was a 64-bit wide mask. The macro was using the
desired width of the result as a shift count - and a left
shift of a 64-bit integer by 64 bits is undefined.
Note that the generated code is correct - it's just the sanity
checking code that was wrong.
Change-Id: Ic6654662f848d3caab2c3b1ef0d92fe2eb9673f4
uick/arm64/target_arm64.cc
|
| 7c7686e62d262f1823876cebb3700e20f967dd56 |
02-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Revert "Revert "ART: Prepare for ELF64."""
|
| f9b87b1eece0e03578c4d1b627f1d5e8691a539a |
02-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "ART: Prepare for ELF64.""
Fix was commited in "Fix frame size issue with 64-bit"
This reverts commit 7eebd95bddc7c6866ba29010d28b4f8251b43242.
Change-Id: I799b7fcab14ae24471d2f9d6d3a5e5cedd4aa7b8
uick/quick_compiler.cc
|
| 893600ce548fb4cf057e2bdcf8b305eae3338f7d |
01-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Revert "ART: Prepare for ELF64.""
|
| 7eebd95bddc7c6866ba29010d28b4f8251b43242 |
01-Sep-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "ART: Prepare for ELF64."
Build fails on arm64 with error message:
art/compiler/elf_writer_quick.cc:1083:1: error: the frame size of 2016 bytes is larger than 1728 bytes [-Werror=frame-larger-than=]
This reverts commit 45b8f1ab2782d02830c77751f883456de799dfb6.
Change-Id: I61b2e5f27ba4b2b32eacaec51fb5e5ed12fd8066
uick/quick_compiler.cc
|
| 59a004328f42c32026a79b59e8eae0f3bf85b59b |
30-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Address issues with kIntrinsicMinMaxDouble for x86"
|
| 5383613c5deab8d92dcfb85c1b034594394c7cca |
30-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Update CFG dumper to handle extended better"
|
| 45b8f1ab2782d02830c77751f883456de799dfb6 |
27-Aug-2014 |
Tong Shen <endlessroad@google.com> |
ART: Prepare for ELF64.
Make ElfWriterQuick a template class. No functionality change.
Change-Id: I62b60dc9795c4795027e80f0bee6b54622ea49e9
uick/quick_compiler.cc
|
| e5beb18ca08962ed271f4c1f703e0c52bc8805f3 |
14-Aug-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Address issues with kIntrinsicMinMaxDouble for x86
This patch fixes the following issues:
- Makes sure that invoke-static/range is considered for analysis
path that decides whether base of code register is needed.
- Invalidates the code pointer register in intrinsic implementations
of min/max for FP since generated code has diamond shape and Quick
does not correctly handle control flow merges.
- Reverts the clobbering of base of code register from constant
loading path since it reduces performance in linear code that
needs the register.
- Ensures that no assumption is made on whether base of code register
exists in cases like 64-bit where rip register may be used.
Change-Id: I96463ae1197e5cfa2a8bd3571163b38fb338a340
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
Signed-off-by: Haitao Feng <haitao.feng@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/fp_x86.cc
uick/x86/utility_x86.cc
|
| 1500e6fe209223f920cfbe6857dc4e2f0e0fc9ca |
23-Aug-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Update CFG dumper to handle extended better
Change-Id: I0df8ece13deadf247a425beac0c08b2be5d773f9
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
ompiler_enums.h
ir_graph.cc
ir_graph.h
|
| b41b93a2b7916fb56b50cc6180d80e8d86d78433 |
28-Aug-2014 |
buzbee <buzbee@google.com> |
Quick compiler: Fix MIPS build
b/16484538
In debug builds, the Quick compiler frequently runs a sanity checker
over the register pool. Among other things, it attempts to verify
consistent representation of register pairs. However, a register's
"wide" flag is meaningful only when the register pair is associated
with a Dalvik wide value (sreg != INVALID_SREG) rather than a temp
wide value.
The MIPS build was tripping over this bad assertion. Fixed here.
Note related cl/105461
(cherry-picked from commit sha 3a658077af2a931e5d7f6cd22b777c57112c19df)
Change-Id: Id726ff1ea0f5cbcc8dba6fa3aacb3fd4fc043a63
uick/ralloc_util.cc
|
| 3a658077af2a931e5d7f6cd22b777c57112c19df |
28-Aug-2014 |
buzbee <buzbee@google.com> |
Quick compiler: Fix MIPS build
In debug builds, the Quick compiler frequently runs a sanity checker
over the register pool. Among other things, it attempts to verify
consistent representation of register pairs. However, a register's
"wide" flag is meaningful only when the register pair is associated
with a Dalvik wide value (sreg != INVALID_SREG) rather than a temp
wide value.
The MIPS build was tripping over this bad assertion. Fixed here.
Note related cl/105461
Change-Id: Id726ff1ea0f5cbcc8dba6fa3aacb3fd4fc043a63
uick/ralloc_util.cc
|
| 2ddd175d74acc316293f5949746c637260437a49 |
26-Aug-2014 |
Yixin Shou <yixin.shou@intel.com> |
Add numerator check for integer divide and modulo
Implemented numerator == 0 optimization for integer divide and modulo
Change-Id: I6e3bff4a9f68d2790394f7df6106a948003a04c4
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
uick/x86/int_x86.cc
|
| ade731854d18839823e57fb2d3d67238c5467d15 |
27-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix read-out-of-bounds in the compiler
In case of a wide dalvik register, asking for the constant value
can lead to a read out of bounds.
Bug: 17302671
Change-Id: Ie1849cd67cc418c97cbd7a8524f027f9b66e4c96
ir_graph.h
uick/codegen_util.cc
|
| 8d0d03e24325463f0060abfd05dba5598044e9b1 |
07-Jun-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Change temporaries to positive names
Changes compiler temporaries to have positive names. The numbering now
puts them above the code VRs (locals + ins, in that order). The patch also
introduces APIs to query the number of temporaries, locals and ins.
The compiler temp infrastructure suffered from several issues
which are also addressed by this patch:
-There is no longer a queue of compiler temps. This would be polluted
with Method* when post opts were called multiple times.
-Sanity checks have been added to allow requesting of temps from BE
and to prevent temps after frame is committed.
-None of the structures holding temps can overflow because they are
allocated to allow holding maximum temps. Thus temps can be requested
by BE with no problem.
-Since the queue of compiler temps is no longer maintained, it is no
longer possible to refer to a temp that has invalid ssa (because it
was requested before ssa was run).
-The BE can now request temps after all ME allocations and it is guaranteed
to actually receive them.
-ME temps are now treated like normal VRs in all cases with no special
handling. Only the BE temps are handled specially because there are no
references to them from MIRs.
-Deprecated and removed several fields in CompilationUnit that saved
register information and updated callsites to call the new interface from
MIRGraph.
Change-Id: Ia8b1fec9384a1a83017800a59e5b0498dfb2698c
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
ompiler_ir.cc
ompiler_ir.h
rontend.cc
lobal_value_numbering.cc
lobal_value_numbering_test.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_optimization.cc
ortable/mir_to_gbc.cc
ortable/mir_to_gbc.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
sa_transformation.cc
reg_analysis.cc
|
| 2cdd2f2f4c18de88c0daeddec362c0471d823b0b |
27-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Added dirty flag to optimizations"
|
| bd25d4bff69e4775b7844d48630618b5ad8d3343 |
03-Jul-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Add capability for a pass to have options
This patch adds capability to have pass options. These are needed when a pass
has multiple flags that can be tweaked. The user is now allowed to pass those
options via command line.
Since passes are treated as singletons and they are immutable, the overridden
options provided by user are set on the compilation unit. Doing this way also
allows a selectivity system to tweak the option per compilation instead of
doing it globally (due to the single pass existing).
The following command line flags have been added:
--print-pass-options - This prints all passes that have options along with
their defaults.
--pass-options= - This is used to pass the overridden options in format of
PassName:PassOption:PassOptionSetting
Change-Id: Ib5156f5d2ff51a0c64c4ea0fa050bd2170663417
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ompiler_ir.cc
ompiler_ir.h
ass_driver.h
ass_driver_me.h
ass_driver_me_opts.cc
ass_driver_me_post_opt.cc
ass_me.h
|
| 09321dfb4803669ba6d6f3fef6363a1fd7202eea |
19-Jul-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Added dirty flag to optimizations
- Added a dirty flag to the PassMEDataHolder and use it to determine
if we want to perform the post-optimization passes or not.
Change-Id: I59a85f5198f9224d5fe8893397bfaf68a978d8f1
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
b_optimizations.cc
b_optimizations.h
ass.h
ass_driver_me_opts.cc
ass_me.h
ost_opt_passes.cc
ost_opt_passes.h
|
| b5bce7cc9f1130ab4932ba8e6917c362bf871f24 |
25-Jul-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Add non-temporal store support
Added non-temporal store support as a hint from the ME.
Added the implementation of the memory barrier
extended instruction that supports non-temporal stores
by explicitly serializing all previous store-to-memory instructions.
Change-Id: I8205a92083f9725253d8ce893671a133a0b6849d
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
ompiler_enums.h
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 88a6b4149415448b589f155df490ca7a13b01008 |
25-Aug-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix DCHECK
Cherry-pick from internal 532582
A DCHECK intended to verify the soundness of the mapping between
a wide Dalvik value and a pair of temp registers incorrectly fired
when the temp register pair was associated with a wide temporary
(i.e. - when (SReg() == INVALID_SREG)).
In this particular situation, the wideness flag is meaningful only when
there is an associated valid vreg. Code rearranged to only perform
the DCHECK and reset the partner's wideness bit when we're dealing with
a live wide value.
b/16484538
Change-Id: I3b8a7bebc5d918c65ea56ae8db0a8a5cd8003386
uick/ralloc_util.cc
|
| 1ff1747e71f0e1b3dbb181b52c2b4880bfa019fc |
26-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Extending FlagsOf"
|
| 28b066ad8baa23f918e99d2e9b4771c00b5a3eca |
25-Aug-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix DCHECK
A DCHECK intended to verify the soundness of the mapping between
a wide Dalvik value and a pair of temp registers incorrectly fired
when the temp register pair was associated with a wide temporary
(i.e. - when (SReg() == INVALID_SREG)).
In this particular situation, the wideness flag is meaningful only when
there is an associated valid vreg. Code rearranged to only perform
the DCHECK and reset the partner's wideness bit when we're dealing with
a live wide value.
b/16484538
Change-Id: I3b8a7bebc5d918c65ea56ae8db0a8a5cd8003386
uick/ralloc_util.cc
|
| fb0ea2df9a52e5db18e1aa85da282938bbd92f2e |
29-Jul-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Extending FlagsOf
Modified FlagsOf to handle extended flags.
Change-Id: I9e47e0c42816136b2b53512c914200dd9dd11376
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ocal_value_numbering.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
reg_analysis.cc
|
| 37f05ef45e0393de812d51261dc293240c17294d |
17-Jul-2014 |
Fred Shih <ffred@google.com> |
Reduced memory usage of primitive fields smaller than 4-bytes
Reduced memory used by byte and boolean fields from 4 bytes down to a
single byte and shorts and chars down to two bytes. Fields are now
arranged as Reference followed by decreasing component sizes, with
fields shuffled forward as needed.
Bug: 8135266
Change-Id: I65eaf31ed27e5bd5ba0c7d4606454b720b074752
ex_to_dex_compiler.cc
ir_graph.cc
uick/arm64/int_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
uick/x86/utility_x86.cc
|
| 53c913bb71b218714823c8c87a1f92830c336f61 |
13-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Clean up compiler
Clean up the compiler: less extern functions, dis-entangle
compilers, hide some compiler specifics, lower global includes.
Change-Id: Ibaf88d02505d86994d7845cf0075be5041cc8438
b_optimizations.h
ompiler_internals.h
ompiler_ir.cc
ompiler_ir.h
rontend.cc
rontend.h
ir_graph.cc
ir_graph.h
ir_optimization.cc
ortable/mir_to_gbc.h
ost_opt_passes.h
uick/arm/backend_arm.h
uick/arm/codegen_arm.h
uick/arm/target_arm.cc
uick/arm64/backend_arm64.h
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/dex_file_method_inliner.cc
uick/mips/backend_mips.h
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mir_to_lir.h
uick/quick_compiler.cc
uick/quick_compiler.h
uick/x86/backend_x86.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
reg_analysis.cc
|
| e18aa4316eb9a15cd6b1051f27a1ce49967c170e |
23-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Support MIRGraph constant interface"
|
| d04d309276a6d35b34ff9805de3754299bbde4a9 |
04-Aug-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Support MIRGraph constant interface
-Adds a helper to be able to ask for a wide constant.
-Allows MIRGraph to provide interface to set constants.
Change-Id: Id282ee1604a0bd0bce6f495176d6bca35dcd5a00
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_graph.h
ir_optimization.cc
|
| a37ad7a6caad2e0a83c72c1103015202cbcaf1a4 |
22-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "GetDalvikDisassembly should work even without SSA info"
|
| 954c7ea1f72780510753524706111d1a2b26d9cb |
22-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Fix frontend to allow possibility of multiple code units"
|
| 651c967583bd267456f4d4beb18de06f9aeec679 |
22-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "AArch64: Improve MIR to LIR translation for abs"
|
| 20acd5b032870564537b81b9801f6afee499186d |
22-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Remove a BasicBlock's fall_through pointer in Hide()"
|
| b289d2c7bee5d81dcbd97964cc4dfbfb514e7cb6 |
22-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Implement kMirOpNullCheck"
|
| 00b3024b350afef115bddea712705bdb4877ac11 |
21-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "x86: A couple of minor changes for String.indexOf() inlining"
|
| 0f3e4989b055bfa0bad3e4fad2f4d1a8b5a09901 |
21-Aug-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
GetDalvikDisassembly should work even without SSA info
It is good if GetDalvikDisassembly can dump MIR even if
SSA register info is not available. Without this patch it
crashes.
Change-Id: I704c28c891cd2580a7819f7fd972167c3bf67ddc
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
ir_graph.cc
|
| f588b50986fe34cba26fc3ff3100af384c081dba |
18-Jun-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Remove a BasicBlock's fall_through pointer in Hide()
Remove the fall_through link that a BasicBlock has to its child when
calling its Hide function. Useful for removing the visible link that is
there when we dump the CFG.
Change-Id: Ie82c48b195d1d62e2984d284dcc29ed7d7444db2
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ir_graph.cc
|
| e77493c7217efdd1a0ecef521a6845a13da0305b |
21-Aug-2014 |
Ian Rogers <irogers@google.com> |
Make common BitVector operations inline-able.
Change-Id: Ie25de4fae56c6712539f04172c42e3eff57df7ca
ir_graph.cc
ir_optimization.cc
sa_transformation.cc
|
| 09ae022f55ab27edf4802baf7a05e76d7dc823a9 |
08-Jul-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Fix frontend to allow possibility of multiple code units
This patch addresses a potential problem in frontend which refers
to the CompilationUnit's code unit. However, a MIRGraph may have
multiple code units and thus it makes sense to refer to the current
one being handled.
Change-Id: I69ca7b6056652109c969e7c583fc223e45315c96
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_graph.cc
|
| 7642324bc8a5c839c669aebbb1fba61c05418651 |
04-Aug-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Implement kMirOpNullCheck
The semantics of kMirOpNullCheck is to check object for null and
throw exception in that case. However, the implementation for it
is empty. This has been changed and appropriate dataflow have been
added to correctly reflect behavior.
In order to allow testing of implementation, the SpecialMethodInliner
has been updated to get rid of invoke and use this instead. This helps
all optimizations which do not check the MIR_INLINED flag because
when invoke is left in, they believe that invoke will still be done.
Change-Id: I62e425e42bdbc6357246fb949db5f79de73cf358
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ompiler_enums.h
ir_dataflow.cc
uick/dex_file_method_inliner.cc
uick/mir_to_lir.cc
|
| 9a8a506b1cd639ad4126c19530cd206d8d3923c3 |
07-Aug-2014 |
Martyn Capewell <martyn.capewell@arm.com> |
AArch64: Improve MIR to LIR translation for abs
Improve translation by using a shorter and more efficient sequence for integer
abs, and replacing UBFM with AND for FP abs in integer registers.
Change-Id: Ifc39cd7806ed637d5cfc3284c435b5d501047eb5
Signed-off-by: Alexandre Rames <alexandre.rames@arm.com>
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/mir_to_lir.h
|
| 5d13f12f3454f07eb83b06b47e884a290e3a7303 |
20-Aug-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix Arm64 inline locking code
The Arm64 monitor enter code was incorrectly comparing the
thread ID to zero rather than the lock value to determine if the
inline fast path was doable. As a result, we ended up always
using the out-of-line case.
internal b/16707253
Change-Id: I499530da84beecf1f3f5c5ebb666e3eb12599ac0
uick/arm64/call_arm64.cc
|
| 4efefc3b900dfc83ffd098b0c296c835b6837925 |
20-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Improve GVN performance when merging null-checked values."
|
| 2d2365cdaa54583b47c18a6506ccd0fd723ab6d0 |
19-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Improve GVN performance when merging null-checked values.
And ignore the limit on maximum number of processed basic
blocks once the GVN has actually converged and we're just
applying optimizations.
Bug: 16398693
Change-Id: Ie5aa0386ea4e0e9ae2bbf13963e2424e1713b22f
lobal_value_numbering.cc
lobal_value_numbering.h
ocal_value_numbering.cc
ocal_value_numbering.h
|
| 9be4be5882a05b3aa6ec822901ff4092203d8dc5 |
19-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "AArch64: Add tbz/tbnz and tst."
|
| 5d7cdec7527f8043bf15e23a0041c40156727243 |
18-Aug-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Add tbz/tbnz and tst.
Since the branch offset supported by tbz/tbnz is quite small(-32k ~ +32k),
it will be replaced by tst and beq/bneq in the fix-up stage if the branch
offset is too large.
Change-Id: I4cace06bec6425e0f2e1f5f7c471eec08d06bca6
ompiler_enums.h
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
|
| a846c1ac65b197844380b8d28377a850dfa1fc94 |
20-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "X86: Fix alias info in GenInlinedIndexOf()." into lmp-dev
|
| b5874a47a4d2c4d2971116b031b4068021ffda05 |
19-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
X86: Fix alias info in GenInlinedIndexOf().
For 32-bit X86, GenInlinedIndexOf() pushes and pops EDI. In
one branch it then calls Load32Disp() with adjusted stack
offset. That calculates wrong alias_info for the generated
insn. If left unfixed, this could confuse load hoisting.
Bug: 17128502
(cherry picked from commit 74de63bb1cc275b411cae28a96f9b3a78b939bc2)
Change-Id: I5dc82b7aae9e9655e75843a952b8ebb04269f46b
uick/x86/target_x86.cc
|
| c6a62592836612b09ff1a8021e49b1328d85493b |
20-Aug-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: fix Arm64 inline locking code" into lmp-dev
|
| ebc56bd68743dfffcfeb04f938181b18efaed85c |
20-Aug-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix Arm64 inline locking code
The Arm64 monitor enter code was incorrectly comparing the
thread ID to zero rather than the lock value to determine if the
inline fast path was doable. As a result, we ended up always
using the out-of-line case.
This fix delivers a 6% improvement to DeltaBlue.
b/16707253
Change-Id: I499530da84beecf1f3f5c5ebb666e3eb12599ac0
uick/arm64/call_arm64.cc
|
| 74de63bb1cc275b411cae28a96f9b3a78b939bc2 |
19-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
X86: Fix alias info in GenInlinedIndexOf().
For 32-bit X86, GenInlinedIndexOf() pushes and pops EDI. In
one branch it then calls Load32Disp() with adjusted stack
offset. That calculates wrong alias_info for the generated
insn. If left unfixed, this could confuse load hoisting.
Bug: 17128502
Change-Id: I0ea07b8f5e25410e290304f662d5fd5bf66c0933
uick/x86/target_x86.cc
|
| dfa7a6c8711623bf20aad58f57ae980b497ef4d7 |
18-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Disable load/store elimination. DO NOT MERGE
The optimization has several issues and it has been
effectively disabled by
https://android-review.googlesource.com/103511
Disable it completely to avoid wasting compilation time.
Bug: 16862804
Change-Id: I42f69ae64170dc44f5fd6455b6a51c9bd3f93672
rontend.cc
|
| 76bc718dc2cf0279ec5afd08c3a82b6ad61756d8 |
18-Aug-2014 |
Andreas Gampe <agampe@google.com> |
Merge "[MIPS] Fix the code generated by GenSelectConst32"
|
| aa1ed01d119ee6d93e6254789c79246e91fcec32 |
16-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART source line debug info in OAT files"
|
| e3ea83811d47152c00abea24a9b420651a33b496 |
08-Aug-2014 |
Yevgeny Rouban <yevgeny.y.rouban@intel.com> |
ART source line debug info in OAT files
OAT files have source line information enough for ART runtime needs like
jump to/from interpreter and thread suspension. But this information
is not enough for finer grained source level debugging and low-level
profiling (VTune or perf).
This patch adds to OAT files two additional sections:
.debug_line - DWARF formatted Elf32 section with detailed source line
information (mapping from native PC to Java source lines).
In addition to the debugging symbols added using the dex2oat option
--include-debug-symbols, the source line information is added to
the section .debug_line.
The source line info can be read by many Elf reading tools like objdump,
readelf, dwarfdump, gdb, perf, VTune, ...
gdb can use this debug line information in x86. In 64-bit mode
the information can be used if the oat file is mapped in the lower
address space (address has higher 32 bits zeroed). Relocation works.
Testing:
1. art/test/run-test --host --gdb [--64] 001-HelloWorld
2. in gdb: break Main.java:19
3. in gdb: break Runtime.java:111
4. in gdb: run - stops at void java.lang.Runtime.<init>()
5. in gdb: backtrace - shows call stack down to main()
6. in gdb: continue - stops at void Main.main() (only in 32-bit mode)
7. in gdb: backtrace - shows call stack down to main()
8. objdump -W <oat-file> - addresses are from VMA range of .text
section reported by objdump -h <file>
9. dwarfdump -ka <oat-file> - no errors expected
Size of aosp-x86-eng boot.oat increased by 11% from 80.5Mb to 89.2Mb
with two sections added .debug_line (7.2Mb) and .rel.debug (1.5Mb).
Change-Id: Ib8828832686e49782a63d5529008ff4814ed9cda
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
uick/codegen_util.cc
uick/mir_to_lir.h
uick/x86/target_x86.cc
|
| 08f8d4cbc5e673a2a4b6eda08e3133c7bb626772 |
14-Aug-2014 |
Raghu Gandham <raghu.gandham@imgtec.com> |
[MIPS] Fix the code generated by GenSelectConst32
Change-Id: Icc1d0449566435200a10fa3ca5489f78d122bc89
uick/mips/int_mips.cc
|
| 06839f868c9c4bb1f2f6333f9e88a560e80bcad8 |
15-Aug-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: Use RegClassBySize() for field accesses
This patch optimizes x86_64 field accesses to use kAnyReg whenever possible
via RegClassBySize(). Previously, using kCoreReg is too strict.
Change-Id: I55a48765b9bfe6b11c4b09f85c4eb08a6e269f98
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/x86/target_x86.cc
|
| 03c9785a8a6d712775cf406c4371d0227c44148f |
14-Aug-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Reduce stack usage for overflow checks""
Fixes stack protection issue.
Fixes mac build issue.
This reverts commit 83b1940e6482b9d8feba5c492507735686650ea5.
Change-Id: I7ba17252882b23a740bcda2ea94aacf398255406
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/mips/call_mips.cc
uick/x86/call_x86.cc
|
| e470a02792ce584fe0ff1b9a7dd6aebe62ca9be5 |
14-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix intrinsic Math.abs(double) for ARM." into lmp-dev
|
| 397297f92ff3004cfcd623690d98bc49edf8c032 |
14-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Fix intrinsic Math.abs(double) for ARM.
Bug: 16930909
(cherry picked from commit a5f90b6f0f5b33487e71eaeb05508555f17dcf30)
Change-Id: I3ee40ffbeeabf53c72ea5781d02cda1b92b13289
uick/arm/fp_arm.cc
|
| 83b1940e6482b9d8feba5c492507735686650ea5 |
14-Aug-2014 |
Dave Allison <dallison@google.com> |
Revert "Reduce stack usage for overflow checks"
This reverts commit 63c051a540e6dfc806f656b88ac3a63e99395429.
Change-Id: I282a048994fcd130fe73842b16c21680053c592f
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/mips/call_mips.cc
uick/x86/call_x86.cc
|
| 63c051a540e6dfc806f656b88ac3a63e99395429 |
26-Jul-2014 |
Dave Allison <dallison@google.com> |
Reduce stack usage for overflow checks
This reduces the stack space reserved for overflow checks to 12K, split
into an 8K gap and a 4K protected region. GC needs over 8K when running
in a stack overflow situation.
Also prevents signal runaway by detecting a signal inside code that
resulted from a signal handler invokation. And adds a max signal count to
the SignalTest to prevent it running forever.
Also reduces the number of iterations for the InterfaceTest as this was
taking (almost) forever with the --trace option on run-test.
Bug: 15435566
Change-Id: Id4fd46f22d52d42a9eb431ca07948673e8fda694
Conflicts:
compiler/optimizing/code_generator_x86_64.cc
runtime/arch/x86/fault_handler_x86.cc
runtime/arch/x86_64/quick_entrypoints_x86_64.S
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/mips/call_mips.cc
uick/x86/call_x86.cc
|
| c739de01b905729b8587003a52a55b62358e979d |
13-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "Avoid use of std::string where we have const char*." into lmp-dev
|
| cb6b0f31ede2275e79e6199ec391147585a37a2a |
12-Aug-2014 |
Ian Rogers <irogers@google.com> |
Avoid use of std::string where we have const char*.
Removing the ClassHelper caused std::string creation for all calls to
Class::GetDescriptor and a significant performance regression. Make the
std::string an out argument so the caller can maintain it and its life time
while allowing GetDescriptor to return the common const char* case.
Don't generate GC maps when compilation is disabled.
Remove other uses of std::string that are occuring on critical paths.
Use the cheaper SkipClass in CompileMethod in CompilerDriver.
Specialize the utf8 as utf16 comparison code for the common shorter byte
encoding.
Force a bit of inlining, remove some UNLIKELYs (they are prone to pessimizing
code), add some LIKELYs.
x86-64 host 1-thread interpret-only of 57 apks:
Before: 29.539s
After: 23.467s
Regular compile:
Before: 1m35.347s
After: 1m20.056s
Bug: 16853450
Change-Id: Ic705ea24784bee24ab80084d06174cbf87d557ad
Conflicts:
runtime/utils.cc
rontend.cc
erification_results.cc
erification_results.h
|
| b0f05b9654eb005bc8c8e15f615a7f5a312f640c |
17-Jul-2014 |
Dave Allison <dallison@google.com> |
Add implicit checks for x86_64 architecture.
This combines the x86 and x86_64 fault handlers into one. It also
merges in the change to the entrypoints for X86_64.
Replaces generic instruction length calculator with one that only
works with the specific instructions we use.
Bug: 16256184
Change-Id: I1e8ab5ad43f46060de9597615b423c89a836035c
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/x86/target_x86.cc
|
| f40f890ae3acd7b3275355ec90e2814bba8d4fd6 |
14-Aug-2014 |
Yixin Shou <yixin.shou@intel.com> |
Implement inlined shift long for 32bit
Added support for x86 inlined shift long for 32bit
Change-Id: I6caef60dd7d80227c3057fd6f64b0ecb11025afa
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/x86_lir.h
|
| 6324ca4706de44b75e5b8ba55473766809c4f132 |
15-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Inline implementation of min() and max() for long in x86"
|
| 4ab6f50c6de9d77e03ba8eb9a3c19aa06cae0917 |
08-Aug-2014 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
ART: Inline implementation of min() and max() for long in x86
Change-Id: I49de0ee10f79ce49245d6a6c2cd06c5a46b45dca
uick/x86/int_x86.cc
|
| b74ff132f217776c1ab698712bc2dbc526297288 |
14-Aug-2014 |
Dave Allison <dallison@google.com> |
Merge "Reduce stack usage for overflow checks"
|
| 648d7112609dd19c38131b3e71c37bcbbd19d11e |
26-Jul-2014 |
Dave Allison <dallison@google.com> |
Reduce stack usage for overflow checks
This reduces the stack space reserved for overflow checks to 12K, split
into an 8K gap and a 4K protected region. GC needs over 8K when running
in a stack overflow situation.
Also prevents signal runaway by detecting a signal inside code that
resulted from a signal handler invokation. And adds a max signal count to
the SignalTest to prevent it running forever.
Also reduces the number of iterations for the InterfaceTest as this was
taking (almost) forever with the --trace option on run-test.
Bug: 15435566
Change-Id: Id4fd46f22d52d42a9eb431ca07948673e8fda694
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/mips/call_mips.cc
uick/x86/call_x86.cc
|
| a5f90b6f0f5b33487e71eaeb05508555f17dcf30 |
14-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Fix intrinsic Math.abs(double) for ARM.
Bug: 16930909
Change-Id: I1210cb3aa82a73b9e4d4df1ceddeff78ac1df42b
uick/arm/fp_arm.cc
|
| 6c6c6f6683cbbb180b8b8c8f55886b067320e1e8 |
13-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "Avoid use of std::string where we have const char*."
|
| 1ff3c98775a4577cf053dba9a0c2d5c21c07b298 |
12-Aug-2014 |
Ian Rogers <irogers@google.com> |
Avoid use of std::string where we have const char*.
Removing the ClassHelper caused std::string creation for all calls to
Class::GetDescriptor and a significant performance regression. Make the
std::string an out argument so the caller can maintain it and its life time
while allowing GetDescriptor to return the common const char* case.
Don't generate GC maps when compilation is disabled.
Remove other uses of std::string that are occuring on critical paths.
Use the cheaper SkipClass in CompileMethod in CompilerDriver.
Specialize the utf8 as utf16 comparison code for the common shorter byte
encoding.
Force a bit of inlining, remove some UNLIKELYs (they are prone to pessimizing
code), add some LIKELYs.
x86-64 host 1-thread interpret-only of 57 apks:
Before: 29.539s
After: 23.467s
Regular compile:
Before: 1m35.347s
After: 1m20.056s
Bug: 16853450
Change-Id: Ic705ea24784bee24ab80084d06174cbf87d557ad
rontend.cc
erification_results.cc
erification_results.h
|
| 8c914c02415d7673f75166e1f1efdcdc7fcadc65 |
28-Jul-2014 |
Yixin Shou <yixin.shou@intel.com> |
Implement GenInlinedReverseBits
Added support for x86 inlined version of reverse method of int and long
Change-Id: I7dbdc13b4afedd56557e9eff038a31517cdb1843
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| f1770fdeb0911d11489b7d495ce31420ac0cdc61 |
12-Aug-2014 |
Junmo Park <junmoz.park@samsung.com> |
Fix missing operation in CombineBlocks
explicit throw, conditional branch flags also need to be moved.
There are no quick compiler bugs before this CL.
So regression test is not necessary.
Change-Id: I5f7c0f261fff5f7a46b32763096ab4fe85b2c0c0
Signed-off-by: Junmo Park <junmoz.park@samsung.com>
ir_optimization.cc
|
| 8bd698fb785b58302be684efcbb24a0b8c6535d7 |
01-Aug-2014 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
x86: A couple of minor changes for String.indexOf() inlining
1. Removed sequence of FlushReg + Clobber + LockTemp for
particular registers and added FlushAllRegs. I believe it will
make sources more readable and not affect the performance
too much.
2. Made MarkPossibleNullPointerException call unconditional
Change-Id: I817f77718e15ec76cae35cf9fb04c0e5dcfb2d16
uick/x86/target_x86.cc
|
| 90223cc2e0bfb5a2b55e9ffed896ef327b9f3d2e |
04-Aug-2014 |
Junmo Park <junmoz.park@samsung.com> |
Fix missing operation in SplitBlock
If block which contains a conditional branch is divided two,
explicit throw, conditional branch flag needs to go to the bottom block.
Change-Id: I17a74f469d0c61fb30daa43fdb967ea485b2a6c3
Signed-off-by: Junmo Park <junmoz.park@samsung.com>
ir_graph.cc
|
| 8c18c2aaedb171f9b03ec49c94b0e33449dc411b |
06-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Generate chained compare-and-branch for short switches
Refactor Mir2Lir to generate chained compare-and-branch sequences
for short switches on all architectures.
Bug: 16241558
(cherry picked from commit 48971b3242e5126bcd800cc9c68df64596b43d13)
Change-Id: I0bb3071b8676523e90e0258e9b0e3fd69c1237f4
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/gen_common.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| e70f179aca4f13b15be8a47a4d9e5b6c2422c69a |
09-Aug-2014 |
Haitao Feng <haitao.feng@intel.com> |
ART: Fix two small DumpLIRInsn issues for x86_64 port.
Change-Id: I81ef32380bfc73d6c2bfc37a7f4903d912a5d9c8
Signed-off-by: Haitao Feng <haitao.feng@intel.com>
uick/x86/assemble_x86.cc
uick/x86/target_x86.cc
|
| fa9c8ec37c66574654e448513e1bb59af7cb9365 |
07-Aug-2014 |
Zheng Xu <zheng.xu@arm.com> |
Add arraycopy intrinsic for arm and arm64.
Implement intrinsic for
java.lang.System.arraycopy(char[], int, char[], int, int).
Bug: 16241558
(cherry picked from commit 947717a2b085f36ea007ac64f728e19ff1c8db0b)
Change-Id: I8199f5c9ce9827f869f0f93aaff7ec359a84d922
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
|
| 7204c04dd86ae8ce05690e38737b2abf017a0a69 |
11-Jun-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
AArch64: Implicit StackOverflow/NPE/Suspend checks.
This implements implicit stack overflow checks and null pointer exceptions
for AArch64. Suspend checks are implemented but not switched on yet.
Bug: 16256184
Change-Id: I2eb076f2c0c9d94793d5a898fea49cf409b4eb66
Signed-off-by: Stuart Monteith <stuart.monteith@arm.com>
uick/arm64/call_arm64.cc
|
| a7894cdb063edb88f1420a42207e0c4bd27ab4f9 |
06-Aug-2014 |
Dave Allison <dallison@google.com> |
Fix checks for kLiteral in local optimizations.
The check for kLiteral (literal load) just checked the kLiteral
bit in the def mask. The kEncodeAll mask has the kLiteral bit
set so this check was triggering. The fix is to check for
only the kLiteral bit being set and no other special bits.
The semantics of the special bits in the use/def mask is that
only one of them can be set at the same time.
Bug: 16824330
Change-Id: I0f1c1157e017870414ffef11767e5433d1fd4401
uick/local_optimizations.cc
|
| 947717a2b085f36ea007ac64f728e19ff1c8db0b |
07-Aug-2014 |
Zheng Xu <zheng.xu@arm.com> |
Add arraycopy intrinsic for arm and arm64.
Implement intrinsic for
java.lang.System.arraycopy(char[], int, char[], int, int).
Bug: 16241558
Change-Id: I558a9c4403d0c3abb07af1511d394981bbfcabc5
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
|
| 52fed5a8f31dac64d09ede03703f40b712a7d766 |
07-Aug-2014 |
Andreas Gampe <agampe@google.com> |
Merge "Emit CFI for x86 & x86_64 JNI compiler."
|
| dfd3b47813c14c5f1607cbe7b10a28b1b2f29cbc |
17-Jul-2014 |
Dave Allison <dallison@google.com> |
Add implicit checks for x86_64 architecture.
This combines the x86 and x86_64 fault handlers into one. It also
merges in the change to the entrypoints for X86_64.
Replaces generic instruction length calculator with one that only
works with the specific instructions we use.
Bug: 16256184
Change-Id: I1e8ab5ad43f46060de9597615b423c89a836035c
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/x86/target_x86.cc
|
| 547cdfd21ee21e4ab9ca8692d6ef47c62ee7ea52 |
05-Aug-2014 |
Tong Shen <endlessroad@google.com> |
Emit CFI for x86 & x86_64 JNI compiler.
Now for host-side x86 & x86_64 ART, we are able to get complete stacktrace with even mixed C/C++ & Java stack frames.
Testing:
1. art/test/run-test --host --gdb [--64] --no-relocate 005
2. In gdb, run 'b art::Class_classForName' which is implementation of a Java native method, then 'r'
3. In gdb, run 'bt'. You should see stack frames down to main()
Change-Id: I2d17e9aa0f6d42d374b5362a15ea35a2fce96302
uick/codegen_util.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| 4b6d27c2079e246cdeb56dca6648539a16493dca |
05-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "x86: Fix assembler for Pextr"
|
| 70c3e111652e8031351b31b9fcb704c2925a711d |
07-Aug-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Fix analysis_attributes_ to update missing definitions."
|
| 81550fa92a02f6c656d13b12dc188fc73ac0fb39 |
07-Aug-2014 |
Dave Allison <dallison@google.com> |
Merge "AArch64: Implicit StackOverflow/NPE/Suspend checks."
|
| 4fc785398707ede68f29768748b7fe5fa39dde24 |
07-Aug-2014 |
Fred Shih <ffred@google.com> |
Fixed build breakage due to incorrect class TypeId.
Fixed incorrect type id being inserted in code buffer and got rid of
inefficient pointer wrapping in LoadClassType.
Change-Id: I7ee1d957ebcd816445c26199723ac50787d926d7
uick/codegen_util.cc
|
| d5c78f44dc53ef9fda47a95ad3e9799be850c2b2 |
11-Jun-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
AArch64: Implicit StackOverflow/NPE/Suspend checks.
This implements implicit stack overflow checks and null pointer exceptions
for AArch64. Suspend checks are implemented but not switched on yet.
Change-Id: I2eb076f2c0c9d94793d5a898fea49cf409b4eb66
Signed-off-by: Stuart Monteith <stuart.monteith@arm.com>
uick/arm64/call_arm64.cc
|
| 57cd9d3bda952ee2c2cf977fb1e26a0a954e1bab |
07-Aug-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Added support for patching classes from different dex files."
|
| e7f82e2515f47f3c3292281312d7031a34a58ffc |
06-Aug-2014 |
Fred Shih <ffred@google.com> |
Added support for patching classes from different dex files.
Added support for class patching from different dex files and moved
ScopedObjectAccess from the quick compiler to driver. Slight refactoring
for clarity.
Bug: 16656190
Change-Id: I107fcbce75db42ca61321ea1c5d5f236680a1b3d
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| b9dbab627bdc3570d5f41cfd6de80ff3b70e1783 |
06-Aug-2014 |
Fred Shih <ffred@google.com> |
Revert "Temporary fix for bad LIR generation in GenInlinedGet."
This reverts commit eb76e11d836ea953b4e40a28e3e69d3b0f4c86fa.
Bug: 16656190
Change-Id: Ie2dd58436b28e79214ef3a7c7651f16fe46a60e8
uick/gen_invoke.cc
|
| f768db4c1cb7ec9374e203305cf3582f32147302 |
05-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "X86: Assembler: Correct r8_form for some cases"
|
| adc73cbe869f9560cf84bda2e953a2b267b1438f |
06-Aug-2014 |
Dave Allison <dallison@google.com> |
Fix checks for kLiteral in local optimizations.
The check for kLiteral (literal load) just checked the kLiteral
bit in the def mask. The kEncodeAll mask has the kLiteral bit
set so this check was triggering. The fix is to check for
only the kLiteral bit being set and no other special bits.
The semantics of the special bits in the use/def mask is that
only one of them can be set at the same time.
Bug: 16824330
Change-Id: I0f1c1157e017870414ffef11767e5433d1fd4401
uick/local_optimizations.cc
|
| cf73835af1421b3346a180c4eb2236d373bf2f2f |
07-Aug-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Revert "Temporary fix for bad LIR generation in GenInlinedGet.""
|
| 79273802f2b788bcd3eb76edf4df1bcaa57f886f |
06-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework CFA frame initialization and writing code
Move eh_frame initialization code and CFI writing code to
elf_writer_quick to remove hard-wired dependencies on specific
Quick-compiler backends.
Change-Id: I27ee8ce7245da33a20c90e0086b8d4fd0a2baf4d
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| 1b192268f167f603fc372f02f9067f3ce5d82daf |
06-Aug-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Generate chained compare-and-branch for short switches"
|
| 48971b3242e5126bcd800cc9c68df64596b43d13 |
06-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Generate chained compare-and-branch for short switches
Refactor Mir2Lir to generate chained compare-and-branch sequences
for short switches on all architectures.
Change-Id: Ie2a572ae69d462ba68a119e9fb93ae538cddd08f
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/gen_common.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| f6e8d0304d0b0024f1af8e63c2a3a3ad78761d59 |
05-Aug-2014 |
Ian Rogers <irogers@google.com> |
Merge "x86_64: Load double constant using core register"
|
| 0e63ce19bdb04d31180d7eb4a8bf6605333ade5a |
10-Jul-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
x86_64: Load double constant using core register
This changes the double const loading scheme for x86_64 in order to
reduce number of memory accesses.
Change-Id: If6ee34b890287ed616ca4ea5d1c13f06a06293a9
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/x86/utility_x86.cc
|
| 8081d2b8d7a743729557051d0294e040e61c747a |
31-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Create allocator adapter for using Arena in std containers.
Create ArenaAllocatorAdapter, similar to the existing
ScopedArenaAllocatorAdapter, for allocating memory for
standard containers via the ArenaAllocator. Add the ability
to specify allocation kind rather than just kArenaAllocSTL
to both adapters. Move the scoped arena allocator to the
scoped_arena_containers.h header file.
Define template aliases for containers using the new adapter
and change a few MIRGraph and Mir2Lir members to use them.
Change-Id: I9bbc50248e0fed81729497b848cb29bf68444268
ir_graph.cc
ir_graph.h
uick/codegen_util.cc
uick/mir_to_lir.h
|
| 6175442a246cded6a9caae4658a0a1dc7cf49071 |
05-Aug-2014 |
Brian Carlstrom <bdc@google.com> |
Merge changes Ibe92d8b5,I9bada598
* changes:
Make system use patchoat to relocate during runtime.
Temporary fix for bad LIR generation in GenInlinedGet.
|
| eb76e11d836ea953b4e40a28e3e69d3b0f4c86fa |
30-Jul-2014 |
Alex Light <allight@google.com> |
Temporary fix for bad LIR generation in GenInlinedGet.
In GenInlinedGet we will sometimes try to load a class directly. If
we are doing that and find one, but cannot get the direct pointer
(due to image compilation or including patch information) we might
end up generating incorrect patching code due to the changing of the
cu_->dex_file attribute.
Bug: 16656190
Change-Id: I9bada598bf4fd972d6164163eedd4a496da306d6
uick/gen_invoke.cc
|
| 5a5e85693b1d5952d88377be5826068b67b0dcec |
18-Jul-2014 |
DaniilSokolov <daniil.y.sokolov@intel.com> |
ART: Enable x86_64 bit support for intrinsic for System.arraycopy(char[], ..)
Implements x86_64 support for intrinsic for java.lang.System.arraycopy(char[], int, char[], int, int).
With this fix the intrinsic works on x86 and x86_64 architectures.
Change-Id: Icc2889ccd0cf7d821522abb7437893e3149e7c99
Signed-off-by: Daniil Sokolov <daniil.y.sokolov@intel.com>
uick/x86/target_x86.cc
|
| c76c614d681d187d815760eb909e5faf488a3c35 |
05-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Refactor long ops in quick compiler
Make GenArithOpLong virtual. Let the implementation in gen_common be
very basic, without instruction-set checks, and meant as a fall-back.
Backends should implement and dispatch to code for better implementations.
This allows to remove the GenXXXLong virtual methods from Mir2Lir, and
clean up the backends (especially removing some LOG(FATAL) implementations).
Change-Id: I6366443c0c325c1999582d281608b4fa229343cf
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 2bc477043b6ab2d7b4719ba8debf0a6a5b10c225 |
31-Jul-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Set REG0_USED on X86 Set8R instruction
Since this instruction only affects the low byte of the register, it is
preceded by an XOR to zero the upper 3 bytes. Set8R isn't marked as
using operand 0 as an input. In practice, this works for now, as the
Xor sets the CC and Set8R uses the CC (although not that of the Xor, but
of a Cmp generally).
This just marks REG0 as using the previous contents of the register, as
it is modifying only 1 byte of 4.
Change-Id: I7a69cbdb06979da5d5d2ae17fabd7c22c5a17701
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
|
| cf8184164650d7686b9f685850463f5976bc3251 |
24-Jul-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: Fix Test32RM
This patch fixes Test32RM use flags and the format.
Change-Id: I486cb7f27e65caeefccbd3bbcc38257ddca033c8
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/x86/assemble_x86.cc
|
| c763e350da562b0c6bebf10599588d4901140e45 |
04-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Implement InexpensiveConstant methods.
Implement IsInexpensiveConstant and friends for A64.
Also extending the methods to take the opcode with respect to which
the constant is inexpensive. Additionally, logical operations (i.e.
and, or, xor) can now handle the immediates 0 and ~0 (which are not
logical immediates).
Change-Id: I46ce1287703765c5ab54983d13c1b3a1f5838622
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
|
| e1fa1dd6924e53d10fbf9a2d8d4f7aa4de2d7fc0 |
04-Aug-2014 |
Junmo Park <junmoz.park@samsung.com> |
Fix analysis_attributes_ to update missing definitions.
There are some missing definitions for supporting vector opcodes.
Change-Id: Ifcddb8b8b7d9a6e93902864488f61721e65da972
Signed-off-by: Junmo Park <junmoz.park@samsung.com>
ir_analysis.cc
|
| 2eba1fa7e9e5f91e18ae3778d529520bd2c78d55 |
31-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add inlining support for ceil(), floor(), rint(), round()
This patch adds inlining support for the following Math, StrictMath
methods in the ARM64 backend:
* double ceil(double)
* double floor(double)
* double rint(double)
* long round(double)
* int round(float)
Also some cleanup.
Change-Id: I9f5a2f4065b1313649f4b0c4380b8176703c3fe1
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/utility_arm64.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| 6bbf0967d217ab2b7bdbb78bfd076b8fb07a44e8 |
14-Jul-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: Implement the easy long division/remainder by a constant
Also optimizes long/int divisions by power-of-two values.
Also do some clean-up.
Change-Id: Ie414e64aac251c81361ae107d157c14439e6dab5
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 77a5b50148633c2651edb7f35f5254e40cc878dc |
04-Aug-2014 |
Andreas Gampe <agampe@google.com> |
Merge "AArch64: Remove unnecessary work around for sp."
|
| cedee4744c2d4f3611a7bb9fe98ef1bf4c37d915 |
01-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Remove unnecessary work around for sp.
Use RegRegRegExtend to encode instruction for "sub/add sp, sp, Xm".
Change-Id: I13d3d2d386a7bd827e1396f291a7dcb9bffd5a29
uick/arm64/codegen_arm64.h
uick/arm64/utility_arm64.cc
|
| 7906b25f79f24af3a8b8eee0454b4db1278b9b77 |
04-Aug-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Rework ARM64 entry sequence"
|
| f29ecd69af2743a425314baa4abd6c44d8d88649 |
29-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework ARM64 entry sequence
Try to fold one sub of SP in the ARM64 entry sequence. When the
framesize is small, generate a sub over the full frame-size, and
adjust the spill offsets accordingly. If the framesize is too
large, use a pre-indexed store and fill upwards from there.
Change-Id: I1c15ac6276fb62b8164372de02fd92437f605938
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
|
| 89c210bf418a152ccabfbbf853ddcce33aea450d |
31-Jul-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Revert "Revert "Enable Load Store Elimination for ARM and ARM64"""
|
| fd0c237e7d80ad567399e760203f3cda404bf4c5 |
31-Jul-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86: Assembler: Correct r8_form for some cases
Set r8_form to false for instruction formats that don't reference
registers.
Change-Id: Ib01edef4ef7f22de25a31dc4207889bff97d163d
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
|
| 00d1ef41d0d0d438d604d102183a6bfac58643e7 |
31-Jul-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: LoadConstWide should clobber temp reg"
|
| 54659e3a2c83d3949957a10436e55e525a430a15 |
30-Jul-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: LoadConstWide should clobber temp reg
If we have 2+ LoadConstWide(FP) calls in one method it is possible
that LoadConstWide will load the method poiner only once. In some
cases, for example, if we have branches, initialization might not be
done and it may lead to a segmentation fault.
Change-Id: If45fc2d1109d7ce9bd272f5c56446b2a6884daac
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/x86/utility_x86.cc
|
| 7da9586b559290e1c16207c6513ffe485de61655 |
30-Jul-2014 |
Hiroshi Yamauchi <yamauchi@google.com> |
Add read barriers for the roots in the verifier.
Note: Because the roots (the class references in RegType objects) can
be updated by the read barriers, a lot of uses of type "const RegType"
were replaced with "RegType".
Bug: 12687968
Change-Id: I6cf37a87f352938d43fb51560a8d927ada104f50
erified_method.cc
|
| b19955d3c8fbd9588f7e17299e559d02938154b6 |
29-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Reduce time and memory usage of GVN.
Filter out dead sregs in GVN. Reclaim memory after each LVN
in the GVN modification phase.
Bug: 16398693
Change-Id: I8c88c3009663754e1b66c0ef3f62c3b93276e385
rontend.cc
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_optimization.cc
|
| bda2722ba62e5be9f9fd6a6eb0db8259bb383629 |
31-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Build fix
Make lint happy, as comments should be separated from code.
Change-Id: I4bfd88357302be9a6a104f1152e3b1fda386371e
uick/x86/target_x86.cc
|
| cc75c1b38e811cc1cb93ce8f8fcc9a83e20844fb |
31-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "1. Fix CFI for quick compiled code in x86 & x86_64; 2. Emit CFI in .eh_frame instead of .debug_frame."
|
| 35e1e6ad4b50f1adbe9f93fe467766f042491896 |
30-Jul-2014 |
Tong Shen <endlessroad@google.com> |
1. Fix CFI for quick compiled code in x86 & x86_64;
2. Emit CFI in .eh_frame instead of .debug_frame.
With CFI, we can correctly unwind past quick generated code.
Now gdb should unwind to main() for both x86 & x86_64 host-side ART.
Note that it does not work with relocation yet.
Testing:
1. art/test/run-test --host --gdb [--64] --no-relocate 005
2. In gdb, run 'b art_quick_invoke_stub', then 'r', then 'c' a few times
3. In gdb, run 'bt'. You should see stack frames down to main()
Change-Id: I5350d4097dc3d360a60cb17c94f1d02b99bc58bb
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| aa910d5ef43256102809e397de305c23f1c315e6 |
31-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix verifier mishandling erroneous array component types
The verifier must not assume that component types are not erroneous.
Bug: 16661259
Change-Id: I23b2f517259ca9c0b8a1aa38f6348fcd61e0b22e
uick/gen_common.cc
|
| 63999683329612292d534e6be09dbde9480f1250 |
15-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
Revert "Revert "Enable Load Store Elimination for ARM and ARM64""
This patch refactors the implementation of the LoadStoreElimination
optimisation pass. Please note that this pass was disabled and not
functional for any of the backends.
The current implementation tracks aliases and handles DalvikRegs as well
as Heap memory regions. It has been tested and it is known to optimise
out the following:
* Load - Load
* Store - Load
* Store - Store
* Load Literals
Change-Id: I3aadb12a787164146a95bc314e85fa73ad91e12b
ompiler_enums.h
rontend.cc
uick/arm/assemble_arm.cc
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/local_optimizations.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
eg_storage.h
|
| 1c7c3990fe5fc5f1afe74f3d94e95015d7419186 |
30-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Remove bogus dcheck
Mea culpa.
Change-Id: I6fd3b678e30354c5ab5ec6da5b3619c26d486563
uick/gen_invoke.cc
|
| 984305917bf57b3f8d92965e4715a0370cc5bcfb |
28-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework quick entrypoint code in Mir2Lir, cleanup
To reduce the complexity of calling trampolines in generic code,
introduce an enumeration for entrypoints. Introduce a header that lists
the entrypoint enum and exposes a templatized method that translates an
enum value to the corresponding thread offset value.
Call helpers are rewritten to have an enum parameter instead of the
thread offset. Also rewrite LoadHelper and GenConversionCall this way.
It is now LoadHelper's duty to select the right thread offset size.
Introduce InvokeTrampoline virtual method to Mir2Lir. This allows to
further simplify the call helpers, as well as make OpThreadMem specific
to X86 only (removed from Mir2Lir).
Make GenInlinedCharAt virtual, move a copy to X86 backend, and simplify
both copies. Remove LoadBaseIndexedDisp and OpRegMem from Mir2Lir, as they
are now specific to X86 only.
Remove StoreBaseIndexedDisp from Mir2Lir, as it was only ever used in the
X86 backend.
Remove OpTlsCmp from Mir2Lir, as it was only ever used in the X86 backend.
Remove OpLea from Mir2Lir, as it was only ever defined in the X86 backend.
Remove GenImmedCheck from Mir2Lir as it was neither used nor implemented.
Change-Id: If0a6182288c5d57653e3979bf547840a4c47626e
ompiler_enums.h
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| c32447bcc8c36ee8ff265ed678c7df86936a9ebe |
27-Jul-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "Enable Load Store Elimination for ARM and ARM64"
On extended testing, I'm seeing a CHECK failure at utility_arm.cc:1201.
This reverts commit fcc36ba2a2b8fd10e6eebd21ecb6329606443ded.
Change-Id: Icae3d49cd7c8fcab09f2f989cbcb1d7e5c6d137a
ompiler_enums.h
rontend.cc
uick/arm/assemble_arm.cc
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/local_optimizations.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
eg_storage.h
|
| fcc36ba2a2b8fd10e6eebd21ecb6329606443ded |
15-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
Enable Load Store Elimination for ARM and ARM64
This patch refactors the implementation of the LoadStoreElimination
optimisation pass. Please note that this pass was disabled and not
functional for any of the backends.
The current implementation tracks aliases and handles DalvikRegs as well
as Heap memory regions. It has been tested and it is known to optimise
out the following:
* Load - Load
* Store - Load
* Store - Store
* Load Literals
Change-Id: Iefae9b696f87f833ef35c451ed4d49c5a1b6fde0
ompiler_enums.h
rontend.cc
uick/arm/assemble_arm.cc
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/local_optimizations.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
eg_storage.h
|
| a65d63e4eb81605fd798f1ca038d651b0faa29eb |
27-Jul-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "SetConstantWide should mark both SSA regs as constant"
|
| 5e3f45bdb987ba7fe7a4114cb5fe8483432015b6 |
27-Jul-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: ReEnable check for a gap between method's arg "in" vregs and rest of its vregs"
|
| b07c1f9f4d6088ca2d4c1a10819e57b19acf7f22 |
26-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Special-case cb(n)z even for in-reg constant
Call out to OpCmpImmBranch in GenCompareAndBranch if the constant
is zero and we are testing == or !=, even when zero has been loaded
to a register already. This avoids a register size mismatch on 64b
architectures when basically doing a null check, and generally
squashes a cmp + branch to a cbz or cbnz on Arm and Mips. X86 is
not degraded.
Bug: 16562601
Change-Id: I1997760f43dc186a84247ad30ae91053f71d102d
uick/gen_common.cc
|
| 688e7c5c9f36573dd4da2edd889470d930b0054b |
15-Jul-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: ReEnable check for a gap between method's arg "in" vregs and rest of its vregs
The Quick backend's runtime model includes a gap between a method's
argument ("in") vregs and the rest of its vregs. Handling a range instruction
which spans the gap is somewhat complicated, and should not happen
in normal usage of dx. Punt to the interpreter if it happened.
This issue relates to https://code.google.com/p/android/issues/detail?id=66371
Which was fixed, but the problem returned after some changes in the verify
flags set for the range bytecodes.
Change-Id: I214f32e7b4227a450257f30607135930d0adff53
Signed-off-by: Katkov, Serguei I <serguei.i.katkov@intel.com>
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
ir_graph.cc
|
| b551fdcda9eb128c80de37c4fb978968bec6d4b3 |
25-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Clean up CalleeSaveMethod frame and the use of temp registers.
CalleeSaveMethod frame size changes :
SaveAll : 368 -> 176
RefOnly : 176 -> 96
RefsAndArgs : 304 -> 224
JNI register spill size changes :
160 -> 88
In the transition assembly, use registers following the rules:
1. x0-x7 as temp/argument registers.
2. IP0, IP1 as scratch registers.
3. After correct type of callee-save-frame has been setup, all registers
are scratch-able(probably except xSELF and xSUSPEND).
4. When restore callee-save-frame, IP0 and IP1 should be untouched.
5. From C to managed code, we assume all callee save register in AAPCS
will be restored by managed code except x19(SUSPEND).
In quick compiler:
1. Use IP0, IP1 as scratch register.
2. Use IP1 as hidden argument register(IP0 will be scratched by
trampoline.)
Change-Id: I05ed9d418b01b9e87218a7608536f57e7a286e4c
uick/arm64/arm64_lir.h
uick/arm64/call_arm64.cc
uick/arm64/target_arm64.cc
|
| 75c99e9dd8512a44d97d9818a74a69065ad82df0 |
24-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "x86: GenSelect utility update"
|
| 9ee4519afd97121f893f82d41d23164fc6c9ed34 |
17-Jul-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86: GenSelect utility update
The is follow-up https://android-review.googlesource.com/#/c/101396/
to make x86 GenSelectConst32 implementation complete.
Change-Id: I69f318e18093f9a5b00f8f00f0f1c2e4ff7a9ab2
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/arm/utility_arm.cc
uick/gen_common.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 55fff044d3a4f7196098e25bab1dad106d9b54a2 |
10-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite topological sort order and improve GVN.
Rewrite the topological sort order to include a full loop
before the blocks that go after the loop. Add a new iterator
class LoopRepeatingTopologicalSortIterator that differs from
the RepeatingTopologicalSortIterator by repeating only loops
and repeating them early. It returns to the loop head if the
head needs recalculation when we reach the end of the loop.
In GVN, use the new loop-repeating topological sort iterator
and for a loop head merge only the preceding blocks' LVNs
if we're not currently recalculating this loop.
Also fix LocalValueNumbering::InPlaceIntersectMaps() which
was keeping only the last element of the intersection, avoid
some unnecessary processing during LVN merge and add some
missing braces to MIRGraph::InferTypeAndSize().
Bug: 16398693
Change-Id: I4e10d4acb626a5b8a28ec0de106a7b37f9cbca32
b_optimizations.h
ataflow_iterator-inl.h
ataflow_iterator.h
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
ocal_value_numbering.cc
ir_graph.cc
ir_graph.h
ir_graph_test.cc
ir_optimization.cc
ir_optimization_test.cc
ass_driver_me.h
ass_me.h
reg_analysis.cc
|
| 7c66c8dffeb299743e6180b36a74018fa563ab44 |
23-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix null pointer check elimination for catch entries."
|
| 0a810d2eab27cd097ebd09a44f0ce83aa608285b |
11-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Fix null pointer check elimination for catch entries.
Remove the special treatment of catch blocks for null
pointer check elimination and class initialization check
elimination. In both cases this can help optimizing
previously missed cases. In the null check case, this
avoids incorrect optimization as exposed by the new test.
Bug: 16230771
Change-Id: I834b7a1835d9ca8572f4f8d8516d93913c701ad1
ir_optimization.cc
ir_optimization_test.cc
|
| 35690630b82dc1dbf4a7ada37225893a550ea1e0 |
16-Jul-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86: Fix assembler for Pextr
Pextr family instructions use r/m part of rmod byte as destination.
This should be handled appropriately.
Disassembler works correctly.
Change-Id: I89d00cb11ae792e9d28c178ba79a0bc1fa27e3c5
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/assemble_x86.cc
|
| 597da1f76e542b9699f8e5f8cacfea84f8854429 |
15-Jul-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
SetConstantWide should mark both SSA regs as constant
Without this change user have no chances to get the highest part
of wide reg using utility functions.
Change-Id: I2f56229ffb98276768a77c1e4a2913f288999328
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
ir_optimization.cc
|
| a59dd80f9f48cb750d329d4d4af2d99d72b484d1 |
03-Jul-2014 |
Alex Light <allight@google.com> |
Runtime can now be set to require relocation
Add a pair of runtime flags -Xrelocate and -Xnorelocate that can force
the runtime to require that all files that are run are relocated, to
prevent attacks based on the known art base address.
Add support for running patchoat on oat files compiled without an image.
Change run-test to have new --prebuild and --relocate flags.
Bug: 15358152
Change-Id: I91166c62dd1ab80e5cbcb7883a2cd0d56afca32d
uick_compiler_callbacks.h
|
| e10a0bd05b195f71cc0ff2d59568d02d29939927 |
22-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Stack overflow checks and NPE checks for optimizing."
|
| f12feb8e0e857f2832545b3f28d31bad5a9d3903 |
17-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Stack overflow checks and NPE checks for optimizing.
Change-Id: I59e97448bf29778769b79b51ee4ea43f43493d96
uick/mir_to_lir.h
|
| 7ea6f79bbddd69d5db86a8656a31aaaf64ae2582 |
15-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Throw StackOverflowError in native code
Initialize stack-overflow errors in native code to be able to reduce
the preserved area size of the stack.
Includes a refactoring away from constexpr in instruction_set.h to allow
for easy changing of the values.
Change-Id: I117cc8485f43da5f0a470f0f5e5b3dc3b5a06246
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/mir_to_lir.h
|
| 2983d230534aee99090d28b2666dae094440f1c4 |
22-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Use vabs/fabs on arm/arm64 for intrinsic abs()."
|
| 5030d3ee8c6fe10394912ede107cbc8df63b7b16 |
17-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Use vabs/fabs on arm/arm64 for intrinsic abs().
Bug: 11579369
Change-Id: If09da85e22786faa13a2d74f62cee68ea67bd087
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
|
| e72ff8022968b23efedc56c0afdc1d24e8a928c2 |
18-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Do not attempt to compile a method with too many registers"
|
| 0d8ea4661c584fc095129f853d0d72b0fa09cda5 |
18-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Do not attempt to compile a method with too many registers
The mir_graph has a hard limit on how many ssa registers it can
handle, and will silently fail or fatal out in debug builds when
more SSA registers are necessary. This adds a check in the frontend
that tries to catch some of these cases, and makes the DCHECK a
CHECK to not silently fail.
Bug: 16018097
Change-Id: Iad82178945a8f8c34943cc7573fd73d2b4decade
rontend.cc
ir_graph.h
|
| 72b660ec5df56cad8ff6d526b4377a462fc53ce5 |
18-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "x86_64: Fix GenDalvikArgsRange for 64-bit ref"
|
| 8e3acdd132aef1391676a5db2696804900aacd8e |
14-Jul-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86_64: Fix GenDalvikArgsRange for 64-bit ref
32-bit virtual register can be in 64-bit solo register.
So we should not compute the size of virtual register
basing on size of phyical register.
Change-Id: I4e11be13df8469be63808d0ce9d1ca6f80bef483
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/target_x86.cc
|
| c3561ae381960cbd52a83b7591504f158ec06920 |
17-Jul-2014 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
Improved implementation of inline of String.indexOf
This version pushes EDI only once and only in 32-bit mode.
Change-Id: I4e871d3531ac539536f8f53ec09ffb664409c9cc
uick/x86/target_x86.cc
|
| 03fc5abc4c6372c4583179d35e56f6d521806698 |
18-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: inline Math.Max/Min (float and double)"
|
| fd60fbcce909655aad71fa3094aa51d49302f19f |
18-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix GVN to handle normal paths leading to catch entry."
|
| 11ca61259be6ec8e03eaff1e98905232728b3d45 |
17-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Fix GVN to handle normal paths leading to catch entry.
When the catch block is empty, the catch entry is actually
the normal path block after the try block. Fix the LVN
merge for catch entries that didn't expect it during GVN.
Bug: 16360024
Change-Id: I9adfc3445245d3fa3c4809d4df1b7b76fbef5ff2
lobal_value_numbering_test.cc
ocal_value_numbering.cc
|
| 1222c96fafe98061cfc57d3bd115f46edb64e624 |
15-Jul-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: inline Math.Max/Min (float and double)
This implements the inlined version of Math.Max/Min intrinsics.
Change-Id: I2db8fa7603db3cdf01016ec26811a96f91b1e6ed
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
Signed-off-by: Shou, Yixin <yixin.shou@intel.com>
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| fb8a07bdf92ab097c1d309a8a6b70dacc81f4478 |
17-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Refactor GenSelect, refactor gen_common accordingly"
|
| 90969af6deb19b1dbe356d62fe68d8f5698d3d8f |
16-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Refactor GenSelect, refactor gen_common accordingly
This adds a GenSelect method meant for selection of constants. The
general-purpose GenInstanceof code is refactored to take advantage of
this. This cleans up code and squashes a branch-over on ARM64 to a
cset.
Also add a slow-path for type initialization in GenInstanceof.
Change-Id: Ie4494858bb8c26d386cf2e628172b81bba911ae5
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 30ab8a8a6597962adf63f3a438ec34b754cc117e |
17-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Lock an arg reg in GenInlinedGet
Must lock an explicit target register so that it doesn't get used
for a temp and clobbered.
Bug: 16352802
Change-Id: I9e4ac76f92460cdbe59392989d12f8d0321cc624
uick/gen_invoke.cc
|
| 9791bb427fd812c1268edab6fb3ac7b82ad9fb93 |
17-Jul-2014 |
Jeff Hao <jeffhao@google.com> |
Merge "Fix art test failures for Mips."
|
| 69dfe51b684dd9d510dbcb63295fe180f998efde |
11-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Revert "Add implicit null and stack checks for x86""""
This reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1.
Bug: 16256184
Change-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| d9cb8ae2ed78f957a773af61759432d7a7bf78af |
09-Jul-2014 |
Douglas Leung <douglas@mips.com> |
Fix art test failures for Mips.
This patch fixes the following art test failures for Mips:
003-omnibus-opcodes
030-bad-finalizer
041-narrowing
059-finalizer-throw
Change-Id: I4e0e9ff75f949c92059dd6b8d579450dc15f4467
Signed-off-by: Douglas Leung <douglas@mips.com>
uick/arm/codegen_arm.h
uick/arm/target_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| 22d5e735f403c57525fe868304c7123f0ce66399 |
16-Jul-2014 |
Ian Rogers <irogers@google.com> |
Remove object_utils.h.
Break into object_lock, field_helper and method_helper.
Clean up header files following this.
Also tidy some of the Handle code in response to compiler errors when resolving
the changes in this CL.
Change-Id: I73e63015a0f02a754d0866bfaf58208aebcaa295
uick/mir_to_lir.cc
|
| ebaca192314e21d26b97646fa962e468ff07b893 |
16-Jul-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Revert "Revert "Revert "Revert "Add intrinsic for Reference.get()"""""
|
| 4ee7a665e7f9cd2c5ace2d6304e33f64067b209f |
11-Jul-2014 |
Fred Shih <ffred@google.com> |
Revert "Revert "Revert "Revert "Add intrinsic for Reference.get()""""
Fixed TargetReg issue causing build failure for x86.
This reverts commit 9e82bd3f0ce9e5f5777bea2f752ff3e251d32f9f.
Change-Id: I7e6a526954467aaf68deeed999880dfe9aa5f06e
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| 0e359ef64546e472ed7e2292c8a48354f9907a37 |
16-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "Break apart header files."
|
| e63db27db913f1a88e2095a1ee8239b2bb9124e8 |
16-Jul-2014 |
Ian Rogers <irogers@google.com> |
Break apart header files.
Create libart-gtest for common runtime and compiler gtest routines.
Rename CompilerCallbacksImpl that is quick compiler specific.
Rename trace clock source constants to not use the overloaded profiler term.
Change-Id: I4aac4bdc7e7850c68335f81e59a390133b54e933
uick_compiler_callbacks.cc
uick_compiler_callbacks.h
|
| ed7a0f2fb84b200ab6ef34e30dcbba4c0cf8d435 |
10-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: improve usage of TargetReg() and friends.
TargetReg(arg1) does now always return a 32-bit register. We also avoid
using this function directly and rather use the two-arguments overload
or TargetPtrReg().
Change-Id: I746b3c29a2a2553b399b5c3e7ee3887c7e7c52c3
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/mir_to_lir.h
|
| 9522af985466b2a05ef5cdede0808777dea7236e |
15-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Squash a cmp w/ zero and b.ls to cbz (ARM/ARM64)
In case of array bounds checks at constant index 0 we generate a
compare and a branch. Squash into a cbz.
Change-Id: I1c6a6e37a7a2356b2c4580a3387cedb55436e251
uick/arm/int_arm.cc
uick/arm64/int_arm64.cc
|
| e50383288a75244255d3ecedcc79ffe9caf774cb |
04-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support fields in optimizing compiler.
- Required support for temporaries, to be only used by baseline compiler.
- Also fixed a few invalid assumptions around locations and instructions
that don't need materialization. These instructions should not have an Out.
Change-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62
ir_field_info.cc
|
| cf90ba7ebe00346651f3b7ce1e5b1f785f7caabd |
12-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Add another special case to GenSelect for ARM64"
|
| 39c8a99a3fdd9876980502ab12ed74a27e6be369 |
12-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Add another special case to GenSelect for ARM64
This adds a special case for a select of two constants that have a
difference of exactly one.
Change-Id: I6e8bea791cb25af1b855d62e2333fd7fe6ac4e3a
uick/arm64/int_arm64.cc
|
| 6ef2aa67656cf8e67bbd6f0f4aec0402d7158297 |
12-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Rework TargetReg(symbolic_reg, wide)"
|
| ccc60264229ac96d798528d2cb7dbbdd0deca993 |
05-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework TargetReg(symbolic_reg, wide)
Make the standard implementation in Mir2Lir and the specialized one
in the x86 backend return a pair when wide = "true". Introduce
WideKind enumeration to improve code readability. Simplify generic
code based on this implementation.
Change-Id: I670d45aa2572eedfdc77ac763e6486c83f8e26b4
ompiler_enums.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
eg_storage.h
|
| 421efca6d71ffe348295872743317bf107a9a94a |
11-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix def use.
Add comment to GenPCUseDefEncoding(). Fix def-use flags for several
instruction encodings.
Change-Id: Ifc5a2484395486c01a64307a4acddc794026d46a
uick/arm64/assemble_arm64.cc
uick/arm64/target_arm64.cc
|
| f08f0ca4b9538bff516f354532ced57cf077da66 |
12-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "Improve performance of invokevirtual/invokeinterface with embedded imt/vtable"
|
| 98d1cc8033251c93786e2fa8c59a2e555a9493be |
16-May-2014 |
Mingyao Yang <mingyao@google.com> |
Improve performance of invokevirtual/invokeinterface with embedded imt/vtable
Add an embedded version of imt/vtable into class object. Both tables start at
fixed offset within class object so method/entry point can be loaded directly
from class object for invokeinterface/invokevirtual.
Bug: 8142917
Change-Id: I4240d58cfbe9250107c95c0708c036854c455968
uick/gen_invoke.cc
uick/x86/int_x86.cc
|
| af263df7f643e699abf622c64447d31bacc14c34 |
12-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Change GenPCUseDefEncoding(), turn on Load Hoisting for ARM64
This defines the PC resource mask as empty, as the PC is not
accessible on ARM64.
Unify code paths with x86 in LoadStoreElimination and LoadHoisting.
Change-Id: Iea8b9e666f306c7a6ff52b6c5bf7e05b35346b2c
rontend.cc
uick/arm64/target_arm64.cc
uick/local_optimizations.cc
uick/mir_to_lir.h
uick/resource_mask.h
uick/x86/target_x86.cc
|
| 48f5c47907654350ce30a8dfdda0e977f5d3d39f |
27-Jun-2014 |
Hans Boehm <hboehm@google.com> |
Replace memory barriers to better reflect Java needs.
Replaces barriers that enforce ordering of one access type
(e.g. Load) with respect to another (e.g. store) with more general
ones that better reflect both Java requirements and actual hardware
barrier/fence instructions. The old code was inconsistent and
unclear about which barriers implied which others. Sometimes
multiple barriers were generated and then eliminated;
sometimes it was assumed that certain barriers implied others.
The new barriers closely parallel those in C++11, though, for now,
we use something closer to the old naming.
Bug: 14685856
Change-Id: Ie1c80afe3470057fc6f2b693a9831dfe83add831
ompiler_enums.h
uick/arm/call_arm.cc
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/call_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/utility_mips.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| b7e78cb6bdc57f2beaa8bccf383289ebdd53e552 |
12-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "AArch64: Fix and enable reverseBytes intrinsic."
|
| 873c371eea7d8700c8037d790de168b5ed7c20d0 |
11-Jul-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
ART: Fix GenSelect for ARM64
Add CSINV and replace CSNEG in GenSelect.
Some tests were failing in 083-complier-regression as CSNEG
was used instead of CSINV. CSNEG on xzr yields 0, whereas
CSINV negates the bits and yields -1, which was the intention.
Change-Id: I60557e34483f98310f7d33f18d8db203fba6e78f
Signed-off-by: Stuart Monteith <stuart.monteith@arm.com>
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/int_arm64.cc
|
| 0f73aa8f64417232e3f3d09e53f49084d2783fe0 |
12-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "Update counting VR for promotion"
|
| 59a42afc2b23d2e241a7e301e2cd68a94fba51e5 |
04-Jul-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Update counting VR for promotion
For 64-bit it makes sense to compute VR uses together for
int and long because core reg is shared.
Change-Id: Ie8676ece12c928d090da2465dfb4de4e91411920
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/arm/codegen_arm.h
uick/arm64/codegen_arm64.h
uick/mips/codegen_mips.h
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
|
| 7c6c2ac4252ac31b42967e0f0233e8d32c5b5abe |
01-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: easy division and remainder for long ints.
Also adding test 701 to test easy division and remainder for int and
long integers.
Change-Id: I8212c84e4d9eb3e9f3f4f1f1c3418537bb13dc55
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
|
| 49ab79da140b9ae79f9efca70c42eeaa84e361ff |
11-Jul-2014 |
Sebastien Hertz <shertz@google.com> |
Merge "Revert "Revert "Revert "Add intrinsic for Reference.get()""""
|
| 9e82bd3f0ce9e5f5777bea2f752ff3e251d32f9f |
11-Jul-2014 |
Sebastien Hertz <shertz@google.com> |
Revert "Revert "Revert "Add intrinsic for Reference.get()"""
This reverts commit d4415e8bd04c4a9367744ff0149597b4f37a0e0a.
Change-Id: I34553ccbdcfea35c7742d21be2a74dc7085ab2a0
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| d4415e8bd04c4a9367744ff0149597b4f37a0e0a |
11-Jul-2014 |
Christopher Ferris <cferris@google.com> |
Revert "Revert "Add intrinsic for Reference.get()""
This reverts commit a9b870b73a155ce70c867d5b3f9758fab0b45f07.
Change-Id: Ic2a9b47f2b911bef4b764d10bc33cf000e4b4211
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| a9b870b73a155ce70c867d5b3f9758fab0b45f07 |
11-Jul-2014 |
Christopher Ferris <cferris@google.com> |
Revert "Add intrinsic for Reference.get()"
This reverts commit 460503b13bc894828a2d2d47d09e5534b3e91aa1.
Change-Id: Ie63f43049307e02e3b90f4e034abc9ea54ca4e24
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| 6a1f4ad192e596b6bf43b39c26846300f401a692 |
11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Revert "Revert "Revert "Add implicit null and stack checks for x86""""
|
| 0025a86411145eb7cd4971f9234fc21c7b4aced1 |
11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Revert "Add implicit null and stack checks for x86"""
Broke the build.
This reverts commit 7fb36ded9cd5b1d254b63b3091f35c1e6471b90e.
Change-Id: I9df0e7446ff0913a0e1276a558b2ccf6c8f4c949
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 7fb36ded9cd5b1d254b63b3091f35c1e6471b90e |
10-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Add implicit null and stack checks for x86""
Fixes x86_64 cross compile issue. Removes command line options
and property to set implicit checks - this is hard coded now.
This reverts commit 3d14eb620716e92c21c4d2c2d11a95be53319791.
Change-Id: I5404473b5aaf1a9c68b7181f5952cb174d93a90d
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 93279da4a8475d187a0a2e75d50c88def5b4b8a5 |
10-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Do not dump hidden basic blocks and add a counter to file naming"
|
| 5a8ecafb7fa63cf3ebb448bb1c904858e9c29717 |
10-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "x86_64: Enable fp-reg promotion"
|
| c380191f3048db2a3796d65db8e5d5a5e7b08c65 |
08-Jul-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86_64: Enable fp-reg promotion
Patch introduces 4 register XMM12-15 available for promotion of
fp virtual registers.
Change-Id: I3f89ad07fc8ae98b70f550eada09be7b693ffb67
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/codegen_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 03c672f1a8e6cc5bef0348f1d321afb9b26ed53a |
11-Jul-2014 |
Christopher Ferris <cferris@google.com> |
Merge "Revert "Revert "Add intrinsic for Reference.get()"""
|
| 75cb5a2468dfa79600cec8668fc2e85bbc7334a7 |
11-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix GenSelect and GenFusedLongCmpBranch for ARM64"
|
| 381f8acbfbad0f84e60b7ebe9fb9584536fb373f |
10-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix GenSelect and GenFusedLongCmpBranch for ARM64
Depending on the result, we need to issue a wide csel. Also need
to handle constants, and src and dest being the same.
In GenFusedLongCmpBranch there is an ordering issue. If we swap
the inputs, we did not Load the second one.
Change-Id: Icb9876ca1288602d078b9fb89ea964ec2c910e0c
rontend.cc
uick/arm64/int_arm64.cc
|
| 7ee5cd1789b098c72010cd26a873f1cd2513e1b1 |
11-Jul-2014 |
Christopher Ferris <cferris@google.com> |
Merge "Revert "Add intrinsic for Reference.get()""
|
| e2ebfb4c7c90863c8dae72723030bf1e2e0e4589 |
11-Jul-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Add intrinsic for Reference.get()"
|
| 183636622546ce73c8b67e586e0bc0799fe9c905 |
11-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "Updates to help classes derived from X86Mir2Lir"
|
| e9f3e71c90094e87ff83bd5449a2fc4d65f717b2 |
04-Jul-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Updates to help classes derived from X86Mir2Lir
Just a couple of extra changes to help me out. These changes won't
affect anyone else.
Change-Id: I0e0985a4f16822d5cbfabbf81c9902d34ebdb5da
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/mir_to_lir.h
|
| a8869e60d93ba9eed36a5b53553b7609f58fc05b |
19-Jun-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Do not dump hidden basic blocks and add a counter to file naming
Currently, if the system dumps the CFG, it dumps the hidden BasicBlocks.
Also, the patch adds a counter that gets incremented to make the file naming
unique, using AtomicInteger.
Change-Id: I55b489c2c2bded73b62d64a94a4a8a54d2ebed2b
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ir_graph.cc
|
| 460503b13bc894828a2d2d47d09e5534b3e91aa1 |
18-Jun-2014 |
Fred Shih <ffred@google.com> |
Add intrinsic for Reference.get()
Added an intrinsic function for Reference.get(). Return immediately
without going through JNI if the slow path is not currently in use.
Otherwise, branch off to the the existing JNI function.
Approximately 47x speedup for cases where slow path is not enabled.
Change-Id: I13ad65a356fe4e104d8d83980694dc2740d7d039
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| 2ab40eb3c23559205ac7b9b039bd749458e8a761 |
02-Jun-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Add Invokes to DecodedInstruction
Add a method Invokes to test for the kInvoke flag.
Also moved IsPseudoMirOp to DecodedInstruction to use it for the various
querry methods.
Change-Id: I59a2056b7b802b8393fa2b0d977304d252b38c89
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
rontend.cc
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
uick/dex_file_method_inliner.cc
uick/mir_to_lir.cc
uick/x86/utility_x86.cc
reg_analysis.cc
|
| fe12035ea434be9b24f578cf51e53c3bb34d945c |
10-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Handle Extended MIRs in a uniform manner"
|
| 49b874b65412a95f3bf0b1e6f60f3d457dca68da |
10-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Detached blocks should not be processed by compiler"
|
| f2466a766947f952c5c41186a6c5e26fb862bb37 |
10-Jul-2014 |
Udayan Banerji <udayan.banerji@intel.com> |
ART: Handle Extended MIRs in a uniform manner
The special handling is needed since some extended MIRs can hold values in
args array, and we might want to handle the dataflow for those in a
specialized manner. Current dataflow attributes may not be able to describe
it for the extended MIRs.
Change-Id: I8b64f3142a4304282bb31f1d4686eba72284d97d
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
ir_dataflow.cc
ir_graph.h
|
| a3fe7422d7ce8bfb01f95decef45f91a44d39264 |
09-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix and enable reverseBytes intrinsic.
There is no revsh on arm64, use rev16 and sxth instead.
Change-Id: I5f9879352f0ad76b386c82cbf476894af888a64c
uick/arm64/utility_arm64.cc
uick/gen_invoke.cc
|
| cb804742f8786826286046e9c4489ef9d7ceb7ec |
10-Jul-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Rename CallInlining to SpecialMethodInliner
The CallInlining pass is used to inline just a set of pre-categorized methods.
This set of methods includes empty, instance getters, instance setters, argument
return, and constant return. Since it inlines only "special methods", it makes
sense to name it to reflect that.
Change-Id: Iea2c1820080b0c212c99e977f6b5d34ee0774868
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
b_optimizations.h
ir_graph.h
ir_optimization.cc
ass_driver_me_opts.cc
|
| 989367a47b015dd85f850cf756b436fb044b5aea |
12-Jun-2014 |
Niranjan Kumar <niranjan.kumar@intel.com> |
ART: Detached blocks should not be processed by compiler
It is possible for blocks to be detached. This means that 'successor_block_info->block'
may evaluate to 'NullBasicBlockId' The code should detect this case and handle it
appropriately.
Signed-off-by: vladimir.a.ivanov <vladimir.a.ivanov@intel.com
Signed-off-by: Niranjan Kumar <niranjan.kumar@intel.com
Change-Id: I410059cd2cbda342cc1380050c0972fcaa2b7a8e
ir_graph.cc
|
| f2b3f3373ae99ed7640e58a3abaa75d546ce2fc6 |
10-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Enable some ARM64 optimizations.
Enables kSuppressLoads, kTrackLiveTemps, kSafeOptimizations,
kPromoteCompilerTemps, kClassInitCheckElimination,
kSuppressExceptionEdges and kMatch.
Change-Id: Id3650adce7140dde8d667cd3f1b4a1c2598f156e
rontend.cc
|
| 5fa647d5f663033e4ed3d398aece1f8211d7f460 |
10-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "Slow path for iget should expect return in core reg"
|
| 4eca9f53ce6c4e59ebad93a049e86d4965e87c9d |
07-Jul-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Slow path for iget should expect return in core reg
Slow path for iget invokes the C implementation.
In all cases the C function returns the result in core reg.
So implementation should expect the result in core reg
independent on whether it is fp or not.
Change-Id: I57fb0e684c38af22316398d8071f087bd4bd253c
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/gen_common.cc
|
| fb16129c3c62f73d00ab7570e147e497e787eaad |
10-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Global Value Numbering."
|
| 95a059793c4c194f026afc74c713cc295d75d91a |
30-May-2014 |
Vladimir Marko <vmarko@google.com> |
Global Value Numbering.
Implement the Global Value Numbering for optimization
purposes. Use it for the null check and range check
elimination as the LVN used to do.
The order of evaluation of basic blocks needs improving as
we currently fail to recognize some obviously identical
values in methods with more than one loop. (There are three
disabled tests that check this. This is just a missed
optimization, not a correctness issue.)
Change-Id: I0d0ce16b2495b5a3b17ad1b2b32931cd69f5a25a
b_optimizations.h
rontend.cc
rontend.h
lobal_value_numbering.cc
lobal_value_numbering.h
lobal_value_numbering_test.cc
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_optimization.cc
ass_driver_me_opts.cc
|
| 50fb243619d337d20b56d2713d861166d48cb491 |
10-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Handle potential <clinit>() correctly in LVN."
|
| f418f3227e0001c8d75257ceff0c248cc406d81a |
09-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Handle potential <clinit>() correctly in LVN.
Bug: 16177324
Change-Id: I727ab6ce9aa9a608fe570cf391a6b732a12a8655
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_optimization.cc
ir_optimization_test.cc
|
| 34e826ccc80dc1cf7c4c045de6b7f8360d504ccf |
29-May-2014 |
Dave Allison <dallison@google.com> |
Add implicit null and stack checks for x86
This adds compiler and runtime changes for x86
implicit checks. 32 bit only.
Both host and target are supported.
By default, on the host, the implicit checks are null pointer and
stack overflow. Suspend is implemented but not switched on.
Change-Id: I88a609e98d6bf32f283eaa4e6ec8bbf8dc1df78a
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| c21dc06adc8c8447561208a3fb72ccf6d0443613 |
09-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Check slow_paths_.Size() every time"
|
| 8159af6320f7413a9d0fff1e29220c01f29c6e96 |
08-Jul-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Check slow_paths_.Size() every time
This patch fixes a bug, when a new slow path is created
during slowpath->Compile().
Change-Id: I4896a82781102694c25f4483112c6de3c56e072c
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/gen_common.cc
|
| 021b60f31a4443081e63591e184b5d707bba28c1 |
09-Jul-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: GenInlinedCas must use wide rl_src_offset under 64-bit targets
This patch fixes to use wide rl_src_offset for int and long types
under 64-bit targets, and fixes movzx8 and movsx8 to use r8_form
on the second register only.
Change-Id: Ib8c0756609100f9bc5c228f1eb391421416f3af6
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/x86/assemble_x86.cc
uick/x86/int_x86.cc
|
| 00caeedf50998444e53a7a085183019fb7bdf742 |
10-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Refactor frontend.cc
Refactor frontend.cc. Pull out flags, merge them in arrays keyed by
the instruction set. Simplify the checks and application of flags.
Change-Id: I12d5216df8d1f12e7fbe39d8132e4725c55bc8e7
rontend.cc
|
| 3d14eb620716e92c21c4d2c2d11a95be53319791 |
10-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Add implicit null and stack checks for x86"
It breaks cross compilation with x86_64.
This reverts commit 34e826ccc80dc1cf7c4c045de6b7f8360d504ccf.
Change-Id: I34ba07821fc0a022fda33a7ae21850957bbec5e7
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| eb24baec056dbe5871f1bc64b793eb2e69907866 |
08-Jul-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
x86_64: enable Peek and Poke intrinsics
This implements intrinsics for:
Memory.peekByte/Short/Int/Long()
Memory.pokeByte/Short/Int/Long()
Change-Id: I6da6250f262dfd7aded35c2e3ade2d0916bd73cb
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/x86/int_x86.cc
|
| 62f28f943e2da2873c7a09096c292f01a21c6478 |
09-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix a compile assert name with inverted meaning."
|
| 2aaed94965c2d483598660db11a1e7d608682516 |
08-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Fix a compile assert name with inverted meaning.
Change-Id: I50cc9a8b88c19e1ce7bc5b34cc4b7d650b2f052d
uick/dex_file_method_inliner.cc
|
| 665f681020ec313d6aea1aa26db582176d780079 |
09-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Workaround for invalid monitor-exit catch ranges."
|
| e8ae81453e1d6c19d7db2001a1e7b1849f74241c |
08-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Workaround for invalid monitor-exit catch ranges.
Avoid bogus exception edges from monitor-exit to a
catch handler that does exactly the same monitor-exit.
Bug: 15745363
Change-Id: I2b8b44b313c470557714744bdfb7beaef2cd2246
ir_graph.cc
ir_graph.h
|
| 460f4ef18761ad25f384172e45dff2ad0b60b7aa |
08-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Add kIntrinsicIsStatic flag for System.arraycopy().
Change-Id: I40ffb07e62474f418eabb7361f129c633022666c
uick/dex_file_method_inliner.cc
|
| 9c1bd6b8744920b62afcb08571ffcfba055c73a0 |
08-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Fix style issue.
Change-Id: Ifc73dd4331d91be8c6c5eed2159ec1733fa84995
uick/dex_file_method_inliner.cc
|
| 74d8348cfd7100fd6bd06d00dce3110a4545c4f8 |
08-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Check invoke type for intrinsic method invokes."
|
| 724c0fe2b39578eafac027e5925f27e95d40e3ba |
03-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Check invoke type for intrinsic method invokes.
Bug: 16017877
Change-Id: I931c0b19b500a042bc9235aa18212c4ab5240745
uick/dex_file_method_inliner.cc
|
| 70c4f06f9965cdb9319a2c85f65acda20086d765 |
25-Jun-2014 |
DaniilSokolov <daniil.y.sokolov@intel.com> |
ART: Intrinsic implementation for java.lang.System.arraycopy.
Implements intrinsic for java.lang.System.arraycopy(char[], int, char[], int, int) -
this method is internal to android class libraries and used in such classes as StringBuffer and
StringBuilder. It is not possible to call it from application code. The intrinsic for
this method is implemented as inline method (assembly code is generated manually).
The intrinsic is x86 32 bit only.
Change-Id: Id1b1e0a20d5f6d5f5ebfe1fdc2447b6d8a515432
Signed-off-by: Daniil Sokolov <daniil.y.sokolov@intel.com>
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| ae2efea4582df773f80be274bdc754f732b07df3 |
07-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation"
|
| 2cfe30bd592cb6ae63bb4c28ccaf4b069d6ab565 |
09-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "X86 Backend support for vectorized float and byte 16x16 operations"
|
| 60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43 |
09-Jul-2014 |
Udayan Banerji <udayan.banerji@intel.com> |
X86 Backend support for vectorized float and byte 16x16 operations
Add support for reserving vector registers for the duration of vector loop.
Add support for 16x16 multiplication, shifts, and add reduce.
Changed the vectorization implementation to be able to use the dataflow
elements for SSA recreation and fixed a few implementation details.
Change-Id: I2f358f05f574fc4ab299d9497517b9906f234b98
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Olivier Come <olivier.come@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
ackend.h
ompiler_enums.h
ir_dataflow.cc
ir_graph.cc
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 7b68fb3b9b421d4b20c1993704986d637f1cab91 |
09-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "x86_64: Clean-up after cmp-long fix"
|
| 94f3eb0c757d0a6a145e24ef95ef7d35c091bb01 |
24-Jun-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86_64: Clean-up after cmp-long fix
The patch adresses the coments from review done by Ian Rogers.
Clean-up of assembler.
Change-Id: I9dbb350dfc6645f8a63d624b2b785233529459a9
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/assemble_x86.cc
uick/x86/x86_lir.h
|
| dfc56e681beb055801491792026cb9976d8566e8 |
09-Jul-2014 |
Ian Rogers <irogers@google.com> |
Merge "Clean-up call_x86.cc"
|
| 407a9d2847161b843966a443b71760b1280bd396 |
04-Jul-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Clean-up call_x86.cc
Also adds some DCHECKs and fixes for the bugs found by them.
Change-Id: I455bbfe2c6018590cf491880cd9273edbe39c4c7
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| 251a057f52946452ac1c485b38d4ebafcf3bc5ad |
09-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix FP promotion"
|
| 01758d53a96a5adc914a2433279a9c283e5a4c2a |
09-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix FP promotion
A previous CL changed != by mistake to ==, causing incorrect
promotion results for ARM32.
Change-Id: I62572e3e86d38a55be7043196027563735010b30
uick/ralloc_util.cc
|
| 7a94961d0917495644193b281b04a570a783bb07 |
08-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Do not emit load when inlining unused Thread.currentThread()
When the result is not used, do not emit the load. This avoids
uninitialized registers leading to size-check errors.
Change-Id: I212392ffea7243720f120b2f12679df286106a02
uick/gen_invoke.cc
|
| fbf156c9394e777385ae2661e673a4c783dfd836 |
07-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "Aarch64: fix bug and enable register promotion."
|
| f101319480b1fe6575891043d0c3f0599292c25c |
07-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: fix bug and enable register promotion.
Iteration over arguments in invoke implementation was not correct
for wide arguments.
Change-Id: I46c7edcbfc9e32ded0e9a535fab3d333905bcf41
rontend.cc
uick/arm64/target_arm64.cc
|
| f22af67db2a6e7221dd15320d1a7688f1b423668 |
06-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "Fix missing dependency in new X86 instruction"
|
| 01a50d660bd1fa692b132a24ec0f18f402e69de2 |
06-Jul-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Fix missing dependency in new X86 instruction
AX is written by this opcode. Note the dependency.
Change-Id: I25209e1fb4ceb0387269436c8b00730b1caa03bc
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
|
| a77ee5103532abb197f492c14a9e6fb437054e2a |
02-Jul-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: TargetReg update for x86
Also includes changes in common code. Elimination of use of TargetReg
with one parameter and direct access to special target registers.
Change-Id: Ied2c1f87d4d1e4345248afe74bca40487a46a371
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/arm64/codegen_arm64.h
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 3ee86bcbbc29f17b0243954a52dcda96b09411e0 |
03-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "Load 64 bit constant into GPR by single instruction for 64bit mode"
|
| b5860fb459f1ed71f39d8a87b45bee6727d79fe8 |
22-Jun-2014 |
buzbee <buzbee@google.com> |
Register promotion support for 64-bit targets
Not sufficiently tested for 64-bit targets, but should be
fairly close.
A significant amount of refactoring could stil be done, (in
later CLs).
With this change we are not making any changes to the vmap
scheme. As a result, it is a requirement that if a vreg
is promoted to both a 32-bit view and the low half of a
64-bit view it must share the same physical register. We
may change this restriction later on to allow for more flexibility
for 32-bit Arm.
For example, if v4, v5, v4/v5 and v5/v6 are all hot enough to
promote, we'd end up with something like:
v4 (as an int) -> r10
v4/v5 (as a long) -> r10
v5 (as an int) -> r11
v5/v6 (as a long) -> r11
Fix a couple of ARM64 bugs on the way...
Change-Id: I6a152b9c164d9f1a053622266e165428045362f3
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
eg_storage.h
eg_storage_eq.h
|
| 0107273ae05d4624495bbaae62b9194f8ae6685b |
07-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "Aarch64: fix references handling in Load*Indexed."
|
| 255e014542b2180620230e4d9d6000ae06846bbd |
04-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: fix references handling in Load*Indexed.
Fix the way we handle references in Load/StoreBaseIndexed and friends.
We assume references are 64-bit RegStorage entities, with the
difference that they are load as 32-bit values.
Change-Id: I7fe987ef9e97e9a5042b85378b33d1e85710d8b5
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| 407f5c1a74892685f0ee603f034c0730381902a9 |
30-Jun-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Fix InstanceofFinal
Comparison should be made using GetReg()
Change-Id: Ic5bebf680395d9b93710511db9760d0e867b38cb
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/x86/int_x86.cc
|
| 63fe93d9f9d2956b1ee2b98cdd6ddd2153f5f9cf |
30-Jun-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable Inlining.
This patch fixes the remaining issues with inlining for ARM64.
Change-Id: I2d85b7c4f3fb2b667bf6029fbc271ab954378889
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Signed-off-by: Matteo Franchin <matteo.franchin@arm.com>
rontend.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_invoke.cc
|
| 15d7a46d198f8064efbe4ab10696d448ed9dc60f |
04-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: fix encoding map for kA64Fmov2xS.
Change-Id: I5127a4443969dc2322461a4b4a34d6c39a0ffd64
uick/arm64/assemble_arm64.cc
|
| ef505256e530951033a705e84a0682e7adcedf30 |
04-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "x86_64: Turn on promotion optimization"
|
| 699c04aa7cb7d0e8187fba2cbec3f0319e4da5bb |
28-Jun-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Turn on promotion optimization
This CL turns on the promotion optimization (longs).
The 64-bit references support is disabled in x86_64 backend.
Change-Id: I62723388f549b51bae41c8a6b334228b2d782610
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
rontend.cc
|
| c5e4ce116e4d44bfdf162f0c949e77772d7e0654 |
10-Jun-2014 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
x86_64: Fix intrinsics
The following intrinsics have been ported:
- Abs(double/long/int/float)
- String.indexOf/charAt/compareTo/is_empty/length
- Float.floatToRawIntBits, Float.intBitsToFloat
- Double.doubleToRawLongBits, Double.longBitsToDouble
- Thread.currentThread
- Unsafe.getInt/Long/Object, Unsafe.putInt/Long/Object
- Math.sqrt, Math.max, Math.min
- Long.reverseBytes
Math.min and max for longs have been implemented for x86_64.
Commented out until good tests available:
- Memory.peekShort/Int/Long, Memory.pokeShort/Int/Long
Turned off on x86-64 as reported having problems
- Cas
Change-Id: I934bc9c90fdf953be0d3836a17b6ee4e7c98f244
uick/gen_invoke.cc
uick/x86/assemble_x86.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 23abec955e2e733999a1e2c30e4e384e46e5dde4 |
02-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add few more inline functions
This patch adds inlining support for the following functions:
* Math.max/min(long, long)
* Math.max/min(float, float)
* Math.max/min(double, double)
* Integer.reverse(int)
* Long.reverse(long)
Change-Id: Ia2b1619fd052358b3a0d23e5fcbfdb823d2029b9
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 5192cbb12856b12620dc346758605baaa1469ced |
01-Jul-2014 |
Yixin Shou <yixin.shou@intel.com> |
Load 64 bit constant into GPR by single instruction for 64bit mode
This patch load 64 bit constant into a register by a single movabsq
instruction on 64 bit bit instead of previous mov, shift, add
instruction sequences.
Change-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
uick/x86/assemble_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| ffcdd9f13daba70a64bb85688726ae23aa7a6eda |
02-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "x86_64: Unify 64-bit check in x86 compiler"
|
| dd64450b37776f68b9bfc47f8d9a88bc72c95727 |
01-Jul-2014 |
Elena Sayapina <elena.v.sayapina@intel.com> |
x86_64: Unify 64-bit check in x86 compiler
Update x86-specific Gen64Bit() check with the CompilationUnit target64 field
which is set using unified Is64BitInstructionSet(InstructionSet) check.
Change-Id: Ic00ac863ed19e4543d7ea878d6c6c76d0bd85ce8
Signed-off-by: Elena Sayapina <elena.v.sayapina@intel.com>
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 6f9dbb8d4aa72c9b24ea45358751123b6e4c7488 |
02-Jul-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Quick compiler: More size checks, add TargetReg variants"
|
| 4d5d794382cd6d3a25392d17543d5987e432d314 |
26-Jun-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Simplify FlushIns
This change simplifies FlushIns for x86_64.
Change-Id: I2b41fae32603e0951e3847cc1e4f9c6bfab349a0
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/x86/target_x86.cc
|
| 4b537a851b686402513a7c4a4e60f5457bb8d7c1 |
01-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Quick compiler: More size checks, add TargetReg variants
Add variants for TargetReg for requesting specific register usage,
e.g., wide and ref. More register size checks.
With code adapted from https://android-review.googlesource.com/#/c/98605/.
Change-Id: I852d3be509d4dcd242c7283da702a2a76357278d
ir_graph.h
uick/arm64/arm64_lir.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
eg_location.h
|
| f9872f0b5f713af867b4e32e647a1b92f94fb01a |
02-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix size error reported by ARM64 backend
Also removes a spurious LOG in dex2oat.
Change-Id: Ia264fbfb3cb8d59978f3a61e814eb6940e272ece
uick/gen_invoke.cc
|
| 595248a0d9b96a4b442bb0cd3fecd55ae630b03f |
30-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Merge "AArch64: Rename A64_/A32_ register prefix to x/w."
|
| baa7c88a34fdfd230a2a383c2e388945f4d907b6 |
30-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Rename A64_/A32_ register prefix to x/w.
A64/A32 look like architecture name, but they are all for arm64.
Use lower-case to name the registers defined in "ARM ARM" which can
also be directly used in assembly file.
Use upper-case to name the registers which are other aliases.
Change-Id: I0ac38ed75f977fdc362288b01179b84feaee5614
uick/arm64/arm64_lir.h
uick/arm64/call_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
|
| 4c7cc15590a2f921e6055f723e46694966cb7665 |
23-Jun-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86_64: Fix GenArrayBoundsCheck
The GenArrayBoundsCheck uses args registers to put array_length and
index as a parameter to out call. To ensure that we do not corrupt
register values there is a check whether need arg is not busy.
We need to use reg num comparison instead of reg comparison.
Change-Id: I260f02d1c155b69be8652dee2e89f3b63d15297c
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/int_x86.cc
|
| 903989dae724ec0b186ec98c2afd1e074ed41d4d |
01-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
AArch64: Fix OpRegRegImm64 add/sub for large negative imm.
Bug: 15837964
Change-Id: I401edf687352fae3dca03c0a807dac5750e454f6
uick/arm64/utility_arm64.cc
|
| 949cd973513f1ae29280fcde7953b0f7e70172a7 |
23-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Enable GenSpecialCase.
With the following fixes:
1. Map reference register to 64-bit argument register.
2. Set max_mapped_in_ to the index of last in. (Originally it was the
low part of the wide register)
Change-Id: If41de654a004a0561396e349d1f150517a72ab2f
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
|
| 2db3e269e3051dacb3c8a4af8f03fdad9b0fd740 |
26-Jun-2014 |
Douglas Leung <douglas@mips.com> |
Fix quick mode bugs for Mips.
This patch enable quick mode for Mips and allows the emulator to boot.
However the emulator is still not 100% functional. It still have problems
launching some apps.
Change-Id: Id46a39a649a2fd431a9f13b06ecf34cbd1d20930
Signed-off-by: Douglas Leung <douglas@mips.com>
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/ralloc_util.cc
|
| a64d728836712e9295ada7de44d8cc3165d595a8 |
27-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: implement easy division and reminder."
|
| c6301bcfbefa1c320f922d2209caee3481dc1aa2 |
27-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: ARM64 fp return reg locations are FP
Change-Id: Ica14b63ebde8efda113a146939309a6c37adc9aa
uick/arm64/arm64_lir.h
|
| a94d7fd18a11dc14fe43c5f814115b73d48846c2 |
27-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix topological ordering and use it for optimizations."
|
| fb0fecffb31398adb6f74f58482f2c4aac95b9bf |
20-Jun-2014 |
Olivier Come <olivier.come@intel.com> |
ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation
The patch adds the HADDPS, HADDPD, SHUFPS, and SHUFPD instruction generation
for X86.
Change-Id: Ida105d3e57be231a5331564c1a9bc298cf176ce6
Signed-off-by: Olivier Come <olivier.come@intel.com>
uick/x86/assemble_x86.cc
uick/x86/x86_lir.h
|
| b9d11f7e2f60bdebfd2ece34e01ecc789921837d |
25-Jun-2014 |
Ian Rogers <irogers@google.com> |
Merge "x86_64: Fix wide argument increment"
|
| e63d9d4e42e659a365a9a06b910852ebc297f457 |
24-Jun-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86_64: int-to-long should ensure that int in kCoreReg
it is possible that int in xmm so implementation of int-to-long
should ensure that src in core reg before usage of move with
sign extension which does not support xmm case.
Change-Id: Ibab9df7564f0f1c1f3e1f5ff67c38f1a5e3cdb69
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/assemble_x86.cc
uick/x86/int_x86.cc
|
| b6564c19c5e14a3caa3f8da423b0da510fda7026 |
24-Jun-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: Fix wide argument increment
This patch fixes to always increment the index for a wide argument,
and fixes the index upper bound.
Otherwise, the mapping may be incorrect.
Change-Id: I0116d8fd0a0a5c1270a23129c73a9e3651132977
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/target_x86.cc
|
| fe7aee2d20b47dad6029a588e0c7394f0c75d080 |
25-Jun-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "More advanced timing loggers."
|
| f5997b4d3f889569d5a2b724d83d764bfbb8d106 |
20-Jun-2014 |
Mathieu Chartier <mathieuc@google.com> |
More advanced timing loggers.
The new timing loggers have lower overhead since they only push into
a vector. The new format has two types, a start timing and a stop
timing. You can thing of these as brackets associated with a
timestamp. It uses these to construct various statistics when needed,
such as: Total time, exclusive time, and nesting depth.
Changed PrettyDuration to have a default of 3 digits after the decimal
point.
Exaple of a GC dump with exclusive / total times and indenting:
I/art (23546): GC iteration timing logger [Exclusive time] [Total time]
I/art (23546): 0ms InitializePhase
I/art (23546): 0.305ms/167.746ms MarkingPhase
I/art (23546): 0ms BindBitmaps
I/art (23546): 0ms FindDefaultSpaceBitmap
I/art (23546): 0ms/1.709ms ProcessCards
I/art (23546): 0.183ms ImageModUnionClearCards
I/art (23546): 0.916ms ZygoteModUnionClearCards
I/art (23546): 0.610ms AllocSpaceClearCards
I/art (23546): 1.373ms AllocSpaceClearCards
I/art (23546): 0.305ms/6.318ms MarkRoots
I/art (23546): 2.106ms MarkRootsCheckpoint
I/art (23546): 0.153ms MarkNonThreadRoots
I/art (23546): 4.287ms MarkConcurrentRoots
I/art (23546): 43.461ms UpdateAndMarkImageModUnionTable
I/art (23546): 0ms/112.712ms RecursiveMark
I/art (23546): 112.712ms ProcessMarkStack
I/art (23546): 0.610ms/2.777ms PreCleanCards
I/art (23546): 0.305ms/0.855ms ProcessCards
I/art (23546): 0.153ms ImageModUnionClearCards
I/art (23546): 0.610ms ZygoteModUnionClearCards
I/art (23546): 0.610ms AllocSpaceClearCards
I/art (23546): 0.549ms AllocSpaceClearCards
I/art (23546): 0.549ms MarkRootsCheckpoint
I/art (23546): 0.610ms MarkNonThreadRoots
I/art (23546): 0ms MarkConcurrentRoots
I/art (23546): 0.610ms ScanGrayImageSpaceObjects
I/art (23546): 0.305ms ScanGrayZygoteSpaceObjects
I/art (23546): 0.305ms ScanGrayAllocSpaceObjects
I/art (23546): 1.129ms ScanGrayAllocSpaceObjects
I/art (23546): 0ms ProcessMarkStack
I/art (23546): 0ms/0.977ms (Paused)PausePhase
I/art (23546): 0.244ms ReMarkRoots
I/art (23546): 0.672ms (Paused)ScanGrayObjects
I/art (23546): 0ms (Paused)ProcessMarkStack
I/art (23546): 0ms/0.610ms SwapStacks
I/art (23546): 0.610ms RevokeAllThreadLocalAllocationStacks
I/art (23546): 0ms PreSweepingGcVerification
I/art (23546): 0ms/10.621ms ReclaimPhase
I/art (23546): 0.610ms/0.702ms ProcessReferences
I/art (23546): 0.214ms/0.641ms EnqueueFinalizerReferences
I/art (23546): 0.427ms ProcessMarkStack
I/art (23546): 0.488ms SweepSystemWeaks
I/art (23546): 0.824ms/9.400ms Sweep
I/art (23546): 0ms SweepMallocSpace
I/art (23546): 0.214ms SweepZygoteSpace
I/art (23546): 0.122ms SweepMallocSpace
I/art (23546): 6.226ms SweepMallocSpace
I/art (23546): 0ms SweepMallocSpace
I/art (23546): 2.144ms SweepLargeObjects
I/art (23546): 0.305ms SwapBitmaps
I/art (23546): 0ms UnBindBitmaps
I/art (23546): 0.275ms FinishPhase
I/art (23546): GC iteration timing logger: end, 178.971ms
Change-Id: Ia55b65609468f212b3cd65cda66b843da42be645
rontend.cc
|
| fbd18f1923334f3208cfe6ba5f1d4f9eb421b063 |
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Merge "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter""
|
| de68676b24f61a55adc0b22fe828f036a5925c41 |
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"
This reverts commit 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d.
Breaks the build.
Change-Id: I9faad4e9a83b32f5f38b2ef95d6f9a33345efa33
ompiler_enums.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 7e47f713067b55e24b5d24f2c892ceefd7971ebf |
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Split out more cases of Load/StoreRef, volatile as parameter"
|
| 3c12c512faf6837844d5465b23b9410889e5eb11 |
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter""
This reverts commit de68676b24f61a55adc0b22fe828f036a5925c41.
Fixes an API comment, and differentiates between inserting and appending.
Change-Id: I0e9a21bb1d25766e3cbd802d8b48633ae251a6bf
ompiler_enums.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 7db22606228d21b3adba04851409a4a78e6b4263 |
24-Jun-2014 |
Calin Juravle <calin@google.com> |
Merge "Always compile leafs during profile based compilation."
|
| 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d |
23-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Split out more cases of Load/StoreRef, volatile as parameter
Splits out more cases of ref registers being loaded or stored. For
code clarity, adds volatile as a flag parameter instead of a separate
method.
On ARM64, continue cleanup. Add flags to print/fatal on size mismatches.
Change-Id: I30ed88433a6b4ff5399aefffe44c14a5e6f4ca4e
ompiler_enums.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 38a09040432001f1a4330ac80b80b1178e1eaf8a |
23-Jun-2014 |
Calin Juravle <calin@google.com> |
Always compile leafs during profile based compilation.
Bug:12877748
Change-Id: Idbee9eaa87c419454728de195bdbdd9b0e6b7b50
rontend.cc
|
| 1c55703526827b5fc63f5d4b8477f36574649342 |
23-Jun-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86_64: Correct fix for cmp-long
We cannot rely on the sign of the sub instruction because
LONG_MAX - LONG_MIN = -1 and the sign will indicate that
LONG_MAX < KONG_MIN and it is incorrect.
The fix also contains small improvement for load wide constant.
Change-Id: I74df70d7c198cebff5cad8c1d5614c1d29b79a1b
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/assemble_x86.cc
uick/x86/int_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 2073e7553d1ca65f13b6c4e4fe364c2a345a1511 |
23-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: Fix StoreValue to use RefDisp when necessary.""
This reverts commit e98297bafe84e2ac15eb73739f27826fcaae1203.
No matter if holding a reference or not, the store needs to be tagged
as updating a Dalvik register.
Change-Id: Icb80e1b6f82103cff33ee971faaaa02f9ad4a683
uick/gen_loadstore.cc
|
| a5377fe9231b441856b3c9bfa4aa003445436958 |
23-Jun-2014 |
Ian Rogers <irogers@google.com> |
Merge "Revert "ART: Fix StoreValue to use RefDisp when necessary.""
|
| e98297bafe84e2ac15eb73739f27826fcaae1203 |
22-Jun-2014 |
Ian Rogers <irogers@google.com> |
Revert "ART: Fix StoreValue to use RefDisp when necessary."
This reverts commit 596bea8f6331fe8ad6eb456afa1f7dfe1b92e09c.
Change-Id: I1942bfc5127e8a631c5b24d107d304c7cd994e78
uick/gen_loadstore.cc
|
| 596bea8f6331fe8ad6eb456afa1f7dfe1b92e09c |
20-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix StoreValue to use RefDisp when necessary.
Split from https://android-review.googlesource.com/#/c/98605
Change-Id: Ib3a03428ddbec659591b838404bbfa1553fe18e9
uick/gen_loadstore.cc
|
| b493c2983016a78de498c3a3aef302b1353dca99 |
21-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Enable some optimizations"
|
| 4370d3d3a92b45ac3bdceae0c3059648b0f3fc1d |
21-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Fix fp-to-core conversion"
|
| 7499cd1d4445fd00aa3c9503497a171fae9bf20e |
21-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Fix comp-long"
|
| 0498223110174a055c743219c6cd82bee90d6034 |
20-Jun-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86_64: Fix comp-long
If result and source are the same VR then implementation does
a wrong thing clearing dest in the beginning.
Change-Id: I66d97a828aa38121676561858119ccd44aaa4d50
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/int_x86.cc
|
| 5078d978f21620824d9c2fdcd73063260592398c |
20-Jun-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86_64: Fix fp-to-core conversion
Long max value cannot be represented with double precision
and check fp against max_long does not guard invocation of
conversion instruction. As a result conversion ends up with
min long instead of max long.
The patch changes the guard check to not allow conversion
instruction for max long.
Change-Id: Ied761051ec27cf6c833040c25a2c61ab9fcea414
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/fp_x86.cc
|
| 990f110b45127055d99fe894afb1ae4cfd92046c |
20-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix StoreValue to use RefDisp when necessary."
|
| 49c5f50cbc8e4d8c195d8f1409abcfde08b39786 |
20-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix register overlap checks in CopyArgumentRegs
This is a make-shift CL. Expect this to be replaced by a reworked
implementation.
Change-Id: Ia74697d1436efd2971bc4c791fabed66d2e9d72d
uick/gen_invoke.cc
|
| 54ee4442a3bd5169258c32234c5dfc187360b043 |
20-Jun-2014 |
buzbee <buzbee@google.com> |
Quick compiler: remove Arm64 "EXPERIMENTAL" filter
Support for the compilation of all dex opcodes should now exist.
We'll go ahead and leave the filter code in for a new weeks, as it
may be handy if we need a quick workaround.
Change-Id: I8f1857136d78347b7d2337db2c793ad41ad45cb9
rontend.cc
|
| c61b3c984c509d5f7c8eb71b853c81a34b5c28ef |
18-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: implement easy division and reminder.
This implements easy division and reminder for integer only (32-bit).
The optimisation applies to div/rem by powers of 2 and to div by small
literals (between 3-15).
Change-Id: I71be7c4de5d2e2e738b88984f13efb08f4388a19
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/mir_to_lir.h
|
| 622bdbe6c295b08d06dfaa8d896b9ca152aa899c |
19-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Fix topological ordering and use it for optimizations.
Use the topological sort order for ClassInitCheckElimination
and NullCheckEliminationAndTypeInference.
Change-Id: I315ca7f300dd11390f48aefebfe988baf91bdcf1
b_optimizations.h
ataflow_iterator.h
ir_graph.cc
ir_graph.h
ir_optimization_test.cc
ass_driver_me.h
ass_driver_me_post_opt.cc
ost_opt_passes.h
|
| a81fe3d512ef846aad3398222afd1f0588bbaf7c |
19-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Several fixes required for enabling promotion"
|
| 7133659eeea45e391aa12affea75e39e8c300eb0 |
19-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Fix neg_double"
|
| 202e74780054ce2b0d87ddf0591cd83b6506de1d |
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Log information when skipping method during compilation"
|
| 060e6febbe2db5e1d754d2743d6534b217d868fe |
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Log information when skipping method during compilation
Add a reason for skipping a method to the log.
Change-Id: I3b31ee64cce6b531b25397f646cdfee650704ad6
rontend.cc
ir_analysis.cc
ir_graph.h
|
| 02959eae949f37445c184ae6f3df4d068ff309e0 |
18-Jun-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
x86_64: Fix neg_double
In a case, when src and dest regs are the same, previous
implementation of the neg_double bytecode returns an
incorrect result.
This implementation uses shifts and xor and works for both
cases.
Change-Id: I137d9a90298ec225d80435d35558da8abb69cd01
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/x86/fp_x86.cc
|
| 995b32cc8e94a9730d6cf663a23afc9c997c1771 |
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Implicit checks in the compiler are independent from Runtime"
|
| 5655e84e8d71697d8ef3ea901a0b853af42c559e |
18-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Implicit checks in the compiler are independent from Runtime
When cross-compiling, those flags are independent. This is an
initial CL that helps bypass fatal failures when cross-compiling,
as not all architectures support (and have turned on) implicit
checks.
The actual transport for the target architecture when it is
different from the runtime needs to be implemented in a follow-up
CL.
Bug: 15703710
Change-Id: Idc881a9a4abfd38643b862a491a5af9b8841f693
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/arm64/target_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/x86/target_x86.cc
|
| f987927a68d0489970c1eca6a32fd02ca9913357 |
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Reserve 8B for float literals on ARM64
This is a cludge to make sure literal pools will be 8B aligned.
A better approach would be post-processing - that way we could
pack the floats.
Change-Id: Ia9c6f53e0f6e37b4be79e1efe7f14feb49f2052b
uick/arm64/utility_arm64.cc
|
| 57eb0b46e4b6ff91b5b74010057d6f733d869bfd |
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Change rrr add and sub for ARM64"
|
| 9f975bfe091e9592a1b6b5b46d224ec04b1183b6 |
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Change rrr add and sub for ARM64
OpRegRegImm will fall back to loading a constant into a register
and then doing the operation with three registers. That is, for
example, the case when we allocate large stack frames. However,
the currently chosen operations are add/sub shifted, which does
*not* allow to specify SP (x31 will be interpreted as xzr). Switch
to add/sub extended. There won't be a practical difference, as we
do not call with anything other than 0 shift.
Change-Id: I2b78df9f044d2963e3e890777c855b339952f9f4
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/utility_arm64.cc
|
| 7cd26f355ba83be75b72ed628ed5ee84a3245c4f |
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Target-dependent stack overflow, less check elision
Refactor the separate stack overflow reserved sizes from thread.h
into instruction_set.h and make sure they're used in the compiler.
Refactor the decision on when to elide stack overflow checks:
especially with large interpreter stack frames, it is not a good
idea to elide checks when the frame size is even close to the
reserved size. Currently enforce checks when the frame size is
>= 2KB, but make sure that frame sizes 1KB and below will elide
the checks (number from experience).
Bug: 15728765
Change-Id: I016bfd3d8218170cbccbd123ed5e2203db167c06
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/mips/call_mips.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
|
| 47b31aa855379471c06735b738396fa76e7c1988 |
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Start implementation of OpRegRegRegExtend for ARM64
We need a sign-extending add for packed-switch and sparse-switch,
as the 32b values are signed offsets. This starts an implementation
that is sufficient for the use cases.
Change-Id: Ib5bae24b902077346a97d5e9e061533f9cdfcdb0
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/utility_arm64.cc
|
| e4a6bd7550508e96aeb575e5aa1faa6fef35e20d |
13-Jun-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Enable some optimizations
Except kLoadStoreElimination and kPromoteRegs.
Change-Id: Iaebf6652641fe32c9e9b21469e4f898af2d67250
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
rontend.cc
|
| 3157f9a18d0524e33b4feb67664974afc13ae351 |
18-Jun-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Several fixes required for enabling promotion
This patch includes x86_64 fixes which solve the issues
reproducible with promotion optimization enabled.
Change-Id: I3a3b0d290380d639705cd58f38b8d62b1eb930d3
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/x86/int_x86.cc
|
| 5969734b3036a7073c378e0687dd3e90c43d21a7 |
18-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Add x86 inlined abs method for float/double"
|
| 7071c8d5885175a746723a3b38a347855965be08 |
05-Mar-2014 |
Yixin Shou <yixin.shou@intel.com> |
Add x86 inlined abs method for float/double
Add the optimized implementation of inlined abs method for
float/double for X86 side.
Change-Id: I2f367542f321d88a976129f9f7156fd3c2965c8a
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/utility_x86.cc
|
| 9b743ef7955a70952f3e147f9ce8d9d47c9051f9 |
18-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: Fix OpCmpMemImmBranch."
|
| 7c1c263f3227169e055200cc481c022f1cf37213 |
17-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix OpCmpMemImmBranch.
The temp register can be 64-bit in some cases(ArgReg or RefReg).
Always compare 32-bit value no matter what the temp register is.
Change-Id: Ib237dd081da0b5900b8c2418df1621d3245cb03d
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
|
| 71921a3ff18ba27061a013465c1b2d850a235dfa |
18-Jun-2014 |
Ian Rogers <irogers@google.com> |
Merge "x86_64: Clobber r8 to r11 and xmm0 to xmm15"
|
| 4c115b85cc48f4dfc8fc2b0484ddfeb29f02d658 |
17-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Revert "Add x86 inlined abs method for float/double"
This reverts commit e88b89ad1d1a583daf205c7a387ba13f549f95f1.
Change-Id: I2ba21b7442ba3696482d45001e6bd32e8baf9d1f
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/utility_x86.cc
|
| 0210d11658becc2bf02fe79788c87276a857d0e9 |
16-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Add transition assembly to wrapper native functions.
There is slight difference between managed code ABI and AAPCS. We
can make managed code ABI to be the same with AAPCS. But considering
that, we might introduce more differences later for performance. It
is better to have a wrapper to deal with the differences.
Change-Id: I46ced072e9e3a83f713d2bf86fa478fc6144ee81
uick/arm64/fp_arm64.cc
|
| 838b38fa3b2fb4a64f8a316459d372020f6e8feb |
17-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Implement rem_double/rem_float for x86/x86-64"
|
| bd3682eada753de52975ae2b4a712bd87dc139a6 |
11-Jun-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: Implement rem_double/rem_float for x86/x86-64
This adds inlined version of the rem_double/rem_float bytecodes
for x86/x86-64 platforms. This patch also removes unnecessary
fmod and fmodf stubs from runtime.
Change-Id: I2311aa2adf08d6614527e0da070e3b6ce2343a20
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/x86_lir.h
|
| cf20c1a6d58eb45fb660722354761925b0a103e1 |
17-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Fix build: style issue.
Change-Id: I2a1e81dc7c95b7e21f4fde47e2f88dae653b25f0
uick/x86/fp_x86.cc
|
| d87c29c7c5f04f643677d87cd202e90bda8fed02 |
17-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Add x86 inlined abs method for float/double"
|
| 35ec2b5faf9a2dbc3c0cddb7ebc09952b8a27d2a |
17-Jun-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: Clobber r8 to r11 and xmm0 to xmm15
This clobbers r8 to r11 and xmm0 to xmm15, so that
they can be reloaded after an external C call.
Change-Id: If5cac97e475083912026309891dc332f14f8683a
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/x86/target_x86.cc
|
| c41e6dc89ec6593e9af9af524f2ec7be6e2d24a4 |
13-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: improve 64-bit immediates loads.
Improve the quick backend to load immediates by choosing the best
of the following strategies:
- use wzr, xzr to load 0 (via mov) or -1 (via mvn),
- use logical immediates (orr),
- use one movz/movn optionally followed by one or more movk,
- use the literal pool.
Change-Id: I8e46e6d9eaf46b717761dd9d60e63ee3f2a5422b
uick/arm64/codegen_arm64.h
uick/arm64/utility_arm64.cc
|
| d6b2237d82507b393cf105a0c6ebf04616bc78a6 |
16-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Instanceof returns true if ref == 0 on x86-64"
|
| bd7ebdbd928673f8136dcbe3f755610e3ae9bc7d |
16-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Use GetLow() to access low register of a pair"
|
| b9b9d66fb4eba71b8691f8b1172fe252b3901aad |
16-Jun-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Use GetLow() to access low register of a pair
A couple of spots were missed.
Change-Id: I14bd1d1bec4b497b742ef9edaf762e0c8e4ebf79
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/int_x86.cc
|
| 57cd219d8a7869a06d669bed08460013cf24398b |
16-Jun-2014 |
buzbee <buzbee@google.com> |
Merge "Arm64 hard-float"
|
| 33ae5583bdd69847a7316ab38a8fa8ccd63093ef |
12-Jun-2014 |
buzbee <buzbee@google.com> |
Arm64 hard-float
Basic enabling of hard-float for Arm64. In future CLs we'll
consolidate the various targets - there is a lot of overlap.
Compilation remains turned off in this CL, but I expect
to enable a subset shortly. With compilation fully enabled
(including the EXPERIMENTAL opcodes with the exception of
REM and THROW), we get the following run-test results:
003-omnibus-opcode failures:
Classes.checkCast
Classes.arrayInstance
UnresTest2
Haven't gone deep, but these appear to be related to throw/catch and/or
stacktrace.
For REM, the generated code looks reasonable to me - my guess is that
we've got something wrong on the transition to the runtime. Haven't
looked deeper yet, though.
The bulk of the other failure also appear to be related to transitioning
to the runtime system, or handling try/catch.
run-test status:
Status with optimizations disabled, REM_FLOAT/DOUBLE and THROW disabled:
succeeded tests: 94
failed tests: 22
failed: 003-omnibus-opcodes
failed: 004-annotations
failed: 009-instanceof2
failed: 024-illegal-access
failed: 025-access-controller
failed: 031-class-attributes
failed: 044-proxy
failed: 045-reflect-array
failed: 046-reflect
failed: 058-enum-order
failed: 062-character-encodings
failed: 063-process-manager
failed: 064-field-access
failed: 068-classloader
failed: 071-dexfile
failed: 083-compiler-regressions
failed: 084-class-init
failed: 086-null-super
failed: 087-gc-after-link
failed: 100-reflect2
failed: 107-int-math2
failed: 201-built-in-exception-detail-messages
Change-Id: Ib66209285cad8998d77a14781de300af02a96b15
ompiler_enums.h
rontend.cc
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.cc
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
|
| e88b89ad1d1a583daf205c7a387ba13f549f95f1 |
05-Mar-2014 |
Yixin Shou <yixin.shou@intel.com> |
Add x86 inlined abs method for float/double
Add the optimized implementation of inlined abs method for
float/double for X86 side.
Change-Id: I4e095644a90524354040174954c1e127c7bb4ee2
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/utility_x86.cc
|
| 954550063b5ac323e31d0b0564b5f9a9a023545c |
09-Jun-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: Instanceof returns true if ref == 0 on x86-64
On x86-64 platform rl_result and kArg0 is not the same, so we have to
handle this in the proper way.
Change-Id: Ia651f5dd8dd2cf584f510739ed58b46197dfee94
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/x86/int_x86.cc
|
| 8c7a02a7d6eab177b0d34b732522ea6dc491e131 |
14-Jun-2014 |
buzbee <buzbee@google.com> |
Quick compiler:interpret on type mismatch
The Dex specification is a bit loose - particularly in regards
to types. The Quick compiler, though, makes some assumptions
about types. In particular, it doesn't expect to encounter the
use of a long or double virtual register pair that was defined
by two independent 32-bit operations.
dx does not create such patterns (at least in recent memory).
However, at least one such case exists in the wild. The next
version of the Dex specification will add more type constraints
and formally disallow such cases. Meanwhile, existing code will
be handled by identifying these cases an reverting to interpretation
for the offending method.
Fix for internal b/15616104
Change-Id: Ibe9c423be9a952ff58cf8d985aa164885b8dd2ae
rontend.cc
ir_analysis.cc
ir_graph.h
reg_analysis.cc
|
| df88a9e44673655009cc560947d29c1400516f12 |
14-Jun-2014 |
Ian Rogers <irogers@google.com> |
Merge "x86_64: Enable compilation"
|
| 136aaee2993a4a5fd93eb9371584161c6d1c7445 |
06-Jun-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Enable compilation
This patch enables compilation of all methods for x86_64
except image.
Change-Id: Ie210809f2595cc25da688a4ad0363c258bcf8233
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
rontend.cc
|
| 5aa6e04061ced68cca8111af1e9c19781b8a9c5d |
14-Jun-2014 |
Ian Rogers <irogers@google.com> |
Tidy x86 assembler.
Use helper functions to compute when the kind has a SIB, a ModRM and RegReg
form.
Change-Id: I86a5cb944eec62451c63281265e6974cd7a08e07
uick/arm/assemble_arm.cc
uick/arm/codegen_arm.h
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/mips/assemble_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
|
| 97ed29f800c56a06fd6989e0883e4c97bedd2453 |
14-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Hide unreachable basic blocks in the compiler"
|
| 4439596b00c91f565370bf0813cc2f9165093693 |
13-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Hide unreachable basic blocks in the compiler
Unreachable blocks are not handled uniformly in the optimization
passes. Uniformly hide them to avoid initialization errors.
Bug: 15573463
Change-Id: Ia9e89fa357d5672a6cd8389f28a06ff618fe60ee
rontend.cc
ir_graph.cc
ir_graph.h
sa_transformation.cc
|
| 7e399fd3a99ba9c9dbfafdf14f75dd318fa7d454 |
11-Jun-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: Disable all optimizations and fix bugs
This disables all optimizations and ensures that art tests still pass.
Change-Id: I43217378d6889bb04f4d064f8d53cb3ff4c20aa0
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
rontend.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 169489b4f4be8c5dd880ba6f152948324d22ff79 |
11-Jun-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add support for inlined methods
This patch adds support for Arm64 inlined methods.
Change-Id: Ic6aeed6d2d32f65cd1e63cf482f83cdcf958798a
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| e2eb29e98be3ba72cce7da40847ab3d605b9455d |
12-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Enable MOVE_*, some CONST_*, CMP_*.
With the fixes of GenArithImmOpLong, GenShiftOpLong, OpRegImm,
OpRegRegImm, OpRegRegImm64, EncodeLogicalImmediate and fmov.
Change-Id: I8cae4f921d5150a6b8e4803ca4dee553928d1a58
rontend.cc
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
|
| c0090a4206306a80a830de35c7b4c74a43df690a |
12-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Rewrite use/def masks to support 128 bits."
|
| 8dea81ca9c0201ceaa88086b927a5838a06a3e69 |
06-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite use/def masks to support 128 bits.
Reduce LIR memory usage by holding masks by pointers in the
LIR rather than directly and using pre-defined const masks
for the common cases, allocating very few on the arena.
Change-Id: I0f6d27ef6867acd157184c8c74f9612cebfe6c16
ompiler_enums.h
uick/arm/arm_lir.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/local_optimizations.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/resource_mask.cc
uick/resource_mask.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| adea0aa22790254bf9978984e9ffc3688a41e129 |
12-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: arm64 explicit stack overflow checks"
|
| f8ec48e8eff0050de1451fc8e9c3a71c26d5ce7e |
06-Jun-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
ART: arm64 explicit stack overflow checks
Implement only the explicit checks for the quick backend for arm64.
Implicit checks require fault handlers, which are currently unimplemented.
CMN + CMP have extended versions implemented for comparisons against the
stack pointer. More extended opcode implementations will need to follow.
Change-Id: I8db297aec73df818b20fe410297800c886701c76
uick/arm64/arm64_lir.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/utility_arm64.cc
|
| f72b7d6066238fd3faa25aac671dbaa02aeafac9 |
12-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: fix MarkGCCard, enabling more MIR opcodes."
|
| 3e1e549c564045d852ace46388eb06427d63e6ca |
12-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Add D/CHECK_CONSTEXPR macros for use in constexpr context."
|
| a5d74015f320306a770519748757d776b977ec56 |
12-Jun-2014 |
Ian Rogers <irogers@google.com> |
Fix typo comment by removing.
Change-Id: I09764f194317634164be9431328013205fba2910
uick/x86/int_x86.cc
|
| d8191d000413504b33702e0f52e1e8e522a47ec0 |
11-Jun-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: Add mul_long bytecode for X86-64
This patch implements the inlined version of the mul-long
bytecode for X86-64 platform.
Change-Id: I828e5861e17024d33f09223e0245380aef63a622
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/x86/int_x86.cc
|
| 836424805dd48af67088d30992a3f2e6841ca047 |
11-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Add D/CHECK_CONSTEXPR macros for use in constexpr context.
Make most RegStorage methods constexpr, make StorageSize()
const.
Change-Id: Ie63faa3b081094b3dd30352c6240fdf10ef8b87e
eg_storage.h
|
| c879aaec949f429c9b029bbbfaa76be8872cef0a |
11-Jun-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Update the DecodedInstruction for the Fused extended bytecodes."
|
| a194acf232b761b2ead114bdc6c38af112bf08cd |
12-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Clean up ArmMirToLir::LoadDispBody()/StoreDispBody()."
|
| 5487494e54e719d3bb4ead7a0b73e1d456fec8da |
11-Jun-2014 |
Ian Rogers <irogers@google.com> |
Workaround frame size issues.
x86 and x86-64 are exceeding the frame size for the switch interpreter.
The SOMETIMES_INLINE hack doesn't work with GCC as inline and the noinline
attribute are mutually exclusive. As a temporary solution move the effected
code to the the interpreter_common.cc file.
Bug: 14882674
Change-Id: Id5383ef5436046b36565cd1d76de8e3d59f42cff
uick/arm64/target_arm64.cc
|
| e1f65bcb957a65c6d45b319d968bc53a833f2c65 |
09-Jun-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: PassMEDataHolder should have a data field
For passes that would like to pass data around while working, let them actually
allocate it if need be in the Start, use it during the Worker, and
potentially free it during the End.
Change-Id: I03238ef17158f7e2615d6defe5d7f15432c8a511
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
b_optimizations.cc
b_optimizations.h
ass.h
ass_me.h
ost_opt_passes.cc
ost_opt_passes.h
|
| 33004d96271f5b6b9dfac165ea61102d0d55a303 |
16-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Clean up ARM load/store with offset imm8 << 2."
|
| 37573977769e9068874506050c62acd4e324d246 |
16-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up ARM load/store with offset imm8 << 2.
Change-Id: I95ed6860131b99eef7ed727f54745976949cbcb3
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
|
| 55884bc1e2e1b324809b462455ccaf5811ffafd8 |
10-Jun-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86_64: Proper IMT fix
Unfortunately, 97184: X86_64: Pass 'hidden method index' in EAX wasn't
correct. TargetReg(kInvokeTgt) is ALSO EAX, and so invoke-interface
blows up, since the saved index is overwritten by the generated code.
Change kInvokeTgt to EDI (the same as ARG0).
Change-Id: I4b1d260237274ee26b9283d810d1b74484ea59af
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/target_x86.cc
|
| c26efa86c02c214665d30760df9d6f370d1c9ef1 |
01-Jun-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Update the DecodedInstruction for the Fused extended bytecodes.
The BasicBlockOpt function creates extended MIRs but does not update the
associated DecodedInstruction. This results in an impossibility to re-create
the SSA algorithm.
Change-Id: I4a6393281e0ee52094f72f3de0001858c3d41ba3
Signed-off-by: Jean Christophe Beyler
ir_optimization.cc
|
| db9d523ff305721d4ca3f1470d1b2ce64c736e0a |
10-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up ArmMirToLir::LoadDispBody()/StoreDispBody().
Refactor the 64-bit load and store code to use a shared
helper function that can be used for any opcode with the
displacement limited to 8-bit value shifted by 2 (i.e. max
1020). Use that function also for 32-bit float load and
store as it is actually better than the old code for
offsets exceeding the 1020 byte limit.
Change-Id: I7dec38bae8cd9891420d2e92b1bac6138af5d64e
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
|
| fd2e291297463a3d5bdb18adc2a1eacbe2759152 |
06-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fix MarkGCCard, enabling more MIR opcodes.
Fixing register usage in MarkGCCard. Also enabling more MIR opcodes in
the compiler filter.
Change-Id: I877250f8deaefc69115e861344ca47cc5ccea8ff
rontend.cc
uick/arm64/call_arm64.cc
uick/arm64/utility_arm64.cc
|
| ea248f8b048d904a8fe806b6a52372985945274d |
10-Jun-2014 |
Ian Rogers <irogers@google.com> |
Remove TARGET_REX_SUPPORT define.
Change-Id: I1c3644176c101064261d13b50484d2e3ae456316
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| fd755e0034373eea3c4c420a870f6f6bbf729734 |
10-Jun-2014 |
Ian Rogers <irogers@google.com> |
Merge "X86_64: Pass 'hidden method index' in EAX"
|
| 0f9b9c508814a62c6e21c6a06cfe4de39b5036c0 |
09-Jun-2014 |
Ian Rogers <irogers@google.com> |
Tidy up x86 assembler and fix byte register encoding.
Also fix reg storage int size issues.
Also fix bad use of byte registers in GenInlinedCas.
Change-Id: Id47424f36f9000e051110553e0b51816910e2fe8
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| a0b0ba04bd733d487dfe5b443dbc72894d63a46a |
10-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "X86_64: Fix core.oat compilation issues"
|
| 846447a1d550771a78696f7ae05e066223e6b456 |
10-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Reduce dex2oat compilation logs"
|
| 88c3484eb7a9956f69f41ced53deeac126a258fc |
10-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: fix and enable sparse- and packed-switch."
|
| d3703d82a0afc28a4ea0cb0f6d88e9f8adc23e43 |
09-Jun-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86_64: Pass 'hidden method index' in EAX
Method* is in EDI, and EAX isn't an argument register, so EAX is free
to hold the hidden method index.
Change-Id: I793a54d00a4593e140f97144419d849b53bfdf44
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/gen_invoke.cc
uick/x86/target_x86.cc
|
| 30022aff96bfcce588cd15f8f46f3f720f69c471 |
06-Jun-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Reduce dex2oat compilation logs
Disable printing of all compiled methods to logcat.
Change-Id: Ie210809f2595cc25da688a4ad0363c258bcf9233
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
rontend.cc
|
| ade54a2fba4ec977dc4ff019004a2ba68e9ea075 |
09-Jun-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86_64: Fix core.oat compilation issues
Fix neg-long and X86Mir2Lir::GenInstanceofFinal
Change-Id: I7fbcc1a89857cc461f74b55573ac6cb7c8e64561
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
uick/x86/int_x86.cc
|
| 5acc8b0e23b12b481a9e97f84d084b79cd544319 |
05-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fix and enable sparse- and packed-switch.
Changed implementation of sparse- and packed-switch to use w and x
registers appropriately. Also added a couple of utilities to obtain a
w/s register corresponding to a given x/d register and viceversa.
Change-Id: I485a110f6e91b09227d9e2a0b8b14224a10bca90
rontend.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
|
| 2d41a655f4f0e4b2178bbd7e93901a5ed6eae4a6 |
09-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix kOpLsl, rem-float/double.
Change-Id: I6f7293493c0f94f96882d2e559e3eef659a23aec
uick/arm64/fp_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_invoke.cc
|
| a014776f4474579d4dfc72e3374ba45c6f6e5f35 |
07-Jun-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: Add long bytecode supports (2/2)
This patch adds implementation of math and complex long bytcodes,
and basic long arithmetic.
Change-Id: I811397d7e0ee8ad0d12b23d32ba58314d479d714
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/gen_common.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| e0ccdc0dd166136cd43e5f54201179a4496d33e8 |
07-Jun-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: Add long bytecode supports (1/2)
This patch includes switch enabling and GenFillArray,
assembler changes, updates of regalloc behavior for 64-bit,
usage in basic utility operations, loading constants,
and update for memory operations.
Change-Id: I6d8aa35a75c5fd01d69c38a770c3398d0188cc8a
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/gen_loadstore.cc
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 8550197244d470bf7645075e5400750f2cab4e42 |
07-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Hard Float ABI support in QCG"
|
| 58994cdb00b323339bd83828eddc53976048006f |
16-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Hard Float ABI support in QCG
This patch shows our efforts on resolving the ART limitations:
- passing "float"/"double" arguments via FPR
- passing "long" arguments via single GPR, not pair
- passing more than 3 agruments via GPR.
Work done:
- Extended SpecialTargetRegister enum with kARG4, kARG5, fARG4..fARG7.
- Created initial LoadArgRegs/GenDalvikX/FlushIns version in X86Mir2Lir.
- Unlimited number of long/double/float arguments support
- Refactored (v2)
Change-Id: I5deadd320b4341d5b2f50ba6fa4a98031abc3902
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
ompiler_enums.h
rontend.cc
uick/arm/target_arm.cc
uick/arm64/target_arm64.cc
uick/gen_invoke.cc
uick/mips/target_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 576ca0cd692c0b6ae70e776de91015b8ff000a08 |
07-Jun-2014 |
Ian Rogers <irogers@google.com> |
Reduce header files including header files.
Main focus is getting heap.h out of runtime.h.
Change-Id: I8d13dce8512816db2820a27b24f5866cc871a04b
uick/arm/call_arm.cc
uick/arm64/call_arm64.cc
uick/mips/call_mips.cc
uick/x86/call_x86.cc
|
| 14108093a9f31472ff0f400dd2d34b1d856b7d19 |
06-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Use ScopedArenaVector instead of std::vector in SSA transformation."
|
| 20aa7cbe93d782e0e756a36e70d610fe84b4bbb4 |
06-Jun-2014 |
Calin Juravle <calin@google.com> |
Merge "Fixed and refactored profiler options handling"
|
| c1b643cc6ac45dbd0eabdcd7425c7e86006c27d6 |
31-May-2014 |
Calin Juravle <calin@google.com> |
Fixed and refactored profiler options handling
- extracted profiler options in a separate class
- switched from system property reading to command line arguments
- added profile based compilation options to CompilerOptions
- removed no longer used kProfile compilation filter
- optimize dex files only if the profiler is enabled
- clean up unused arguments
Bug: 12877748
Bug: 15275634
Change-Id: I37ff68e7694370950ce8db2360562e9058ecebb7
rontend.cc
ir_analysis.cc
|
| c9360ce1f1dabb4075b09dd6db49ee6d4212a6fc |
05-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Use ScopedArenaVector instead of std::vector in SSA transformation.
Change-Id: Ibf8471274f2d5e11fcc185044745434c3c82ed74
ir_optimization_test.cc
sa_transformation.cc
|
| 04f4d8abe45d6e79eca983e057de76aea24b7df9 |
30-May-2014 |
Wei Jin <wejin@google.com> |
Add an optimization for removing redundant suspend tests in ART
This CL:
(1) eliminates redundant suspend checks (dominated by another check),
(2) removes the special treatment of the R4 register, which got
reset on every native call, possibly yielding long execution
sequences without any suspend checks, and
(3) fixes the absence of suspend checks in leaf methods.
(2) and (3) increase the frequency of suspend checks, which improves
the performance of GC and the accuracy of profile data. To
compensate for the increased number of checks, we implemented an
optimization that leverages dominance information to remove
redundant suspend checks on back edges. Based on the results of
running the Caffeine benchmark on Nexus 7, the patch performs
roughly 30% more useful suspend checks, spreading them much more
evenly along the execution trace, while incurring less than 1%
overhead. For flexibility consideration, this CL defines two flags
to control the enabling of optimizations. The original
implementation is the default.
Change-Id: I31e81a5b3c53030444dbe0434157274c9ab8640f
Signed-off-by: Wei Jin <wejin@google.com>
ir_graph.cc
ir_graph.h
uick/arm/arm_lir.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/mir_to_lir.cc
|
| 76af0d307194045ece429dbaf62e93d3e08c6c20 |
05-Jun-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Turn on 64-bit core registers initialization.
This enables 64-bit core registers initialization for x86_64.
The backend update with 64-bit temp support is in progress.
Change-Id: If7c9a62c1145f81050adda86f2beed427220baa2
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/target_x86.cc
|
| c029c98cc056bc247b69160f413ee7ce9a93d8c3 |
04-Jun-2014 |
Johnny Qiu <joqiu@nvidia.com> |
Update maximum number of reachable blocks in last step
Change-Id: I58e20d74fafdffd86ab3b7e4a1523b93abaae9a5
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
ir_graph.cc
|
| 089142cf1d0c028b5a7c703baf0b97f4a4ada3f7 |
05-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Avoid register pool allocations on the heap.
Create a helper template class ArrayRef and use it instead
of std::vector<> for register pools in target_<arch>.cc to
avoid these heap allocations during program startup.
Change-Id: I4ab0205af9c1d28a239c0a105fcdc60ba800a70a
uick/arm/target_arm.cc
uick/arm64/target_arm64.cc
uick/mips/target_mips.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/target_x86.cc
|
| 511c8a653d5896e81428393a1c3d427da64e36f3 |
03-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix cmp-long and method with long arguments.
1. Fix cmp-long.
2. Use single register to pass long argument.
3. Flush StackReference<ArtMethod> on arm64 the same as in common code.
3. Fix the mismatch in calculate reg offset.
Change-Id: Ie2723260fb143512e4da6ee88d4f3aded80d3d5e
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/gen_invoke.cc
|
| ca9da5090a946331ca5e72a39c6f70721d3b326c |
03-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Correct another RegStorage::Solo32"
|
| d44f1a6027b04c0d080089e6a8d87a4d19b5933f |
03-Jun-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Correct another RegStorage::Solo32
It should be RegStorage::FloatSolo32
Change-Id: Iadfc6654254e5a1d117b35cc2d88ceb7057cc30d
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/utility_x86.cc
|
| e997429dec7fd0682abc3c3f9885c64af1be6386 |
03-Jun-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: split list of opcodes in compiler filter."
|
| 87662da8f55e3a21ac8f4f6d970035708c933c0b |
03-Jun-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: reference cleanup"
|
| ec3f3d14915ec8f8c59bb88190928faa63ed9eb8 |
29-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: split list of opcodes in compiler filter.
Some of the opcodes that are currently enabled in the compiler
filter are generating assertion failures when using libartd.so.
In this patch, these opcodes are marked as experimental
via #if ... #endif and are disabled. This allows using libartd.so
to run the tests and for development. Further commits will follow
to fix the assertion issues.
Change-Id: I9493fddc281542cb15ced38b262f37f4ef4f0870
rontend.cc
|
| a0cd2d701f29e0bc6275f1b13c0edfd4ec391879 |
01-Jun-2014 |
buzbee <buzbee@google.com> |
Quick compiler: reference cleanup
For 32-bit targets, object references are 32 bits wide both in
Dalvik virtual registers and in core physical registers. Because of
this, object references and non-floating point values were both
handled as if they had the same register class (kCoreReg).
However, for 64-bit systems, references are 32 bits in Dalvik vregs, but
64 bits in physical registers. Although the same underlying physical
core registers will still be used for object reference and non-float
values, different register class views will be used to represent them.
For example, an object reference in arm64 might be held in x3 at some
point, while the same underlying physical register, w3, would be used
to hold a 32-bit int.
This CL breaks apart the handling of object reference and non-float values
to allow the proper register class (or register view) to be used. A
new register class, kRefReg, is introduced which will map to a 32-bit
core register on 32-bit targets, and 64-bit core registers on 64-bit
targets. From this point on, object references should be allocated
registers in the kRefReg class rather than kCoreReg.
Change-Id: I6166827daa8a0ea3af326940d56a6a14874f5810
ompiler_enums.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/target_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 03dbc04d1d5a3bd62801989b16e994a9ed0dafb5 |
02-Jun-2014 |
Ian Rogers <irogers@google.com> |
Make class status volatile.
Discourage loads and stores from reordering around the status being updated.
Bug: 15347354
Change-Id: Ice805cb834617747c8209e98a142d3e5c7585719
uick/gen_common.cc
|
| a4307aca310aac0ac62dcb5435daa02b1f950558 |
02-Jun-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Fix comments and link before MIR to next in Remove method
There are some comments without a period at the end and the remove does not
link the MIR before the one we want to remove to the one after.
Change-Id: Ia1263d3191e39b4f8f76ef62b28f7fbb1c6c0403
Signed-off-by: Jean Christophe Beyler jean.christophe.beyler@intel.com
ir_graph.cc
|
| e4283be97047a26d3476acd3863dcc386498be17 |
01-Jun-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: fix array overrun."
|
| 35ba7f3a78d38885ec54e61ed060d2771eeceea7 |
31-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix array overrun.
MIRGraph::InlineCalls() was using the MIR opcode to recover
Dalvik instruction flags - something that is only valid for
Dalvik opcodes and not the set of extended MIR opcodes.
This is probably the 3rd or 4th time we've had a bug using
the MIR opcode in situations that are only valid for the Dalvik
opcode subset. I took the opportunity to scan the code for
other cases of this (didn't find any), and did some cleanup while
I was in the neighborhood.
We should probably rework the DalvikOpcode/MirOpcode model whenver we
get around to removing DalvikInstruction from MIR.
Internal bug b/15352667: out-of-bound access in mir_optimization.cc
Change-Id: I75f06780468880892151e3cdd313e14bfbbaa489
rontend.cc
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ortable/mir_to_gbc.cc
uick/dex_file_method_inliner.cc
uick/mir_to_lir.cc
uick/x86/utility_x86.cc
reg_analysis.cc
|
| b20c373e45200102eaf2d4aac35d366067e0074b |
30-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: Enable extended MIR"
|
| 22460ecbaae7e489a3bc17a2adb2e7e9d0028f9c |
30-May-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: Method* as a reference"
|
| 3326027d2cc52463db3786a860cf238e8feb349e |
30-May-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: x86_64 workaround"
|
| fd5a852e49796374899772381f15c9033dae0057 |
30-May-2014 |
Narayan Kamath <narayan@google.com> |
Fix build.
Lint error due to a wrong #include guard.
Change-Id: I3b5d56c412580ec14f5c09b859a1bd6f9eb667ee
ass_driver_me_post_opt.h
ost_opt_passes.h
|
| 05e27ff942b42e123ea9519d13d31070ab96f0ac |
28-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable extended MIR
This patch enables all the extended MIR opcodes for ARM64. Please note
that currently the compiler will never generate these opcodes since the
BB optimisations are not enabled.
Change-Id: Ia712b071f62301db868297d37567795128b5bf2e
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
rontend.cc
ir_optimization.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
|
| 2469e60e6ff08c2a0b4cd1e209246c5d91027679 |
07-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Setting up cleanup
- Moved code around to actually have the clean-up code in a PassDriver format.
This allows us to better control what is being called after an optimization
It also allows the use of a centralized pass system for both optimizations
and cleanup.
Change-Id: I9d21e9bb9ee663739722f440d82adf04f73e380c
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
b_optimizations.cc
b_optimizations.h
rontend.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization_test.cc
ass_driver_me.cc
ass_driver_me.h
ass_driver_me_opts.cc
ass_driver_me_opts.h
ass_driver_me_post_opt.cc
ass_driver_me_post_opt.h
ass_me.h
ost_opt_passes.cc
ost_opt_passes.h
sa_transformation.cc
|
| d9f4c52071b305b777c7d7d08176b19882b393d8 |
30-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: x86_64 workaround
A recent CL changed the allocation of temp registers destined to
hold a reference such that on 64-bit systems a 64-bit register
would be allocated. However, for bring-up purposes, the x86_64
backend wants the ability to continue holding long values in a
register pair.
Change-Id: I25d9f755fafbe96144226677f85c6d5cad1ffa76
uick/ralloc_util.cc
|
| f2c3e564fa9e484c29f35f10d4659ab2d7b8614a |
29-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: Method* as a reference
This is the first of two CLs intended to fix up and make consistent
the handling of references in the Quick backend. A sibling
CL c/96237 updates the runtime to treat Method* as a compressed
reference when stored. This CL makes a similar change for the
backend.
As far as the general handling of in-register references, though,
the current Quick backend is not consistent even for non-Method*
references. Sometimes they are treated as references, but other
times are handled as if they were 32-bit ints. A subsequent CL
will deal with that issue.
Change-Id: I5591c5eea6cca6ed22208ab806fd38b959c9d03d
uick/gen_invoke.cc
reg_analysis.cc
|
| ea0b6e284cab12eed88eebf6aa19e6292af57389 |
29-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: fixing some assertions."
|
| 2ac01fc279e8397beacf90302b0f215040eb78fa |
22-May-2014 |
Vladimir Marko <vmarko@google.com> |
Improve tracking of memory locations in LVN.
Rewrite the tracking of values stored in memory to allow
recognizing the same value after storing it in memory and
loading it back to vreg. Drop reliance on value name
ordering for memory versioning in preparation for GVN.
Also fix a few minor issues in LVN.
Change-Id: Ifabe2d47d669d9ec43942cea6fd157e41af77ec8
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_optimization.cc
|
| 0955f7e470fb733aef07096536e9fba7c99250aa |
23-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fixing some assertions.
Fixing some assertions while attempting to get libartd.so to work.
Fixing also the shift logic in LoadBaseIndexed() and StoreBaseIndexed().
This commit only fixes a part of the assertion issues.
Change-Id: I473194d4260dd59a8ee6d73114429728c977ee0e
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
|
| a9f1ce6fbe8a9247d0d8e20727f590b091e816da |
28-May-2014 |
Vladimir Marko <vmarko@google.com> |
Fix pass driver's dump_pass_list_ and print_pass_list_.
The lists were allocated with new char[], so they should
have been held by std::unique_ptr<const char[]> rather than
std::unique_ptr<const char>. However, it's much cleaner with
std::string.
Change-Id: Ie7c604773272194345f5e6e3c4803c3a914edf99
ass_driver.h
ass_driver_me.cc
|
| 6d25996baef5037d0aa8beb2f517755f2fb7b91f |
28-May-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Print and dump functionalities per pass"
|
| 32f38c0775aba280fe02e8fafe0d35a5debc4eac |
28-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Support r8-r15, xmm8-xmm15 in assembler"
|
| 32c02c15b879174bb8ae13b964ba1f49eb5c6e70 |
28-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Add 64-bit version of instructions in asm"
|
| a20468c004264592f309a548fc71ba62a69b8742 |
30-Apr-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Support r8-r15, xmm8-xmm15 in assembler
Added REX support. The TARGET_REX_SUPPORT should be used during build.
Change-Id: I82b457ff5085c8192ad873923bd939fbb91022ce
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 33a60e47278d09acfa44d92ad85b1902b57a6b5b |
27-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Set the type of a RegStorage correctly"
|
| 67c482f6737343f3afbf214995d67d98b0b36c91 |
27-May-2014 |
buzbee <buzbee@google.com> |
Merge "Art compiler: remove unnecessary sqrt call"
|
| 055c29fd0f752328981f1b7ccadb1862eecedd40 |
27-May-2014 |
buzbee <buzbee@google.com> |
Art compiler: remove unnecessary sqrt call
For reasons lost in the mists of time, the Dalvik JIT tested
the results of an inlined sqrt for NaN on Arm targets, and then
called an out-of-line routine to recompute if true. The Quick
compiler inherited this behavior. It is not necessary, and the CL
purges it (along with the out-of-line sqrt entrypoint).
Change-Id: I8c8fa6feacf9b7c3b9e190dfc6f728932fd948c6
uick/arm/fp_arm.cc
|
| 6c35a6ba61a190cfd3698bba0aa14038a0867cfe |
27-May-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: generalize NarrowRegLoc()"
|
| 0c52451e9be14a6bff9ffefce89ff1d60691af60 |
27-May-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Set the type of a RegStorage correctly
This will be used as a FP value, so call the right function to create
the RegStorage.
Change-Id: I2bd832746afac509d20f195a7770f2fbd215cbd7
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/utility_x86.cc
|
| 96992e8f2eddba05dc38a15cc7d4e705e8db4022 |
19-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Add 64-bit version of instructions in asm
Add missed 64-bit versions of instructions.
Change-Id: I8151484d909dff487cb7e521494a0be249a42214
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 8bceccec7eddff8cd872aa20505b4a3a6be60a16 |
29-Apr-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Print and dump functionalities per pass
LOG is a great logging tool but sometimes a pass has some debugging text it
want to be able to turn on/off easily.
By going via a print_pass flag, we can actually turn it on/off easily per pass
when debugging/instrumenting.
- Added a pass printer to help debug messages for future passes.
- Added a print_pass flag in CompilationUnit to filter out messages.
At the same time, did a similar system for dumping the CFG.
- Also moved some API into public from protected.
Change-Id: Ie0e89a8fc773e8583f3e4ffd6e4bd2eebdbb2bf4
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
ompiler_ir.h
rontend.cc
ass.h
ass_driver.h
ass_driver_me.cc
|
| ab5b370e44629332e73ffd66bfe8b8a924236c5c |
27-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: Add suspend check in managed code."
|
| bbc66c5855fa4f36b6f94311607f0119a93d809a |
27-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Better SSA Allocation when recreating SSA"
|
| 4896d7b6fb75add25f2d6ba84346ac83d8ba9d51 |
02-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Better SSA Allocation when recreating SSA
The SSA calculation is not allocation friendly. This makes the
SSARepresentation remember how much is allocated and not reallocate
if SSA should be recalculated.
Also added some allocation friendly code for the dominance code.
Change-Id: Icd5586b7e2fefae8e1535975ab400b1ca95b500f
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ir_dataflow.cc
ir_graph.cc
ir_graph.h
sa_transformation.cc
|
| 032d3775552e27eda98af2066306b773f3762b64 |
23-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable FLOAT and DOUBLE opcodes
This patch enables all the DOUBLE and FLOAT opcodes except for REM ones.
It has been tested and passes all Dalvik tests except for:
failed: 018-stack-overflow[pid=1076]
failed: 107-int-math2[pid=1593]
Change-Id: I581f219bde354e3402aa3ad6e24ef15566da5f78
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
ompiler_enums.h
rontend.cc
uick/arm64/fp_arm64.cc
|
| 48241e786121e1c4c050d9cfad3d22de270a3e75 |
23-May-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Add suspend check in managed code.
TODO: Remove x19 in the frame in runtime, generic jni, compiled jni.
Change-Id: Ibdc292c9e7adb3a5d3eff353c22f60ffc101f549
rontend.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
|
| 85089dd28a39dd20f42ac258398b2a08668f9ef1 |
26-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: generalize NarrowRegLoc()
Some of the RegStorage utilites (DoubleToLowSingle(),
DoubleToHighSingle(), etc.) worked only for targets which
which treat double precision registers as a pair of aliased
single precision registers.
This CL elminates those utilities, and replaces them with
a new RegisterInfo utility that will search an aliased register
set and return the member matching the required storage
configuration (if it exists).
Change-Id: Iff5de10f467d20a56e1a89df9fbf30d1cf63c240
uick/arm/fp_arm.cc
uick/arm/target_arm.cc
uick/codegen_util.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
eg_storage.h
|
| cd9b4e287c20b14655d21e3f349733e80a5aaf23 |
24-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Rebase on top of "64-bit temp register support""
|
| fe94578b63380f464c3abd5c156b7b31d068db6c |
22-May-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Implement all vector instructions for X86
Add X86 code generation for the vector operations. Added support for
X86 disassembler for the new instructions.
Change-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
eg_storage.h
|
| 8c895b3385ed96a0b040c35222c0338058895d49 |
24-May-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: fix register clobbering."
|
| 642fe34958ba7fafa81341823241616edde0380c |
24-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix register clobbering.
Ensure all aliased children of a register set are clobbered
when any member is clobbered. Additionally, use a clobbering
mask to avoid clobbering non-overlapping siblings.
Change-Id: Ic0d88a30f3e5b7a359396f6541d602739fa3124a
uick/mir_to_lir.h
uick/ralloc_util.cc
|
| 0999a6f7c83d10aa59b75f079f0d2fdbac982cf7 |
21-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Rebase on top of "64-bit temp register support"
Added the 64-bit core/temp register definition, fixed RegisterPool
creation for x86_64 so that 64-bit core/temps are NOT used for now.
The long arithmetic still operates with register pair on x86_64 and
it is a subject for change in a separate patch.
Change-Id: I2be06d5aefaf80141983bc9d8ed8a2ee24c2b21b
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 919ed6b2e2aa58a6153eb1d74edc29edc50d514a |
24-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Revert "ART: Better SSA Allocation when recreating SSA""
|
| d4750f202170a448119c1813a964574bfea0dded |
24-May-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "ART: Better SSA Allocation when recreating SSA"
Temporarily reverting until memory footprint cost of adding a vreg to ssa entrance map on every applicable MIR node can be assessed..
This reverts commit cb73fb35e5f7c575ed491c0c8e2d2b1a0a22ea2e.
Change-Id: Ia9c03bfc5d365ad8d8b949e870f1e3bcda7f9a54
ir_dataflow.cc
ir_graph.cc
ir_graph.h
sa_transformation.cc
|
| be7ba65210f0eb9cd86b3b76337020b039191ba6 |
24-May-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Better SSA Allocation when recreating SSA"
|
| 8512758d1208d3c32bf67db9c925b8fc6e077fd7 |
12-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: BasicBlock API Implementation
- Adding BasicBlock Utility functions.
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Change-Id: Ia264b4e68a9a56441ca143f1d98e5a333cf87b29
ir_graph.cc
ir_graph.h
|
| 82f3c1b76a19f196a482cad9d5c1aac769d5a397 |
23-May-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: API to dex instructions"
|
| e24580a135aa6e85cdc49426ec74d2ae1e326243 |
23-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Rewrite BitVector index iterator."
|
| a5b8fde2d2bc3167078694fad417fddfe442a6fd |
23-May-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite BitVector index iterator.
The BitVector::Iterator was not iterating over the bits but
rather over indexes of the set bits. Therefore, we rename it
to IndexIterator and provide a BitVector::Indexes() to get
a container-style interface with begin() and end() for range
based for loops.
Also, simplify InsertPhiNodes where the tmp_blocks isn't
needed since the phi_nodes and input_blocks cannot lose any
blocks in subsequent iterations, so we can do the Union()
directly in those bit vectors and we need to repeat the loop
only if we have new input_blocks, rather than on phi_nodes
change. And move the temporary bit vectors to scoped arena.
Change-Id: I6cb87a2f60724eeef67c6aaa34b36ed5acde6d43
b_optimizations.cc
b_optimizations.h
it_vector_block_iterator.cc
it_vector_block_iterator.h
ir_graph.cc
ir_graph.h
sa_transformation.cc
|
| 61bc2b3770c8078c7dbe1a9fd4faf0ab1c129701 |
23-May-2014 |
Vladimir Marko <vmarko@google.com> |
Remove obsolete pass_driver.cc .
Obsoleted by https://android-review.googlesource.com/93433 .
Change-Id: I01865d17160fdc698f43c61fa4f5642d0f1391d9
ass_driver.cc
|
| 567e9dbc65ee183cda2a052dbf224c8c4a8f9423 |
23-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Disable optimizations on x86_64"
|
| 4c80043aa75d0dfa62dd2fd1845bc2b92110336d |
07-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Disable all intrinsics
Intrinsics are subject to rework for x86_64 and disabled for now.
Change-Id: Ice67db083fe43dc4faa9276faf02234a4a24f207
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/gen_invoke.cc
|
| ba279d9b7b3fd065ffbeae6b2dc2997af2d20aa4 |
16-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Disable optimizations on x86_64
This patch disables all QCG optimizations as ARM64 does.
Optimizations are subject to step-by-step enabling according
to test results.
Change-Id: Idd6e10f3b67e8c0f1f029bb26a0e9bf40061aeac
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
rontend.cc
|
| d293fb40cf1cd23ead34f6002da037cead69cba2 |
19-May-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86: For integer ALU operation handle v+=v case
When destination and operand are the same Virtual Register
we should ensure that destination RegLocation is updated after
operand is loaded with LoadValue in physical register.
Change-Id: I59da106471b0c494203af01c99583f51dbc0f9ee
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/int_x86.cc
|
| 54d36b6bf280c22ae69280feffa9d65d6417b153 |
23-May-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
Create two CompilerTemp for a wide compiler temp
We create a new CompilerTemp for the high part of
a wide compiler temp to fix counting compiler temps.
Otherwise, assertion failures may happen inside
GetNumUsedCompilerTemps(), if there are any wide compiler temps.
Previously, we never ask for a wide compiler temp, such that
we don't hit the issue.
Change-Id: I9e79ad15e4192665b9d8a9dae5a5453496e48a79
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
ir_optimization.cc
|
| 5ef3d95466ffdea0f4348a64218d08b1b5a29aa7 |
23-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: Enable LONG_* and INT_* opcodes."
|
| c3db20b7e6f847339d6ecbd89846c173a7ccc967 |
06-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: API to dex instructions
- Added the GetConstant function call in DecodedInstruction.
- Added a few rewriter helper functions for later higher level rewriting.
- Added Setter/Getter data and query functions.
- Added Clobber memory/Const/Call/Cast data and query functions.
- Added expression information (add, multiply, ...).
- Added a IsLinear function for additions and subtractions.
- Added an empty constructor for the DecodedInstruction:
- Useful for the creation of a MIR constructor too.
- Added the IsConditionalBranch utility function.
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Change-Id: Ie21f2a7779b38c1b383334f04126c2d792cae462
ir_graph.cc
ir_graph.h
|
| 44e5bdec17d0528b90cc0773be2beb76dcafdc5b |
29-Apr-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Topological Sort Traversal Implementation
- Added a topological sort implementation for traversal.
- Useful for traversals that require traversing the predecessors first.
- Added a function to BasicBlock to detect if it is an exception block.
Change-Id: I573da1768a635c6fd0259573dbb46b112132e129
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
ataflow_iterator.h
ir_graph.cc
ir_graph.h
ass.h
ass_driver.cc
ass_me.h
|
| ed65c5e982705defdb597d94d1aa3f2997239c9b |
22-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable LONG_* and INT_* opcodes.
This patch fixes some of the issues with LONG and INT opcodes. The patch
has been tested and passes all the dalvik tests except for 018 and 107.
Change-Id: Idd1923ed935ee8236ab0c7e5fa969eaefeea8708
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
rontend.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
eg_storage.h
|
| 4f59668b3d51f63601ebe59dbd2b7e8a7c5bd093 |
01-May-2014 |
James C Scott <james.c.scott@intel.com> |
ART: Pass driver generalization
- Generalizing Pass Driver.
- Migrating ME Pass Driver to use the new generalized Pass Driver.
There will be some more changes after in the compiler code to generalize
it a bit more by separating what is being done by the optimizing passes
and post-pass cleanups.
Change-Id: I140a70e88483d7c3991b7d336bd593b2613ae194
Signed-off-by: James C Scott <james.c.scott@intel.com>
b_optimizations.cc
b_optimizations.h
rontend.cc
ass.h
ass_driver.h
ass_driver_me.cc
ass_driver_me.h
ass_me.h
|
| 3aa57730e2aec451bb836918d936c6862598d8d6 |
17-Apr-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: MIR, SSARepresentation, and BasicBlock Additional API
Adding the API calls to the MIR structure to help with higher level code.
Some code has been added to BasicBlock as well for the removal.
Some code has also been added to SSARepresentation.
A constructor has been added to DecodedInstruction.
Change-Id: Ie65948d53d83fd8250545c94c88b442a68d702c7
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
ir_graph.cc
ir_graph.h
uick/dex_file_method_inliner.cc
sa_transformation.cc
|
| 481b4027849c8c8b0f6f25a2d5c460e11f8eb64d |
22-May-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: free up space in MIR."
|
| 7bf9c46e93c6f7551f2645cf9bbd1ec9f797c86c |
22-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Method inlining across dex files in boot image."
|
| a51a0b0300268b605e3ad71b0e87ff394032c5e7 |
21-May-2014 |
Vladimir Marko <vmarko@google.com> |
Method inlining across dex files in boot image.
Fix LoadCodeAddress() and LoadMethodAddress() to use the dex
file in addition to the method index to uniquely identify
the literal. With that fix in place, when we have both the
direct code and the direct method, we can safely pass the
actual target method id instead of the method id from the
same dex file in the method lowering info. This was already
done for calls from apps into boot image (and thus there was
a bug with a tiny risk of the wrong literal being used) and
now we also do that for calls within the boot image. The
latter allows the inlining pass to inline many more methods
than before in the boot image.
Bug: 15021903
Change-Id: Ic765ce9809b43ef07e7db32b8e3fbc9acb09147f
uick/codegen_util.cc
uick/mir_to_lir.h
|
| ef562fdef7e0071cae11e07a9e53fb152d0934b8 |
21-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: free up space in MIR.
The width field in MIR isn't especially useful - it could always
be recalculated from the Dalvik instruction. This CL eliminates
it to allow the 16 bits it occupied to be used for the ID of the
parent BasicBlock.
Change-Id: I75ab8562ca217f0f819ecfc417014dee74bc587e
ocal_value_numbering_test.cc
ir_graph.cc
ir_graph.h
ir_optimization_test.cc
uick/dex_file_method_inliner.cc
|
| b01bf15d18f9b08d77e7a3c6e2897af0e02bf8ca |
14-May-2014 |
buzbee <buzbee@google.com> |
64-bit temp register support.
Add a 64-bit temp register allocation path. The recent physical
register handling rework supports multiple views of the same
physical register (or, such as for Arm's float/double regs,
different parts of the same physical register).
This CL adds a 64-bit core register view for 64-bit targets. In
short, each core register will have a 64-bit name, and a 32-bit
name. The different views will be kept in separate register pools,
but aliasing will be tracked. The core temp register allocation
routines will be largely identical - except for 32-bit targets,
which will continue to use pairs of 32-bit core registers for holding
long values.
Change-Id: I8f118e845eac7903ad8b6dcec1952f185023c053
rontend.cc
rontend.h
uick/arm/codegen_arm.h
uick/arm/target_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/codegen_util.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| 9593976c3753b6ff6390cd022d70ed7e116dc847 |
20-May-2014 |
Ian Rogers <irogers@google.com> |
Merge "Allow X86 QBE to be extended"
|
| e87f9b5185379c8cf8392d65a63e7bf7e51b97e7 |
30-Apr-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Allow X86 QBE to be extended
Enhancements and updates to allow X86Mir2LIR Backend to be subclassed
for experimentation. Add virtual in a whole bunch of places, and make
some other changes to get this to work.
Change-Id: I0980a19bc5d5725f91660f98c95f1f51c17ee9b6
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
ir_graph.h
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 9cdf48e03c302e03e2ec118a22cbdfae460b1665 |
20-May-2014 |
buzbee <buzbee@google.com> |
Arm64 - update fp callee save base
Hit commit button too quickly - this should have been part
of CL 95013.
Change-Id: I4a733414db74d6e9cab2d8fbe2eb9b398fff3f45
uick/arm64/arm64_lir.h
|
| 214eee43f1507b3bc8595bf0d438ba97d21dc7a3 |
20-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: fixes in A64 code generation."
|
| 607fa7b07233a7233ebe21bba8f3e7c1925ae0f2 |
20-May-2014 |
Ian Rogers <irogers@google.com> |
Merge "Now we have a proper C++ library, use std::unique_ptr."
|
| 700a402244a1a423da4f3ba8032459f4b65fa18f |
20-May-2014 |
Ian Rogers <irogers@google.com> |
Now we have a proper C++ library, use std::unique_ptr.
Also remove the Android.libcxx.mk and other bits of stlport compatibility
mechanics.
Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
ompiler_ir.h
rontend.h
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_analysis.cc
ir_graph.h
ir_optimization.cc
uick/codegen_util.cc
sa_transformation.cc
erified_method.cc
|
| 082833c8d577db0b2bebc100602f31e4e971613e |
18-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler, out of registers fix
It turns out that the register pool sanity checker was not
working as expected, leaving some inconsistencies unreported.
This could result in "out of registers" failures, as well
as other more subtle problems.
This CL fixes the sanity checker, adds a lot more check and cleans
up the previously undetected episodes of insanity.
Cherry-pick of internal change 468162
Change-Id: Id2da97e99105a4c272c5fd256205a94b904ecea8
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| bc6d197cdb02eeac0c98ec4ed37f530b003a4e7a |
13-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fixes in A64 code generation.
- Disabled special method compilation, as it requires hard-float ABI,
- Disabled suspend checks, as runtime is not yet ready (e.g. trampolines
are not setting the suspend register, etc),
- Changing definition of zero register (the zero register has now 0x3f
as its register number),
- Fixing some issues with handling of cmp instructions in the assembler:
we now use the shift-register rather than the extended-register variant
of cmp and cmn,
- Partially fixing register setup (register sN is now mapped to dN),
- Fixing and completing implementation of register spills/unspills,
- Fixing LoadBaseDispBody() and StoreBaseDispBody().
Change-Id: Ia49ba48b6ca0f782380066345b7a198cb6c1dc1d
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
|
| d65c51a556e6649db4e18bd083c8fec37607a442 |
29-Apr-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Add support for constant vector literals
Add in some vector instructions. Implement the ConstVector
instruction, which takes 4 words of data and loads it into
an XMM register.
Initially, only the ConstVector MIR opcode is implemented. Others will
be added after this one goes in.
Change-Id: I5c79bc8b7de9030ef1c213fc8b227debc47f6337
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
ompiler_enums.h
ir_graph.cc
uick/codegen_util.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 1e97c4a4ab9f17d1394b952882d59d894b1e3c74 |
16-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Add x86_64 code generation support"
|
| c830430ed65497c2268649d8e78121364e31b184 |
15-May-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix quick compiler monitor implementation.
Also with some small fixes :
1. Enable some dex byte code to compile.
2. Copy the register definition from runtime.cc.
3. A quick fix for "cmp Wn, Wm" in the assembler.
4. Optimise GenMoveException a bit by using xzr.
5. Fix improper use of StoreValueWide() on 32-bit value in FlushIns().
6. Fix one debug assert in the assembler.
It can pass all cases in run-all-test, except 044 which also fails with
the interpreter.
Change-Id: I9cc0253f1039c78d5100640235ac33e884b02560
rontend.cc
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/target_arm64.cc
|
| 380d24d9af676d047148083774fa634b77a00634 |
16-May-2014 |
Ian Rogers <irogers@google.com> |
Merge "Compatibility layer to transition from UniquePtr to std::unique_ptr."
|
| 507dfdd147c97bfbadebfd63584d094b6a4e7b47 |
16-May-2014 |
Ian Rogers <irogers@google.com> |
Compatibility layer to transition from UniquePtr to std::unique_ptr.
Use ART_WITH_STLPORT (enabled for the target) to cause the use of UniquePtr,
for the host switch to std::unique_ptr. For now the type remains called
UniquePtr.
Make dalvik compile with clang on the host, move its build to C++11.
Change-Id: I5ba8d2757904bc089ed62047ea03de3c0853fb12
ocal_value_numbering.h
ir_analysis.cc
erified_method.cc
|
| e1a71b2a6e899645b006c29ba37695f521545a5b |
16-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: A Compile Filter for x86_64"
|
| 13ff8cd5d29c66de49506b0d7dddf8e0a959e104 |
15-May-2014 |
Bill Buzbee <buzbee@google.com> |
Merge "Quick Compiler: fix Arm cts failures"
|
| fe8cf8b1c1b4af0f8b4bb639576f7a5fc59f52ea |
15-May-2014 |
Bill Buzbee <buzbee@google.com> |
Quick Compiler: fix Arm cts failures
Fixes move_wide_16#testN1, move_wide_16#testN2
Two bugs for the price of one (thanks CTS!)
First, the new stack overflow checking code was broken for very
large frames. For Arm on method entry, we only have 1 available
temp register, r12, until argument registers are flushed.
Previously, for explicit checks on large frames,
r12 was immediately loaded with the stack_end value. However,
later on when the frame is extended, if the frame size exceeds
the range of a reg-reg-imm subtract, the codegen utilities will
allocate a new temporary register to complete the operation. r12
was getting clobbered. Similarly, for medium-large frames r12
could get clobbered during frame creation.
What we should always do when directly using fixed registers like
this is to lock them to prevent them from being allocated as a
temp. The other half of the first bug is easily solved by delaying
the load of stack_end until after the new sp is computed. We'll
increase the stall cost, but this is an uncommon case.
The second bug was likely a typo in LoadValueDisp(). I'm a bit
surprised we hadn't hit this one earlier - but perhaps it was
recently introduced. The wrong base register was being used in
the non-float, wide, excessive offset case (which I suppose is also
somewhat uncommon).
Cherry-pick of internal commit If5b30f729e31d86db604045dd7581fd4626e0b55
Change-Id: If5b30f729e31d86db604045dd7581fd4626e0b55
uick/arm/call_arm.cc
uick/arm/utility_arm.cc
|
| b2c3e10deb6a2f069748c7a48e778a5da66900fd |
15-May-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix MonitorExit code on ARM"
|
| b14329f90f725af0f67c45dfcb94933a426d63ce |
15-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix MonitorExit code on ARM
We do not emit barriers on non-SMP systems. But on ARM, we have
places that need to conditionally execute, which is done through
an IT instruction. The guide of said instruction thus changes
between SMP and non-SMP systems.
To cleanly approach this, change the API so that GenMemBarrier
returns whether it generated an instruction. ARM will have to
query the result and update any dependent IT.
Throw a build system error if TARGET_CPU_SMP is not set.
Fix runtime/Android.mk to work with new multilib host.
Bug: 14989275
Change-Id: I9e611b770e8a1cd4ca19367d7dae0573ec08dc61
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| 93dcff30c9bea0d6c7ca3a71a1bf460336c3467d |
15-May-2014 |
Ian Rogers <irogers@google.com> |
Fix CompilationUnit constructor issues.
Ensure target64 is initialized. Switch from NULL to nullptr as the former gives
compilation errors with std::unique_ptr from libc++.
Change-Id: I7153368d9324d10ef257f7c7ce9571a1753e5ba8
rontend.cc
|
| a1926cdbd05314accb55cc7d8fcb37fb361bbf8a |
15-May-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Fix ARM dmb placement in monitor-exit"
|
| f54fcba62745f897b9e741594dc5f4b2143601f6 |
14-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Support any cpu register sequence in LoadArgRegs"
|
| 5c13d43f69a5c893b4ee7abf02772ad526b3d263 |
14-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "x86_64: Handle UnsafeGet/Put equal to x86"
|
| d115735fe5523ff72319f0968f773683323c7f79 |
14-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix special getter/setter to use RegClassForFieldLoadStore()."
|
| c93ac8b73b5772e43b6dd1cc9e1deee79ca68849 |
13-May-2014 |
Vladimir Marko <vmarko@google.com> |
Fix special getter/setter to use RegClassForFieldLoadStore().
This ensures correct register class is used for volatile
load/store in these getters and setters.
Bug: 14112919
Change-Id: Ib7aa83d441fb007e97f9acc2a778bc20ffed837c
uick/mir_to_lir.cc
uick/mir_to_lir.h
|
| 5678455bdf9ebf2bd88ab39a9aeb6e08b7c6e245 |
12-May-2014 |
Vladimir Kostyukov <vladimir.kostyukov@intel.com> |
ART: A Compile Filter for x86_64
This patch enables an x86_64 compile filter for everything
we're not ready to compile right now.
Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
Change-Id: I9ba87cf7f05e3465f12fd16a87b54f9649baf88a
rontend.cc
|
| 26ee07a9dbdff5d7ea61ff412e5fb7f510972aad |
12-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
Support any cpu register sequence in LoadArgRegs
The LoadArgRegs was designed only for case when
arg1.reg < arg2.reg < arg3.reg which is not true for x86_64 ABI.
Now LoadArgRegs supports three args passed by any cpu register.
Change-Id: I62f58c47ec12b8e3f8124724cb3b5371dde8173f
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/gen_invoke.cc
|
| 9bf549d472462e4d1888a97c218a8c26fe3bfefb |
12-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Handle UnsafeGet/Put equal to x86
This patch extends "Handle x86_64 architecture equal to x86"
and covers UnsafeGet/UnsafePut.
Change-Id: Ib07cfc217c7825cff0b49cfbb9151452d62b1b68
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/gen_invoke.cc
|
| 9b9dec8bbcb812315eb0b68b3465c6c567f09527 |
14-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix ARM dmb placement in monitor-exit
This moves the dmb in quick-compiled monitor-exit before the str
perfoming the unlock.
Change-Id: I231f98ff21eb7bac45b4a1b7ff57316deeb858cc
uick/arm/call_arm.cc
|
| eb8167a4f4d27fce0530f6724ab8032610cd146b |
08-May-2014 |
Mathieu Chartier <mathieuc@google.com> |
Add Handle/HandleScope and delete SirtRef.
Delete SirtRef and replaced it with Handle. Handles are value types
which wrap around StackReference*.
Renamed StackIndirectReferenceTable to HandleScope.
Added a scoped handle wrapper which wraps around an Object** and
restores it in its destructor.
Renamed Handle::get -> Get.
Bug: 8473721
Change-Id: Idbfebd4f35af629f0f43931b7c5184b334822c7a
ir_field_info.cc
ir_method_info.cc
|
| 9ee801f5308aa3c62ae3bedae2658612762ffb91 |
12-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
Add x86_64 code generation support
Utilizes r0..r7 in register allocator, implements spill/unsill
core regs as well as operations with stack pointer.
Change-Id: I973d5a1acb9aa735f6832df3d440185d9e896c67
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_storage.h
|
| 3ec5da20f27da3bb8cea7ae29538c30c4b1549b4 |
13-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix typo in ThreadOffset modification
Change-Id: Ifc3bd44a2a8442dcc242f4abcb17ae2acbc3b4e7
uick/gen_invoke.cc
|
| 2f244e9faccfcca68af3c5484c397a01a1c3a342 |
08-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Add more ThreadOffset in Mir2Lir and backends
This duplicates all methods with ThreadOffset parameters, so that
both ThreadOffset<4> and ThreadOffset<8> can be handled. Dynamic
checks against the compilation unit's instruction set determine
which pointer size to use and therefore which methods to call.
Methods with unsupported pointer sizes should fatally fail, as
this indicates an issue during method selection.
Change-Id: Ifdb445b3732d3dc5e6a220db57374a55e91e1bf6
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/arm64_lir.h
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 0c5e8417a1e82f6e31fbfc33be7e64d9073d6ef4 |
13-May-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: fix compile-time perf regression"
|
| ba57451494946a128703e1cbd8bf5969ee8dc598 |
13-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix compile-time perf regression
The recent changes to the temp register liveness tracking
introduced a measureable compile-time performance regression.
This CL cleans it up.
Change-Id: Id698b93e957f0ecab7ddfab94727f85e49cf10cf
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
|
| 0dc242d6fc1254e6ca1c31e08e612bbf45644b17 |
12-May-2014 |
Vladimir Marko <vmarko@google.com> |
Avoid unnecessary copy/load in EvalLoc() and LoadValue().
EvalLoc()/EvalLocWide() are used to prepare a register where
a value is subsequently stored, so they shouldn't copy the
old value to the new register for register class mismatch.
The only exception where we actually need a copy is
LoadValue()/LoadValueWide(), so we inline the old code that
makes the copy there. We also avoid loading inexpensive
constants when the value is already in the register.
Change-Id: I07519e9d4d9b3f7272233d196435f3035e4a3ca9
uick/gen_loadstore.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/int_x86.cc
|
| d111c6eeb01955964d9c7f68126adcb1e1824ab3 |
12-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: RegStorage tweak
Previously, the RegStorage struct allowed for up to 32 physical
registers per register class. Although this is sufficient to
handle instruction encodings for all targets, some targets may
re-use the register number encoding for different physical elements.
For example, Arm64 uses register encoding 0x1f for both the stack
pointer and the zero register. This change adds a bit to the low
register number, allowing 0..63. Targets can use this extra
encoding space to differentiate between multiple uses of the same
encoding pattern.
Change-Id: I11f2ebbce8865a08627eef5868bb51fae6421c33
eg_storage.h
|
| e1910f1d802dff79bba5ef61e1c4fd0b95f6e5b0 |
11-May-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: Fix liveness tracking"
|
| 30adc7383a74eb3cb6db3bf42cea3a5595055ce1 |
10-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: Fix liveness tracking
Rework temp register liveness tracking to play nicely with aliased
physical registers, and re-enable liveness tracking optimization.
Add a pair of x86 utility routines that act like UpdateLoc(),
but only show in-register live temps if they are of the expected
register class.
Change-Id: I92779e0da2554689103e7488025be281f1a58989
rontend.cc
uick/gen_loadstore.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 90cf3eefb4cd4dbd7ccd514738055b4d193981fe |
09-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Clean up ScopedArenaAllocatorAdapter."
|
| 69f08baaa4b70ce32a258f3da43cf12f2a034696 |
11-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up ScopedArenaAllocatorAdapter.
Make the adapter equality-comparable, define aliases for
containers using the adapter and use those aliases.
Fix DebugStackIndirectTopRefImpl assignment.
Change-Id: I689aa8a93d169f63a659dec5040567d7b1343277
ocal_value_numbering.h
ir_analysis.cc
ir_optimization.cc
|
| 674744e635ddbdfb311fbd25b5a27356560d30c3 |
24-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Use atomic load/store for volatile IGET/IPUT/SGET/SPUT.
Bug: 14112919
Change-Id: I79316f438dd3adea9b2653ffc968af83671ad282
uick/arm/codegen_arm.h
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 8b1f6050ae4f6291d0ed082cf5d2efed2da0eef4 |
08-May-2014 |
Ian Rogers <irogers@google.com> |
Merge "X86: EmitArrayImm shouldn't truncate to 16 bits"
|
| e45fb9e7976c8462b94a58ad60b006b0eacec49f |
06-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Change arm64 backend to produce A64 code.
The arm backend clone is changed to produce A64 code. At the moment
this backend can only compile simple methods (both leaf and non-leaf).
Most of the work on the assembler (assembler_arm64.cc) has been done.
Some work on the LIR generation layer (functions such as OpRegRegImm
& friends) is still necessary. The register allocator still needs to
be adapted to the A64 instruction set (it is mostly unchanged from
the arm backend). Offsets for helpers in gen_invoke.cc still need to
be changed to work on 64-bit.
Change-Id: I388f99eeb832857981c7d9d5cb5b71af64a4b921
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/create.sh
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
uick/codegen_util.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| 9ed427724a18dc24f9eb2ddf39e4729bea203c2e |
07-May-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86: EmitArrayImm shouldn't truncate to 16 bits
The code in X86Mir2Lir::EmitArrayImm() always truncates the immediate
value to 16 bits. This can't be right. The code in EmitImm() will check
the expected immediate size from the entry.
Change-Id: I75b3b96e41777838b0f243d65f3f2ded2e1dbdd2
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
|
| 410d87ff51e9432768924d2f294592818f93c244 |
07-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Cleanup ARM load/store wide and remove unused param s_reg."
|
| 052a647973b590c9d5007a2e16f313f4e32a70bd |
07-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: Add fake arm64 backend, and disable it by method filter."
|
| 221b86d96f6e1971d24e3d6a283352c58cedbd32 |
07-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: BitVector and Optimization changes"
|
| 3bf7c60a86d49bf8c05c5d2ac5ca8e9f80bd9824 |
07-May-2014 |
Vladimir Marko <vmarko@google.com> |
Cleanup ARM load/store wide and remove unused param s_reg.
Use a single LDRD/VLDR instruction for wide load/store on
ARM, adjust the base pointer if needed. Remove unused
parameter s_reg from LoadBaseDisp(), LoadBaseIndexedDisp()
and StoreBaseIndexedDisp() on all architectures.
Change-Id: I25a9a42d523a68addbc11abe44ddc55a4401df98
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/utility_x86.cc
|
| 9e06c8cd4a2e1471754470e09aaab63c0795b4af |
06-May-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Add fake arm64 backend, and disable it by method filter.
Just create an ArmCodeGenerator for arm64, but currently no code will
be generated for arm64.
The method filter can:
1. Skip methods with unsupported prototype.
2. Skip methods with unsupported dalvik byte code.
3. Skip methods with invocation to unsupported prototype.
These are temporary codes and should be removed later. But with this
patch, it won't break anything when we merge partly implemented arm64
backend later.
Change-Id: Ib9180d7b8a978f0a5ebaf6b4893e7e3724897113
rontend.cc
|
| 99380ed2f0f108a3110a3243e57e9863e74095cb |
07-May-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Ensure X86 OpRegCopyWide preserves src
X86Mir2Lir::OpRegCopyWide will clobber r_src if it is assigning a value
in an XMM register to a pair of GPRs. This change introduces a
temporary to preserve the input value.
Change-Id: I02af5174007c9572e597f8efb0da34f21882a3a8
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/int_x86.cc
|
| 290fda3acf3d9ce60f7ac3903fabfb01d3521d0f |
07-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Remove LoadBaseDispWide and StoreBaseDispWide."
|
| 91152bc2ab6e60add80dd017e30e57dce40a8ae0 |
07-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: ChildBlockIterator Implementation"
|
| 455759b5702b9435b91d1b4dada22c4cce7cae3c |
06-May-2014 |
Vladimir Marko <vmarko@google.com> |
Remove LoadBaseDispWide and StoreBaseDispWide.
Just pass k64 or kDouble to non-wide versions.
Change-Id: I000619c3b78d3a71db42edc747c8a0ba1ee229be
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/arm64/codegen_arm64.h
uick/arm64/int_arm64.cc
uick/arm64/utility_arm64.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/utility_x86.cc
|
| 7189fee4268c70d7ed0151e988ff7c7cd85f2a30 |
07-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "AArch64: Added arm64 quick backend as an arm clone."
|
| 43ec8737d8356dbff0a90bee521fb0e73438da47 |
31-Mar-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Added arm64 quick backend as an arm clone.
Created a new directory arm64 under compiler/dex/quick which contains
a copy of the 32-bit arm backend. In following CLs, this code will
be replaced/modified to support Aarch64.
Change-Id: I06c468db8d588e339eecf4d7d85276d5e334a17a
uick/arm64/arm64_lir.h
uick/arm64/assemble_arm64.cc
uick/arm64/call_arm64.cc
uick/arm64/codegen_arm64.h
uick/arm64/create.sh
uick/arm64/fp_arm64.cc
uick/arm64/int_arm64.cc
uick/arm64/target_arm64.cc
uick/arm64/utility_arm64.cc
|
| 72d32629303f8f39362a4099481f48646aed042f |
07-May-2014 |
Ian Rogers <irogers@google.com> |
Give Compiler a back reference to the driver.
The compiler driver is a single object delegating work to the compiler, rather
than passing it through to every Compiler call make it a member of Compiler so
that it maybe queried. This simplifies the Compiler API and makes the
relationship to CompilerDriver more explicit.
Remove reference arguments that contravene code style.
Change-Id: Iba47f2e3cbda679a7ec7588f26188d77643aa2c6
rontend.cc
uick/codegen_util.cc
|
| 47ebd77a6d249403a34d242908749b7446da2a82 |
07-May-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Improve fused compare long branch"
|
| 80475df914f9dbdbb1f4b42e87e75d375d50a629 |
06-May-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: Ensure use counts updated when adding SSA reg"
|
| 1f1d2513a11eaaa59601d7599ac2e80ddfa1bcf5 |
06-May-2014 |
Andreas Gampe <agampe@google.com> |
Merge "ART: Use utils.h::RoundUp instead of explicit bit-fiddling"
|
| b5c9b4008760c9042061490f22aaff990ed04c9a |
30-Apr-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: BitVector and Optimization changes
- The BitVector has a function SameBitsSet that is a bit upside down
- This patch fixes it.
- Two optimizations are fixed also:
- The null check pass uses now same bits set instead of equal due to a
subsequent change that will make it not always the case that the
compared bitvectors be of the same size.
- The fused optimization supposes a predecessor will have an instruction.
Change-Id: I9ef1c793964b18dc0f47baf9d1f361448bb053a3
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
ir_optimization.cc
|
| 99b0578036179849aa9fb7b8ef378bd20fabc71e |
06-May-2014 |
Dave Allison <dallison@google.com> |
Merge "Handle implicit stack overflow without affecting stack walks"
|
| f8c762b8cbd4a223c697d7e7bdb976fb39224cb8 |
02-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: ChildBlockIterator Implementation
- Added the API to be able to walk through a BasicBlock's children directly.
- When calling Reset(GrowableArray*), there is an assignment to the g_list_
member. This is not possible with the g_list_ being const.
Change-Id: I25d06484fd93848d80ccf96a1324058370b2ee46
Signed-Off-By: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
ir_graph.cc
ir_graph.h
|
| 36b65964d128471d917c2efc69c81bc50ef9360b |
06-May-2014 |
Ian Rogers <irogers@google.com> |
Merge "ART: Update and correct assemble_x86.cc"
|
| 2637f2e9bf4fc5591994b7c0158afead88321a7c |
30-Apr-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Update and correct assemble_x86.cc
Correct the definition of some X86 instructions in the file.
Add some new instructions and the code to emit them properly.
Added EmitMemCond()
Change-Id: Icf4b70236cf0ca857c85dcb3edb218f26be458eb
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/x86_lir.h
|
| 752e205de95ca9d4f4e825173a3cefd831a3b933 |
01-May-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Improve fused compare long branch
The code generated by a fused compare long with an immediate value is
much longer than comparing to a runtime value. Rewrite the code to
improve it.
The special cases are == or != to 0, and whether the source is a
temporary value or not. Try to handle all of these well. For all
except == and !=, we can use a 'cmp' instruction for the upper word, in
order to set the carry flag properly, rather than a 'sub' into a temp.
Also, we have to handle the <= and > cases properly, in order to get the
correct code generated, in the same manner as
X86Mir2Lir::GenFusedLongCmpBranch().
Change-Id: Ic29bf89ff2c06916d7fc996926997888ea013ba7
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/int_x86.cc
|
| 0095e0b8380a8802f40a21928800b9df6e11f1d7 |
06-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Add a last item in the MIROptimizationFlagPositions enumeration"
|
| 0add77a86599260aba3ea4b56e9db3da6bb881a8 |
06-May-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
ART: Ensure use counts updated when adding SSA reg
Ensure that matching data structures are updated when adding SSA
registers late in the compile.
Change-Id: I8e664dddf52c1a9095ba5b7a8df84e5a733bbc43
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
ir_dataflow.cc
ir_optimization.cc
|
| 660188264dee3c8f3510e2e24c11816c6b60f197 |
06-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Use utils.h::RoundUp instead of explicit bit-fiddling
Change-Id: I249a2cfeb044d3699d02e13d42b8e72518571640
uick/arm/assemble_arm.cc
uick/codegen_util.cc
uick/mips/assemble_mips.cc
uick/x86/assemble_x86.cc
|
| f29a4244bbc278843237f0ae242de077e093b580 |
05-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Fix frame size calculation for 64-bit
Calculate frame size in the same way as calculated in patch
"64bit changes to the stack walker for the Quick ABI"
Change-Id: I8c2458f5973536a84f3fd6ad56167b5cfafa9ab4
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/codegen_util.cc
|
| 0b8027003514c4fa6a850e5087076e991daaf4c3 |
05-May-2014 |
Andreas Gampe <agampe@google.com> |
Merge "x86_64: Fix Array::DataOffset in calls"
|
| 37498b6719347190f45472ad44ea21de563585eb |
05-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Fix Array::DataOffset in calls
Calculates offset using utility function
Change-Id: I19339537f4458dcae931897f4ee282f5c40746d2
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/gen_invoke.cc
|
| 5cd33753b96d92c03e3cb10cb802e68fb6ef2f21 |
16-Apr-2014 |
Dave Allison <dallison@google.com> |
Handle implicit stack overflow without affecting stack walks
This changes the way in which implicit stack overflows are handled
to satisfy concerns about changes to the stack walk code.
Instead of creating a gap in the stack and checking for it in
the stack walker, use the ManagedStack infrastructure to concoct
an invisible gap that will never be seen by a stack walk.
Also, this uses madvise to tell the kernel that the main stack's
protected region will probably never be accessed, and instead
of using memset to map the pages in, use memcpy to read from
them. This will save 32K on the main stack.
Also adds a 'signals' verbosity level as per a review request.
Bug: 14066862
Change-Id: I5257305feeaea241d11e6aa6f021d2a81da20b81
uick/arm/call_arm.cc
|
| 091cc408e9dc87e60fb64c61e186bea568fc3d3a |
31-Mar-2014 |
buzbee <buzbee@google.com> |
Quick compiler: allocate doubles as doubles
Significant refactoring of register handling to unify usage across
all targets & 32/64 backends.
Reworked RegStorage encoding to allow expanded use of
x86 xmm registers; removed vector registers as a separate
register type. Reworked RegisterInfo to describe aliased
physical registers. Eliminated quite a bit of target-specific code
and generalized common code.
Use of RegStorage instead of int for registers now propagated down
to the NewLIRx() level. In future CLs, the NewLIRx() routines will
be replaced with versions that are explicit about what kind of
operand they expect (RegStorage, displacement, etc.). The goal
is to eventually use RegStorage all the way to the assembly phase.
TBD: MIPS needs verification.
TBD: Re-enable liveness tracking.
Change-Id: I388c006d5fa9b3ea72db4e37a19ce257f2a15964
ompiler_enums.h
rontend.cc
ir_graph.h
ir_optimization.cc
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/local_optimizations.cc
uick/mips/README.mips
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_storage.h
reg_analysis.cc
|
| 29a2648821ea4d0b5d3aecb9f835822fdfe6faa1 |
03-May-2014 |
Ian Rogers <irogers@google.com> |
Move DecodedInstruction into MIR.
Change-Id: I188dc7fef4f4033361c78daf2015b869242191c6
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
|
| cb73fb35e5f7c575ed491c0c8e2d2b1a0a22ea2e |
02-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Better SSA Allocation when recreating SSA
The SSA calculation is not allocation friendly. This makes the
SSARepresentation remember how much is allocated and not reallocate
if SSA should be recalculated.
Also added some allocation friendly code for the dominance code.
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Change-Id: I6418b402434bd850b45771c75b7631b7b84a8f66
ir_dataflow.cc
ir_graph.cc
ir_graph.h
sa_transformation.cc
|
| 89fde26f586883e04d295d6e30954cb5a0dc37bf |
30-Apr-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Add a last item in the MIROptimizationFlagPositions enumeration
- Added a last item in the enumeration in order to be able to notice
when an extended MIR opcode is beyond the last one known to libart, and hence
must be an opcode added by code from a plugin.
- Fixed the naming typo of the enumeration.
Change-Id: I0e021ba54b0e60531338f23ca0ab64755e15229b
Signed-Off-By: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ompiler_enums.h
|
| 1dbbbf6090274ebae6809fdb340c166bb34e09c2 |
02-May-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Add finalizer references from the entrypoints."
|
| f6ba35df8609abf0e290a7cda37c63b5ee76ec3c |
02-May-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Move oat_data_flow_attributes_ to private and put an API"
|
| cc794c3dc5b45601da23fb0d7bc16f9b4ef04065 |
02-May-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Move oat_data_flow_attributes_ to private and put an API
The oat_data_flow_attributes had no checking mechanism to ensure bound
correctness.
This fix handles this and also offers two functions to retrieve the
attributes: using the MIR and DecodedInstruction.
Change-Id: Ib4f1f749efb923a803d364a4eea83a174527a644
Signed-Off-By: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ir_optimization_test.cc
ortable/mir_to_gbc.cc
uick/mir_to_lir.cc
uick/x86/utility_x86.cc
reg_analysis.cc
|
| 8194963098247be6bca9cc4a54dbfa65c73e8ccc |
02-May-2014 |
Vladimir Marko <vmarko@google.com> |
Replace CountOneBits and __builtin_popcount with POPCOUNT.
Clean up utils.h, make some functions constexpr.
Change-Id: I2399100280cbce81c3c4f5765f0680c1ddcb5883
uick/codegen_util.cc
|
| 42fcd9838a87abaf7a2ef86853a5287f86dbe391 |
22-Apr-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "64bit changes to the stack walker for the Quick ABI.""
This reverts commit 8d5ead52a92675c258113d3dfa71bf8fceba5d9f.
Change-Id: I6b4774a9bd180de33551975e106322ba1192e6ab
uick/mir_to_lir.cc
uick/ralloc_util.cc
|
| 8668c3cbdcf9471bd97e0da68a240051f2973074 |
25-Apr-2014 |
Mathieu Chartier <mathieuc@google.com> |
Add finalizer references from the entrypoints.
We now have an invariant where we never allocate finalizable
objects with the Initialized or Resolved entrypoints. This speeds up
allocation by only doing the check in the slow path.
Before:
MemAllocTest: 3625, 3707, 3641
EvaluateAndApplyChanges: 3448, 3421, 3413
After:
MemAllocTest: 3164, 3109, 3135
EvaluateAndApplyChanges: 3272, 3299, 3353
Bug: 14078487
Change-Id: I2b0534af3e7c75ea5e5257cf3647744f7abfb74e
uick/gen_common.cc
|
| ff093b31d75658c3404f9b51ee45760f346f06d9 |
01-May-2014 |
Ian Rogers <irogers@google.com> |
Fix a few 64-bit compilation of 32-bit code issues.
Bug: 13423943
Change-Id: I939389413af0a68c0d95b23cd598b7c42afa4383
uick/codegen_util.cc
uick/gen_invoke.cc
|
| 3b004ba749beb0fa0f0601fb5cf1929cc46bc1f1 |
30-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Simplify GenConstString
Now it's the same code for all platforms.
Bug: 13506069
Change-Id: I42c08a9dc99a3079caad01602de84296c9357dd8
uick/gen_common.cc
|
| 6ffcfa04ebb2660e238742a6000f5ccebdd5df15 |
25-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Rewrite suspend test check with LIRSlowPath.
Change-Id: I2dc17d079655586bfc588349c7a04afc2c6879af
uick/arm/call_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/int_x86.cc
|
| becc37249b652ae9fecb6a23ced708cdacb7effd |
29-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "ART: Initialization of RegLocation and API for GrowableArray Iterator"
|
| 1ceea7eb080a309fc2811db604bceed9e638bc5e |
16-Apr-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: Initialization of RegLocation and API for GrowableArray Iterator
Two things:
- Added a default initialization for the RegLocation.
- Added a default constructor and Reset for the GrowableArray's Iterator class.
Change-Id: I74d9c584304c77add42e0d66e4037ac45b890142
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
reg_analysis.cc
|
| 7a11ab09f93f54b1c07c0bf38dd65ed322e86bc6 |
29-Apr-2014 |
buzbee <buzbee@google.com> |
Quick compiler: debugging assists
A few minor assists to ease A/B debugging in the Quick
compiler:
1. To save time, the assemblers for some targets only
update the object code offsets on instructions involved with
pc-relative fixups. We add code to fix up all offsets when
doing a verbose codegen listing.
2. Temp registers are normally allocated in a round-robin
fashion. When disabling liveness tracking, we now reset the
round-robin pool to 0 on each instruction boundary. This makes
it easier to spot real codegen differences.
3. Self-register copies were previously emitted, but
marked as nops. Minor change to avoid generating them in the
first place and reduce clutter.
Change-Id: I7954bba3b9f16ee690d663be510eac7034c93723
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/codegen_util.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/utility_x86.cc
|
| fd698e67953e40e804d7c9d1a3e8460e9d67382a |
28-Apr-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix DCHECKS
The recent change to introduce k32, k64 and kReference operand
sizes missed updating a few DCHECKS.
Change-Id: I66eb617b07766e781b38962dc862fc5b023c2fbd
uick/arm/utility_arm.cc
uick/mips/utility_mips.cc
|
| e8256e7773a230337c3d137cbf0365f737820405 |
25-Apr-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Skip BBs without SSA representation in the Constant Propagation phase"
|
| 9c3b089519792245ab9f658865f44b8639b8d696 |
24-Apr-2014 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: Extracts an utility function of the duplicated code""
This reverts commit b5a14d2a6c18c1ea3c019c53b10af2e8f5dea234.
Change-Id: Id09a4cc27ac22db940badf3a277848b38b173eae
uick/gen_common.cc
|
| b5a14d2a6c18c1ea3c019c53b10af2e8f5dea234 |
24-Apr-2014 |
Andreas Gampe <agampe@google.com> |
Revert "ART: Extracts an utility function of the duplicated code"
This reverts commit 973cc95da6fb617bab133bd7a693c1cb7eafd393.
Change-Id: I3883c74ba06116e89d89d9cf085f20cff5d15f77
uick/gen_common.cc
|
| 973cc95da6fb617bab133bd7a693c1cb7eafd393 |
18-Apr-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
ART: Extracts an utility function of the duplicated code
This patch introduces an utility function 'DataOffsetOfType' in
'mirror::Array' class that calculates the data offset at given index
in an array of given type.
Change-Id: Idb19558653c70a129245f220f0fbb553f898865b
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
uick/gen_common.cc
|
| 125011d70aa84b3fd9052f1c90101401b0851928 |
24-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Merge "Delete throw launchpads."
|
| 0ea4bf7edb20be30f63566bce2d9db23f0b1c87f |
22-Apr-2014 |
buzbee <buzbee@google.com> |
Merge "Update load/store utilities for 64-bit backends"
|
| 695d13a82d6dd801aaa57a22a9d4b3f6db0d0fdb |
19-Apr-2014 |
buzbee <buzbee@google.com> |
Update load/store utilities for 64-bit backends
This CL replaces the typical use of LoadWord/StoreWord
utilities (which, in practice, were 32-bit load/store) in
favor of a new set that make the size explicit. We now have:
LoadWordDisp/StoreWordDisp:
32 or 64 depending on target. Load or store the natural
word size. Expect this to be used infrequently - generally
when we know we're dealing with a native pointer or flushed
register not holding a Dalvik value (Dalvik values will flush
to home location sizes based on Dalvik, rather than the target).
Load32Disp/Store32Disp:
Load or store 32 bits, regardless of target.
Load64Disp/Store64Disp:
Load or store 64 bits, regardless of target.
LoadRefDisp:
Load a 32-bit compressed reference, and expand it to the
natural word size in the target register.
StoreRefDisp:
Compress a reference held in a register of the natural word
size and store it as a 32-bit compressed reference.
Change-Id: I50fcbc8684476abd9527777ee7c152c61ba41c6f
ompiler_enums.h
uick/arm/call_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/call_mips.cc
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 6123d94cddf34f3fdb8ece55476e414e34662394 |
22-Apr-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "GenArithOpInt should ensure that reg is in core"
|
| 3a74d15ccc9a902874473ac9632e568b19b91b1c |
22-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Delete throw launchpads.
Bug: 13170824
Change-Id: I9d5834f5a66f5eb00f2ac80774e8c27dea99949e
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 4e0d5ee57ab5f76a761cf0d7ebb50b782e3eacdc |
22-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Merge "Revert "Revert "Use LIRSlowPath for throwing ArrayOutOfBoundsException."""
|
| 9d894662426e413454935e483d56a8cc33924174 |
21-Apr-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
Skip BBs without SSA representation in the Constant Propagation phase
In some cases the constant propagation optimization may get the MIR graph
where some of the BBs have no predecessors and do not transformed to the
SSA form. If such BB has operations on constants this may lead to segfault.
This patch adds the condition that will pass the only BBs with SSA.
Change-Id: I816d46b2492c5bd4748f983c3725b4798f9ebd68
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
ir_optimization.cc
|
| 42d65c52bbf4a354605389a759190e793787f692 |
19-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Add an option to specify a list of methods for LIR dumping.
An example would be:
--runtime-arg -verbose-methods:Array.checkRange32,Array.checkRange64
or
"-verbose-methods:void Array.checkRange32,void Array.checkRange64"
Change-Id: I61c1eb3b2eb4b24126a9264261c27889d53cc6bd
rontend.cc
|
| 80365d9bb947edef0eae0bfe62b9f7a239416e6b |
18-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Revert "Revert "Use LIRSlowPath for throwing ArrayOutOfBoundsException.""
This adds back using LIRSlowPath for ArrayIndexOutOfBoundsException.
And fix the host test crash.
Change-Id: Idbb602f4bb2c5ce59233feb480a0ff1b216e4887
ompiler_enums.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 7fff544c38f0dec3a213236bb785c3ca13d21a0f |
18-Apr-2014 |
Brian Carlstrom <bdc@google.com> |
Revert "Use LIRSlowPath for throwing ArrayOutOfBoundsException."
This reverts commit 9d46314a309aff327f9913789b5f61200c162609.
ompiler_enums.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 366f8ae038c4f6a3852deed1cff322ba54689808 |
15-Apr-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
GenArithOpInt should ensure that reg is in core
GenArithOpInt in two-addr case of add-int where destination is in
register should ensure that it is a core reg.
Change-Id: I5b5ca126773a2bb45f9b23ad892102b034d694b4
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/int_x86.cc
|
| d15f4e2ef3b1b4c01a490a00b0f6dc744741ce01 |
18-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Fix a use of OpCondBranch that breaks the MIPS build.
Change-Id: I09e19cb00c1e3f4bc0b0293f58674c9160094f7f
uick/gen_common.cc
uick/mips/int_mips.cc
|
| 9d46314a309aff327f9913789b5f61200c162609 |
18-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Use LIRSlowPath for throwing ArrayOutOfBoundsException.
Get rid of launchpads for throwing ArrayOutOfBoundsException
and use LIRSlowPath instead.
Bug: 13170824
Change-Id: I0e27f7a261a6a7fb5c0645e6113a957e098f699e
ompiler_enums.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 425640d6fac3432a44e236a002e8401a7cd59c5c |
17-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Merge "Use LIRSlowPath for throwing NPE."
|
| 79f2c53f3cb8649c19aeded82f7b8dcc96015808 |
17-Apr-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "String.IndexOf method handles negative start index value in incorrect way"
|
| a1758d83e298c9ee31848bcae07c2a35f6efd618 |
16-Apr-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
String.IndexOf method handles negative start index value in incorrect way
The standard implementation of String.IndexOf converts the negative value of
the start index to 0 and searching will start from the beginning of the string.
But current implementation may start searching from the incorrect memory
offset, that can lead to sigsegv or return incorrect result.
This patch adds the handler for cases when fromIndex is negative.
Change-Id: I3ac86290712789559eaf5e46bef0006872395bfa
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/x86/target_x86.cc
|
| b4b06678125131367999135e634055509b77b9e8 |
16-Apr-2014 |
Yevgeny Rouban <yevgeny.y.rouban@intel.com> |
Fix volatile wide put/get to be atomic on x86 arch
Current implementation puts memory barriers for volatile fields.
Volatile semantics needs atomicity, which are not guaranteed by memory barriers.
The patch forces all wide volatile fields to be loaded/stored using
xmm registers.
Change-Id: Ie78e186d13ffa237e6e93747b71d26651fa02866
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
uick/gen_common.cc
|
| e643a179cf5585ba6bafdd4fa51730d9f50c06f6 |
08-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Use LIRSlowPath for throwing NPE.
Get rid of launchpads for throwing NPE and use LIRSlowPath instead.
Also clean up some code of using LIRSlowPath for checking div
by zero.
Bug: 13170824
Change-Id: I0c20a49c39feff3eb1f147755e557d9bc0ff15bb
ompiler_enums.h
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| af13ad9fd18b6f75fe82e7995224c55654594f93 |
11-Apr-2014 |
Andreas Gampe <agampe@google.com> |
Centralize instruction-set pointer-size, alignment, 64b-width code
in instruction_set.h/cc
This allows to clean up some places that currently make explicit
comparisons.
Change-Id: I0dcc924c52fa53306f706aceea93a2d4a655c5df
rontend.cc
|
| d6ed642458c8820e1beca72f3d7b5f0be4a4b64b |
10-Apr-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Use trampolines for calls to helpers"""
This reverts commit f9487c039efb4112616d438593a2ab02792e0304.
Change-Id: Id48a4aae4ecce73db468587967968a3f7618b700
ompiler_enums.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| f9487c039efb4112616d438593a2ab02792e0304 |
09-Apr-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Use trampolines for calls to helpers""
This reverts commit 081f73e888b3c246cf7635db37b7f1105cf1a2ff.
Change-Id: Ibd777f8ce73cf8ed6c4cb81d50bf6437ac28cb61
Conflicts:
compiler/dex/quick/mir_to_lir.h
ompiler_enums.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| 1512ea155cbe0a4b33776b0320c1ce38583ab09b |
08-Apr-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler: fix CmpLong pair handling"
|
| 4289456fa265b833434c2a8eee9e7a16da31c524 |
07-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Use LIRSlowPath for throwing div by zero exception.
Get rid of launchpads for throwing div by zero exception and
use LIRSlowPath instead. Add a CallRuntimeHelper that takes no
argument for the runtime function.
Bug: 13170824
Change-Id: I7e0563e736c6f92bd63e3fbdfe3a777ad333e338
ompiler_enums.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/int_x86.cc
|
| a1983d4dab10b0cc51e9d1b6bcafa9a723fabcd9 |
07-Apr-2014 |
buzbee <buzbee@google.com> |
Quick compiler: fix CmpLong pair handling
OpCmpLong wasn't properly extracting the low register of a
pair.
Change-Id: I6d6cc3de1f543f4316e561648f371f793502fddb
uick/arm/int_arm.cc
|
| 4d3dc8a04da8a80251b381cdb482190363171dc1 |
07-Apr-2014 |
Dave Allison <dallison@google.com> |
Merge "Revert "Use trampolines for calls to helpers""
|
| 081f73e888b3c246cf7635db37b7f1105cf1a2ff |
07-Apr-2014 |
Dave Allison <dallison@google.com> |
Revert "Use trampolines for calls to helpers"
This reverts commit 754ddad084ccb610d0cf486f6131bdc69bae5bc6.
Change-Id: Icd979adee1d8d781b40a5e75daf3719444cb72e8
ompiler_enums.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| 50ca506e9191c2eafcf9564528712020f9531dc4 |
07-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Inlining synthetic accessors."
|
| 12c0273fd394d72ae93424784b1450daea417472 |
07-Apr-2014 |
Dave Allison <dallison@google.com> |
Merge "Use trampolines for calls to helpers"
|
| c8f60a69a9f2420fc1ecafec612a667be8dcd547 |
02-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Inlining synthetic accessors.
Bug: 11549140
Change-Id: I0d6a38c51887f55563414c240ac42ee64bdb5426
uick/dex_file_method_inliner.cc
|
| e1fced1d1805caec04b6e97d2b01a4977c6785c6 |
04-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Inlining setters that return one of their arguments.
Useful for builder classes and synthetic setters. The latter
are not inlined yet since they are static methods, i.e. they
don't use "this" as the object for IPUT.
Change-Id: I3d34156c3629b837a0a95ccc34a8aae3f4a636d5
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/mir_to_lir.cc
|
| 73ed718e7b08d17fd2e4af9bceb5e74ac46db676 |
05-Apr-2014 |
Mathieu Chartier <mathieuc@google.com> |
Revert "Inlining setters that return one of their arguments."
Bug: 13817614
This reverts commit 8e40c3e662d852da87b6bcfe79355f96ab9e91c7.
Change-Id: Ia7ed2d933514781150b2e0b9855244e383c60187
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/mir_to_lir.cc
|
| 389e11db6ef350b806f7a3f0d7b7df23b0ab6e0c |
05-Apr-2014 |
Mathieu Chartier <mathieuc@google.com> |
Revert "Inlining synthetic accessors."
This reverts commit 505ebb0e7b42e7facc8354515b06333ee8b84b10.
uick/dex_file_method_inliner.cc
|
| 53bee42d0f8b454ff4fe5b7e42bdb070c786e3eb |
05-Apr-2014 |
Mathieu Chartier <mathieuc@google.com> |
Fix using kArm instead of kThumb2.
Change-Id: I0f3bf93b38d910bc57d017693675829b6a39bc18
rontend.cc
|
| 754ddad084ccb610d0cf486f6131bdc69bae5bc6 |
19-Feb-2014 |
Dave Allison <dallison@google.com> |
Use trampolines for calls to helpers
This is an ARM specific optimization to the compiler
that uses trampoline islands to make calls to runtime
helper functions. The intention is to reduce the size
of the generated code (by 2 bytes per call) without
affecting performance.
By default this is on when generating an OAT file. It is
off when compiling to memory.
To switch this off in dex2oat, use the command line option:
--no-helper-trampolines
Enhances disassembler to print the trampoline entry on the
BL instruction like this:
0xb6a850c0: f7ffff9e bl -196 (0xb6a85000) ; pTestSuspend
Bug: 12607709
Change-Id: I9202bdb7cf21252ad807bd48701f1f6ce8e3d0fe
ompiler_enums.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| 45157a41b6c0ac9f73aeeb1f064c2270a6a68a60 |
05-Apr-2014 |
Ian Rogers <irogers@google.com> |
Merge "ARM: enable optimisation for easy multiply, add modulus pattern."
|
| 09379fd9f20e25ee71687e2c60f6a84c9ede8cd6 |
04-Apr-2014 |
Dave Allison <dallison@google.com> |
Merge "Disable use of R4 as a promotable register"
|
| 505ebb0e7b42e7facc8354515b06333ee8b84b10 |
02-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Inlining synthetic accessors.
Bug: 11549140
Change-Id: Ie0034a6840b1beaa3df92f26bf9d315119c81e34
uick/dex_file_method_inliner.cc
|
| 8e40c3e662d852da87b6bcfe79355f96ab9e91c7 |
04-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Inlining setters that return one of their arguments.
Useful for builder classes and synthetic setters. The latter
are not inlined yet since they are static methods, i.e. they
don't use "this" as the object for IPUT.
Change-Id: I946cf570195be83ecec5fb32851bcaefad45f8a5
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/mir_to_lir.cc
|
| 764c798b57b7baa04885fcdf5eba5708a01b9edc |
04-Apr-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Fix LoadValueWide to not call MarkLive for high reg that is equal to low reg"
|
| b3e527b2a9ee28ecaba2045f4415b00c8b395039 |
04-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up special method inlining.
Mark inlined getter/setter INVOKEs as NOP to allow implicit
null checks (SIGSEGV-based) rather than the explicit checks
in GenInvoke().
Avoid inlining wide setter and returning wide argument if
the wide source is not in consecutive dalvik registers in
INVOKE. This is valid dalvik bytecode and we should treat it
correctly even if we're currently unaware of any tools that
would generate such INVOKEs.
Remove bogus MIR_INLINED checks from LVN.
Change-Id: I7e75a832fcf9bd0550e21b1c8b3813c6166197dd
ocal_value_numbering.cc
uick/dex_file_method_inliner.cc
|
| 7efad5d3a806a15166109837439f2e149031feef |
04-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Disassemble Thumb2 shifts and more VFP instructions."
|
| 8325296769a77ecf3ab647b5ab516f439f5b3206 |
04-Apr-2014 |
Dave Allison <dallison@google.com> |
Disable use of R4 as a promotable register
When we are using implicit suspend checks we can potentially
use r4 as a register into which variables can be promoted. However
the runtime doesn't save this and thus will corrupt it. Not good.
This disables the promotion of r4 until we can figure out how
to make the runtime save it properly.
Change-Id: Ib95ce93579e1c364de5ecc8e728f2cb7990da77a
uick/arm/target_arm.cc
|
| cbd18b7f4da7677ca48c48c23ed9a7de3a8b0354 |
04-Apr-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
Fix LoadValueWide to not call MarkLive for high reg that is equal to low reg
For x86 double FP registers, LoadValueWide should not call MarkLive for
high reg that is equal to low reg.
Change-Id: Ie6a59307c9ff93303bd489c15529432cfdeceaa4
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/gen_loadstore.cc
|
| c777e0de83cdffdb2e240d439c5595a4836553e8 |
03-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Disassemble Thumb2 shifts and more VFP instructions.
Disassemble Thumb2 instructions LSL, LSR, ASR, ROR and VFP
instructions VABS, VADD, VSUB, VMOV, VMUL, VNMUL, VDIV.
Clean up disassembly of VCMP, VCMPE, VNEG and VSQRT. These
could have been erroneously used for other insns (VSQRT for
VMOV was encountered) and one VSQRT branch was unreachable.
Remove duplicate VMOV opcodes from compiler.
Change-Id: I160a1e3e4b6eabb6a5101ce348ffd49c0573257d
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
|
| 3da67a558f1fd3d8a157d8044d521753f3f99ac8 |
03-Apr-2014 |
Dave Allison <dallison@google.com> |
Add OpEndIT() for marking the end of OpIT blocks
In ARM we need to prevent code motion to the inside of an
IT block. This was done using a GenBarrier() to mark the end, but
it wasn't obvious that this is what was happening. This CL adds
an explicit OpEndIT() that takes the LIR of the OpIT for future
checks.
Bug: 13751744
Change-Id: If41d2adea1f43f11ebb3b72906bd308252ce3d01
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| f9719f9abbea060e086fe1304d72be50cbc8808e |
02-Apr-2014 |
Zheng Xu <zheng.xu@arm.com> |
ARM: enable optimisation for easy multiply, add modulus pattern.
Fix the issue when src/dest registers overlap in easy multiply.
Change-Id: Ie8cc098c29c74fd06c1b67359ef94f2c6b88a71e
uick/arm/int_arm.cc
uick/gen_common.cc
|
| 5a4139fd33547d09c94d9650157e3a4e4c9eede4 |
03-Apr-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "art: Handle x86_64 architecture equal to x86"
|
| 99f391e48f79421a4d949152aec6bafe1a7b5b82 |
03-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Fix Unsafe.getLong()/putLong() for x86, add test.
Change-Id: Id6841ae50e1047543c04dcdae30254dd6ce82082
uick/gen_invoke.cc
|
| 6a58cb16d803c9a7b3a75ccac8be19dd9d4e520d |
02-Apr-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
art: Handle x86_64 architecture equal to x86
This patch forces FE/ME to treat x86_64 as x86 exactly.
The x86_64 logic will be revised later when assembly will be ready.
Change-Id: I4a92477a6eeaa9a11fd710d35c602d8d6f88cbb6
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
rontend.cc
ir_optimization.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/local_optimizations.cc
uick/mir_to_lir.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 8549cf9d83688f7decbbea2a8de761ce29e95f3c |
03-Apr-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Use temp register in Unsafe Get/Put intrisics for displaced offset."
|
| 7c95cefc168ba81b17a9ed2d987ac5bcf0b05781 |
03-Apr-2014 |
Mathieu Chartier <mathieuc@google.com> |
Use temp register in Unsafe Get/Put intrisics for displaced offset.
Previously, the object register would get clobberd by the adding the
offset for wide UnsafeGets and wide UnsafePuts. This resulted in heap
corruption in AtomicLongFieldUpdater.compareAndSet and possibly other
places.
Bug: 13744490
Change-Id: Ic368d930b855c5c57e22060b32b73d0745328ef2
uick/gen_invoke.cc
|
| 4a200f56b7075309316b04d550c9cc50f8314edd |
01-Apr-2014 |
Jeff Hao <jeffhao@google.com> |
Add support for -Xverify:none mode.
This mode skips all verification and compilation.
Public bug: https://code.google.com/p/android/issues/detail?id=67664
Change-Id: Idd00ab8e9e46d129c02988b063c41a507e07bf5b
rontend.cc
ir_analysis.cc
|
| f6b65c123dafad62004a93a43eb82de00ddc8214 |
02-Apr-2014 |
Dave Allison <dallison@google.com> |
Add r4 as promotable register if implicit suspend checks
If we are doing implicit suspend checks we should be able
to use r4 as a target for promotion.
Also bump OAT version
Change-Id: Ia27d14ece3b3259dbb74bcf89feaa9da2cda6db8
uick/arm/target_arm.cc
|
| 43a065ce1dda78e963868f9753a6e263721af927 |
02-Apr-2014 |
Dave Allison <dallison@google.com> |
Add GenBarrier() calls to terminate all IT blocks.
This is needed to prevent things like load hoisting from putting
instructions inside the IT block.
Bug: 13749123
Change-Id: I98a010453b163ac20a90f626144f798fc06e65a9
uick/arm/int_arm.cc
uick/gen_common.cc
|
| 80fdef4018cde9bee8cdb0159ba660db1c4c4bf7 |
01-Apr-2014 |
buzbee <buzbee@google.com> |
Quick compiler: add comment to Arm encoding
A question from an AOSP contributer demonstrated the need for
explanation of a seemingly odd encoding for vldrd/vldrs. In short,
we add a "def" bit for lr on those instructions to cover the cases
in which we have to materialize a new base pointer at assembly
time using lr as a temp register.
Change-Id: I22c5740218a90e0ff387c6aac2bd20cc98eece85
uick/arm/assemble_arm.cc
|
| d265a8ab12e1b783af42bf07a264edbb86826d2c |
01-Apr-2014 |
buzbee <buzbee@google.com> |
Merge "Quick compiler, MIPS resource cleanup"
|
| 7ea687d886be7b8c106b0e0190dab299d14adcad |
01-Apr-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Fix stack overflow slow path error."
|
| 88e0463fa7e8ea7b427b65a07cd7b28111575174 |
01-Apr-2014 |
Ian Rogers <irogers@google.com> |
Merge "Revert "Revert "Optimize easy multiply and easy div remainder."""
|
| dd7624d2b9e599d57762d12031b10b89defc9807 |
15-Mar-2014 |
Ian Rogers <irogers@google.com> |
Allow mixing of thread offsets between 32 and 64bit architectures.
Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.
Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| d0b86c7ec593a552f726a15e532bb48170fbf487 |
01-Apr-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Use ResetDef to prevent from removing necessary stores for x86 long-to-fp."
|
| f943914730db8ad2ff03d49a2cacd31885d08fd7 |
27-Mar-2014 |
Dave Allison <dallison@google.com> |
Implement implicit stack overflow checks
This also fixes some failing run tests due to missing
null pointer markers.
The implementation of the implicit stack overflow checks introduces
the ability to have a gap in the stack that is skipped during
stack walk backs. This gap is protected against read/write and
is used to trigger a SIGSEGV at function entry if the stack
will overflow.
Change-Id: I0c3e214c8b87dc250cf886472c6d327b5d58653e
uick/arm/call_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
|
| 05a48b1f8e62564abb7c2fe674e3234d5861647f |
01-Apr-2014 |
Mathieu Chartier <mathieuc@google.com> |
Fix stack overflow slow path error.
The frame size without spill was being passed into the slow path
instead of the spill size. This was incorrect since only the spills
will have been pushed at the point of the overflow check.
Also addressed an other comment.
Change-Id: Ic6e455122473a8f796b291d71f945bcf72788662
uick/arm/call_arm.cc
|
| 306f017dd883c0bf806d239d97e0bca3194afbd7 |
07-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Faster AssembleLIR for ARM.
This also reduces sizeof(LIR) by 4 bytes (32-bit builds).
Change-Id: I0cb81f9bf098dfc50050d5bc705c171af26464ce
ompiler_enums.h
uick/arm/assemble_arm.cc
uick/arm/codegen_arm.h
uick/mir_to_lir.h
|
| 6170f5576f46f64eec6cd6c125c3de001afa5bcf |
29-Mar-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
Use ResetDef to prevent from removing necessary stores for x86 long-to-fp.
X86 long-to-fp needs the source operand in the memory.
Later on, NullifyRange may remove the stores and then lead to incorrect
long-to-fp conversions.
To fix this bug, ResetDef is called after flushing source to the memory
for x86 long-to-fp.
Change-Id: I3510739294dc2e5ffb3d76d7651880fae63f2382
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/x86/fp_x86.cc
|
| e2143c0a4af68c08e811885eb2f3ea5bfdb21ab6 |
28-Mar-2014 |
Ian Rogers <irogers@google.com> |
Revert "Revert "Optimize easy multiply and easy div remainder.""
This reverts commit 3654a6f50a948ead89627f398aaf86a2c2db0088.
Remove the part of the change that confused !is_div with being multiply rather
than implying remainder.
Change-Id: I202610069c69351259a320e8852543cbed4c3b3e
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 9da5c1013215176f2a4dbe7a804be899e12d5f68 |
28-Mar-2014 |
buzbee <buzbee@google.com> |
Quick compiler, MIPS resource cleanup
MIPS architecture includes internal registers HI and LO.
Similar to condition codes in other architectures, these internal
resouces must be accounted for during instruction scheduling.
Previously, the Quick backend for MIPS dealt with them by defining
rHI and rLO pseudo registers - treating them as actual registers for
def/use masks. This CL changes the handling of these resources to
be in line with how condition codes are used elsewhere - leaving
register definitions to be used for registers.
Change-Id: Idcd77f3107b0c9b081ad05b1aab663fb9f41492d
ompiler_enums.h
uick/mips/assemble_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mir_to_lir.h
uick/x86/x86_lir.h
|
| 4aeec176eaf11fe03f342aadcbb79142230270ed |
28-Mar-2014 |
Mathieu Chartier <mathieuc@google.com> |
Refactor some GC code.
Reduced amount of code in mark sweep / semi space by moving
common logic to garbage_collector.cc. Cleaned up mod union tables
and deleted an unused implementation.
Change-Id: I4bcc6ba41afd96d230cfbaf4d6636f37c52e37ea
rontend.cc
|
| 217fe73a6c2f3ec44dc52c85c8a101313d048f04 |
27-Mar-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Annotate Dalvik VR access as both use and def if we use it in this way
Some 2addr operations use direct access to VR in memory as both def and use but
annotate its only as def. It results in later optimizations like reorder
of LIRs can re-order this operation with other mov.
Change-Id: I04ac40c9f229af6f1e5c5f91f4901b1452509582
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/int_x86.cc
uick/x86/utility_x86.cc
|
| 3654a6f50a948ead89627f398aaf86a2c2db0088 |
28-Mar-2014 |
Brian Carlstrom <bdc@google.com> |
Revert "Optimize easy multiply and easy div remainder."
This reverts commit 08df4b3da75366e5db37e696eaa7e855cba01deb.
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 3d325c6700509c37d85f21a94575d7605812e806 |
27-Mar-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
Fix CopyRegInfo to keep live/dirty flags of new registers.
CopyRegInfo should not change live/dirty flags of new registgers.
Otherwise, it will lead to incorrectly clobbering these live registers
that are not live actually, and then allocating them to another usage.
Change-Id: Ia9f055b33a11a6d70c0aca1a9fe8639ecfb09464
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
uick/ralloc_util.cc
|
| 262b299abf658c16f61dad2240cfaf3deafe4423 |
27-Mar-2014 |
buzbee <buzbee@google.com> |
Fix x86 master build failure.
Replace bogus DCHECKs with logic matching pre-cleanup code.
Register pairs are considered temp, promoted, dirty or live if
either register of the pair meets criteria.
Change-Id: If2df891fdd1e3351d4cbe72aaf2a2ac5b34b2110
uick/mir_to_lir.h
uick/ralloc_util.cc
|
| 08df4b3da75366e5db37e696eaa7e855cba01deb |
25-Mar-2014 |
Zheng Xu <zheng.xu@arm.com> |
Optimize easy multiply and easy div remainder.
Update OpRegRegShift and OpRegRegRegShift to use RegStorage parameters.
Add special cases for *0 and *1. Add more easy multiply special cases for
Arm.
Reuse easy multiply in SmallLiteralDivRem() to support remainder cases.
Change-Id: Icd76a993d3ac8d4988e9653c19eab4efca14fad0
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 2700f7e1edbcd2518f4978e4cd0e05a4149f91b6 |
07-Mar-2014 |
buzbee <buzbee@google.com> |
Continuing register cleanup
Ready for review.
Continue the process of using RegStorage rather than
ints to hold register value in the top layers of codegen.
Given the huge number of changes in this CL, I've attempted
to minimize the number of actual logic changes. With this
CL, the use of ints for registers has largely been eliminated
except in the lowest utility levels. "Wide" utility routines
have been updated to take a single RegStorage rather than
a pair of ints representing low and high registers.
Upcoming CLs will be smaller and more targeted. My expectations:
o Allocate float double registers as a single double rather than
a pair of float single registers.
o Refactor to push code which assumes long and double Dalvik
values are held in a pair of register to the target dependent
layer.
o Clean-up of the xxx_mir.h files to reduce the amount of #defines
for registers. May also do a register renumbering to bring all
of our targets' register naming more consistent. Possibly
introduce a target-independent float/non-float test at the
RegStorage level.
Change-Id: I646de7392bdec94595dd2c6f76e0f1c4331096ff
ir_graph.h
uick/arm/arm_lir.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/local_optimizations.cc
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_storage.h
|
| 99ad7230ccaace93bf323dea9790f35fe991a4a2 |
26-Feb-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Relaxed memory barriers for x86
X86 provides stronger memory guarantees and thus the memory barriers can be
optimized. This patch ensures that all memory barriers for x86 are treated
as scheduling barriers. And in cases where a barrier is needed (StoreLoad case),
an mfence is used.
Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ompiler_enums.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/local_optimizations.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| d3a2dfad0e1231b354e4bf77b67a4e179fa0e837 |
18-Mar-2014 |
Yevgeny Rouban <yevgeny.y.rouban@intel.com> |
Reuse promoted register temporarily
AtomicLong (x86) is implemented as an intrinsic, which uses
the cmpxchng8b instruction.
This instruction requires 4 physical registers plus 2 more used for
the memory operand. On x86 we have only 4 temporaries. The code tried
to solve this by using MarkTemp utility, but this was not meant to be
used with promoted registers. The problem is that MarkTemp does not
spill anything and as a result we can lose VR.
If the registers are promoted this patch just reuses the values pushed
on the stack.
Change-Id: Ifec9183e2483cf704d0d1166a1004a9aa07b4f1d
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
uick/x86/int_x86.cc
|
| ab5545f31aec6ed4b906bd1bb34a02778e7081e9 |
25-Mar-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
x86 GenLongRegOrMemOp should be aware about xmm to core reg conversion
GenLongRegOrMemOp function expects arithmetic on core regs but does not
ensure that operand in core reg.
The patch adds the conversion if it is required.
Change-Id: Ibb6928b8cc2c63ede1a20d6ee45d9a64884231b6
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/int_x86.cc
|
| 889d079baea1d9ee488b5915de9aec4e0d02e2a0 |
25-Mar-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "An argument is handled incorrectly for add-int/lit8 during optimization phase"
|
| 716426fe40f5de972084de0e5bd6395b2617ec12 |
25-Mar-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Small update to CFG printing using DOT"
|
| ee40aa4650d7d000335ccfcb2fbb742acfb1f1c3 |
24-Mar-2014 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
An argument is handled incorrectly for add-int/lit8 during optimization phase
Dalvik instruction 'add-int/lit8' stores a constant in the third parameter.
But during optimization phase the compiler reads the constant from the
second parameter. This is incorrect because it leads to wrong decision that
no array bound checks are needed in our test case. As a consequence it
fails with SIGSEGV because of accessing elements which are beyond the bounds.
Change-Id: I653892514934046d31a9e4d206d9d95ebb6267ab
Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com>
ocal_value_numbering.cc
|
| 5d47447e1d0cd18cf91a189f7a08e65c8d43ea5a |
21-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Move saved SSA map to ScopedArenaAllocator to save memory.
Bug: 13564922
Change-Id: I917d451267ca6fceb2f6b2ff33b872ee8c209893
sa_transformation.cc
|
| 53b6afc93d91f9a48660682082dafcd81a652d6c |
21-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Free Arenas from the ArenaStack before running codegen.
Since the ArenaStack is used only by the MIRGraph and not by
the memory hungry codegen, freeing the ArenaStack's Arenas
just before running the codegen should reduce the compiler's
peak memory usage.
Bug: 13564922
Change-Id: I1cb49d367e4e81d71a03cac89b3739ed61e4f966
rontend.cc
|
| b982331680a9fa329302c68bfdcc9a4d9d403921 |
20-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Fix and clean up intrinsic Math.abs(long).
On ARM, make sure we don't clobber a register that we still
need for the next insn. On x86, don't free a source register
for temps if it's overlapping a result register as that
would allow the sign_reg temporary to alias with the result.
Change-Id: I785f2f607900ae8ceb2fa0b8f3eefafdf6fab5c7
uick/gen_invoke.cc
|
| 25bc279080a56546b0f8a33342a853b2778eed0d |
19-Mar-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Small update to CFG printing using DOT
-Ensures to print all non-null basic blocks in MIR graph.
-Prints links from exceptions to catch targets.
Change-Id: I98fe46cd1c39cf59c46e6bccf967612defaa4f3b
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_graph.cc
|
| ec31d37f76b0d594ad1499b22b11bbeaad246c23 |
19-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up intrinsic Math.abs(float/double).
Don't load 0x7fffffff into register.
Change-Id: I0197f9f3ad33db1f6eb09a9b4113299c00f500e3
uick/gen_invoke.cc
|
| 63a4c96e71d6c3223842f4eebd69b269cc491897 |
20-Mar-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Fix GenArithOpInt to work with RA correctly"
|
| ac05eb59b8998b31684b32cc69d2de767d5482cc |
20-Mar-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART: API changes"
|
| 66da1364425df90e6a03b032ee0a401375e45c39 |
14-Mar-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Fix GenArithOpInt to work with RA correctly
In a case of mul-int/2addr bytecode when source operand is in
memory implementation should first load value of destination
and then evaluate location for destination. Otherwise load will
be skipped because after evaluation of physical register for
destination load will be ignored due to register allocator
thinks that value is already in register.
Change-Id: Iecee5a07d0fba16b421b8c49d42c5d8623794ad7
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
uick/x86/int_x86.cc
|
| b95a5345ae4217b70ca36f0cced92f68dda7caf5 |
12-Mar-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
AArch64: Add arm64 runtime support.
Adds support for arm64 to ART. Assembler stubs are sufficient for
down calls into interpreter. JNI compiler and generics are not finished.
Basic Generic JNI functionality.
Change-Id: I4a07c79d1e037b9f5746673480e32cf456867b82
rontend.cc
|
| 66e4c3e96dccdec7423d673ad6bbf7821a776651 |
19-Mar-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Optimize stack overflow handling."
|
| 40bbb39b85c063cd6a9f4ab00ff70372370e08cf |
19-Mar-2014 |
buzbee <buzbee@google.com> |
Fix Quick compiler "out of registers"
There are a few places in the Arm backend that expect to be
able to survive on a single temp register - in particular
entry code generation and argument passing. However, in the
case of a very large frame and floating point ld/st, the
existing code could end up using 2 temps.
In short, if there is a displacement overflow we try to use
indexed load/store instructions (slightly more efficient).
However, there are none for floating point - so we ended up
burning yet another register to construct a direct pointer.
This CL detects this case and doesn't try to use the indexed
load/store mechanism for floats.
Fix for https://code.google.com/p/android/issues/detail?id=67349
Change-Id: I1ea596ea660e4add89fd4fddb8cbf99a54fbd343
uick/arm/utility_arm.cc
|
| 0d507d1e0441e6bd6f3affca3a60774ea920f317 |
19-Mar-2014 |
Mathieu Chartier <mathieuc@google.com> |
Optimize stack overflow handling.
We now subtract the frame size from the stack pointer for methods
which have a frame smaller than a certain size. Also changed code to
use slow paths instead of launchpads.
Delete kStackOverflow launchpad since it is no longer needed.
ARM optimizations:
One less move per stack overflow check (without fault handler for
stack overflows). Use ldr pc instead of ldr r12, b r12.
Code size (boot.oat):
Before: 58405348
After: 57803236
TODO: X86 doesn't have the case for large frames. This could case an
incoming signal to go past the end of the stack (unlikely however).
Change-Id: Ie3a5635cd6fb09de27960e1f8cee45bfae38fb33
ompiler_enums.h
uick/arm/call_arm.cc
uick/gen_common.cc
uick/mips/call_mips.cc
uick/x86/call_x86.cc
|
| 0d9c02e661813abdf18b4e7544e204d2da719d20 |
19-Mar-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Run Java tests with the optimizing compiler."
|
| 92cf83e001357329cbf41fa15a6e053fab6f4933 |
18-Mar-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Run Java tests with the optimizing compiler.
Also fix a vector.reserve -> vector.resize braino, and build
a GC map that dex2oat expects.
Change-Id: I6acf2f90a4c32f90b79bf7709bf2e43931b98757
uick/codegen_util.cc
|
| cdacac4a8196bdc620185079ec9e886329606f3d |
13-Mar-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
ART: API changes
- Moved AppendMIR to BasicBlock
- Moved PrependMIR to BasicBlock
- Moved InsertMIRAfter to BasicBlock
- Moved GetNextUnconditionalMir to BasicBlock
Change-Id: Id261434e9f7d5d93f1bce0c87c9276a20077c483
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ir_graph.cc
ir_graph.h
ir_optimization_test.cc
uick/dex_file_method_inliner.cc
uick/mir_to_lir.cc
sa_transformation.cc
|
| 60d7a65f7fb60f502160a2e479e86014c7787553 |
14-Mar-2014 |
Brian Carlstrom <bdc@google.com> |
Fix stack overflow for mutual recursion.
There was an error where we would have a pc that was in the method
which generated the stack overflow. This didn't work however
because the stack overflow check was before we stored the method in
the stack. The result was that the stack overflow handler had a PC
which wasnt necessarily in the method at the top of the stack. This
is now fixed by always restoring the link register before branching
to the throw entrypoint.
Slight code size regression on ARM/Mips (unmeasured). Regression on ARM
is 4 bytes of code per stack overflow check. Some of this regression is
mitigated by having one less GC safepoint.
Also adds test case for StackOverflowError issue (from bdc).
Tests passing: ARM, X86, Mips
Phone booting: ARM
Bug: https://code.google.com/p/android/issues/detail?id=66411
Bug: 12967914
Change-Id: I96fe667799458b58d1f86671e051968f7be78d5d
(cherry-picked from c0f96d03a1855fda7d94332331b94860404874dd)
uick/arm/utility_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/mips_lir.h
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 9820b7c1dc70e75ad405b9e6e63578fa9fe94e94 |
02-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Early inlining of simple methods.
Inlining "special" methods: empty methods, methods returning
constants or their arguments, simple getters and setters.
Bug: 8164439
Change-Id: I8c7fa9c14351fbb2470000b378a22974daaef236
b_optimizations.h
rontend.cc
rontend.h
ocal_value_numbering.cc
ir_dataflow.cc
ir_graph.h
ir_method_info.cc
ir_method_info.h
ir_optimization.cc
ass_driver.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.cc
|
| bfea9c29e809e04bde4a46591fea64c5a7b922fb |
17-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Class initialization check elimination.
Also, move null check elimination temporaries to the
ScopedArenaAllocator and reuse the same variables in the
class initialization check elimination.
Change-Id: Ic746f95427065506fa6016d4931e4cb8b34937af
b_optimizations.cc
b_optimizations.h
ompiler_enums.h
rontend.cc
rontend.h
ir_field_info.h
ir_graph.cc
ir_graph.h
ir_method_info.h
ir_optimization.cc
ir_optimization_test.cc
ass_driver.cc
uick/gen_common.cc
sa_transformation.cc
|
| 1d45438a031916f2d373c8759c19a6f14fe50255 |
15-Mar-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Remove duplicated register load in function call to quick entry."
|
| d7f8e02041e9d16160bc81bd1fa19189bffc04b3 |
13-Mar-2014 |
Zheng Xu <zheng.xu@arm.com> |
ARM: Do not allocate temp registers in MulLong if possible.
Just use rl_result if we have enough registers and it is *not* either operand.
Change-Id: I5a6f3ec09653b97e41bbc6dce823aa8534f98a13
uick/arm/int_arm.cc
|
| 9a84ad99aab002e8cfeec9381df971a00e28d05f |
13-Mar-2014 |
Zheng Xu <zheng.xu@arm.com> |
Remove duplicated register load in function call to quick entry.
CallRuntimeHelperRegLocation() will load parameter to registers for native call, but
GenConversionCall() duplicates the work before it call CallRuntimeHelperRegLocation().
Instructions generated before patch:
0xf731007e: f8d9e25c ldr.w lr, [r9, #604] ; pF2l
0xf7310082: ee180a10 vmov.f32 r0, s16
0xf7310086: ee180a10 vmov.f32 r0, s16
0xf731008a: 47f0 blx lr
After:
0xf739707e: f8d9e25c ldr.w lr, [r9, #604] ; pF2l
0xf7397082: ee180a10 vmov.f32 r0, s16
0xf7397086: 47f0 blx lr
Change-Id: I1868aefa4703a0f8133eaac707f5b80f01293cb8
uick/gen_common.cc
uick/gen_invoke.cc
|
| e90501da0222717d75c126ebf89569db3976927e |
12-Mar-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Add dependency for operations with x86 FPU stack
Load Hoisting optimization can re-order operations with
FPU stack due to no dependency set.
Patch adds resource dependency between these operations.
Change-Id: Iccce98c8f3c565903667c03803884d9de1281ea8
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
ompiler_enums.h
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| b373e091eac39b1a79c11f2dcbd610af01e9e8a9 |
21-Feb-2014 |
Dave Allison <dallison@google.com> |
Implicit null/suspend checks (oat version bump)
This adds the ability to use SEGV signals
to throw NullPointerException exceptions from Java code rather
than having the compiler generate explicit comparisons and
branches. It does this by using sigaction to trap SIGSEGV and when triggered
makes sure it's in compiled code and if so, sets the return
address to the entry point to throw the exception.
It also uses this signal mechanism to determine whether to check
for thread suspension. Instead of the compiler generating calls
to a function to check for threads being suspended, the compiler
will now load indirect via an address in the TLS area. To trigger
a suspend, the contents of this address are changed from something
valid to 0. A SIGSEGV will occur and the handler will check
for a valid instruction pattern before invoking the thread
suspension check code.
If a user program taps SIGSEGV it will prevent our signal handler
working. This will cause a failure in the runtime.
There are two signal handlers at present. You can control them
individually using the flags -implicit-checks: on the runtime
command line. This takes a string parameter, a comma
separated set of strings. Each can be one of:
none switch off
null null pointer checks
suspend suspend checks
all all checks
So to switch only suspend checks on, pass:
-implicit-checks:suspend
There is also -explicit-checks to provide the reverse once
we change the default.
For dalvikvm, pass --runtime-arg -implicit-checks:foo,bar
The default is -implicit-checks:none
There is also a property 'dalvik.vm.implicit_checks' whose value is the same
string as the command option. The default is 'none'. For example to switch on
null checks using the option:
setprop dalvik.vm.implicit_checks null
It only works for ARM right now.
Bumps OAT version number due to change to Thread offsets.
Bug: 13121132
Change-Id: If743849138162f3c7c44a523247e413785677370
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 9545a446e99b22248099fe66f5f9431530c20851 |
13-Mar-2014 |
Jeff Hao <jeffhao@google.com> |
Merge "Allow patching between dex files in the boot classpath."
|
| 3bc8615332b7848dec8c2297a40f7e4d176c0efb |
13-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Use LIRSlowPath for intrinsics, improve String.indexOf().
Rewrite intrinsic launchpads to use the LIRSlowPath.
Improve String.indexOf for constant chars by avoiding
the check for code points over 0xFFFF.
Change-Id: I7fd5583214c5b4ab9c38ee36c5d6f003dd6345a8
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/target_x86.cc
|
| 9e6a1113381ef7958e36237dfe22752e88272b2b |
13-Mar-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "ART's intrinsic for String.indexOf use the incorrect register"
|
| 0cecf494999cc35e13ff2104145c1d9229bf8776 |
13-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Add dex2oat --print-pass-names and --disable-passes= options."
|
| b9d50a9829b795932eac4cc50a99b4ce80b0ecb4 |
13-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Move inline method detection to runtime."
|
| b34f69ab43aaf7a6e6045c95f398baf566ef5023 |
07-Mar-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add command line support for enabling the optimizing compiler.
Also run tests with the optimizing compiler enabled when
the file art/USE_OPTIMIZING_COMPILER is present.
Change-Id: Ibc33eed62a43547bc3b9fe786d014c0d81b5add8
ompiler_ir.h
rontend.cc
ir_optimization.cc
|
| 34fa0d935bed7a0e17bc6df4bd079e3428a179e7 |
12-Mar-2014 |
Yevgeny Rouban <yevgeny.y.rouban@intel.com> |
ART's intrinsic for String.indexOf use the incorrect register
ART's intrinsic for String.indexOf of x86 platform use the incorrect register
to compare start with the string length. It should be fixed.
Change-Id: I22986b4d4b23f62b4bb97baab9fe43152d12145e
Signed-off-by: Vladimir Ivanov <vladimir.a.ivanov@intel.com>
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
uick/x86/target_x86.cc
|
| 49161cef10a308aedada18e9aa742498d6e6c8c7 |
12-Mar-2014 |
Jeff Hao <jeffhao@google.com> |
Allow patching between dex files in the boot classpath.
Change-Id: I53f219a5382d0fcd580e96e50025fdad4fc399df
uick/codegen_util.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| e3e0260c23d8999b9433715ac7ee5296ee2fd633 |
12-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Move inline method detection to runtime.
The debugger needs this for selective deoptimization.
Change-Id: I8100000449b56e619288fb05d41ea6f02b53b334
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/mir_to_lir.cc
|
| cd8ce66a83af05d5ecb59aa6a8aad89a29e0a844 |
11-Mar-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
Add dex2oat --print-pass-names and --disable-passes= options.
Add --print-pass-names to print a list of pass names.
Add --disable-passes= to disable one ore more passes
separated by comma.
Ex: Using --disable-passes=UseCount,BBOptimizations can disable UseCount
and BBOptimizations passes.
Change-Id: I0dffaf10547afdcca78a20d8e0e6b358bfb2ee8c
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
ass_driver.cc
ass_driver.h
|
| 2f4c3a4e1b84963e9f4465fc476d1ec804321601 |
12-Mar-2014 |
buzbee <buzbee@google.com> |
Remove spurious duplicate line of code
This CL removes a duplicate line of code which appears to have
been intended for removal during a cleanup, but wasn't. It would
not have affected correctness, rather it uselessly performed the
same store twice.
Bug originally reported by M Mendell.
Change-Id: If4333a29f32b6bdb944b67aa560d856611041ff6
uick/gen_invoke.cc
|
| 3d73ba2ce682edfaf41f29521bd6039c6499a1c5 |
06-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Avoid Cache*LoweringInfo pass when there's no GET/PUT/INVOKE.
Add new data flow flags indicating instance/static field
access. Record merged flags of all insns and use them to skip
the CacheFieldLoweringInfo pass if the method uses no fields
and the CacheMethodLoweringInfo pass if it has no invokes.
Change-Id: I36a36b438ca9b0f104a7baddc0497d736495cc3c
b_optimizations.h
ir_dataflow.cc
ir_graph.cc
ir_graph.h
|
| 0f6784737882199197796b67b99e5f1ded383bee |
11-Mar-2014 |
Ian Rogers <irogers@google.com> |
Unify 64bit int constant definitions.
LL and ULL prefixes are word size dependent, use the INT64_C and UINT64_C
macros instead.
Change-Id: I5b70027651898814fc0b3e9e22a18a1047e76cb9
ir_graph.h
uick/arm/fp_arm.cc
uick/arm/utility_arm.cc
|
| 73a471336a9515fa7fdc5859e3c481ec451237a5 |
10-Mar-2014 |
Ian Rogers <irogers@google.com> |
Merge "Fix LIR generation for long arithmetic operation"
|
| 3c050399e482f6eaf0617fa82ee47adbc01b82cd |
10-Mar-2014 |
Ian Rogers <irogers@google.com> |
Merge "LongToFp result storage fixed"
|
| 3dfc5c168506b89e345c977355a4eabebfede72a |
10-Mar-2014 |
Ian Rogers <irogers@google.com> |
Merge "ARM: Inline codegen for long-to-float on ARM."
|
| e19649a91702234f9aa9941d76da447a1e0dcc2a |
27-Feb-2014 |
Zheng Xu <zheng.xu@arm.com> |
ARM: Remove duplicated instructions; add vcvt, vmla, vmls disassembler.
Remove kThumb2VcvtID in the assembler which was duplicated.
Add vcvt, vmla, vmls in the disassembler.
Change-Id: I14cc39375c922c9917274d8dcfcb515e888fdf26
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/fp_arm.cc
|
| f0e6c9c7b395f4fce4d00d31cabd362302e1d924 |
10-Mar-2014 |
Zheng Xu <zheng.xu@arm.com> |
ARM: Inline codegen for long-to-float on ARM.
long-to-double-to-float using vfp instructions should be faster than the
function provided by toolchain.
Change-Id: I7ff809bca6665f0c1a0d7e6db98d570ce86b7c66
uick/arm/fp_arm.cc
|
| f096aad9203d7c50b2f9cbe1c1215a50c265a059 |
23-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Cache method lowering info in mir graph.
This should enable easy inlining checks. It should also
improve compilation time of methods that call the same
methods over and over - it is exactly such methods that
tend to exceed our 100ms time limit.
Change-Id: If01cd18e039071a74a1444570283c153429c9cd4
b_optimizations.h
ir_analysis.cc
ir_graph.cc
ir_graph.h
ir_method_info.cc
ir_method_info.h
ass_driver.cc
uick/gen_invoke.cc
|
| a03de6dbabbe857deae5b0f1e388fbd3a2420dc2 |
09-Mar-2014 |
Ian Rogers <irogers@google.com> |
Revert "Revert "Make clang the default compiler on host.""
This reverts commit d54f3a6219bca6ae018f4395fa0f1254bd4459be.
Change-Id: Id96bb52a0d599f8848010d1589bdf0f70fc7124b
rontend.cc
erification_results.cc
erification_results.h
|
| d54f3a6219bca6ae018f4395fa0f1254bd4459be |
08-Mar-2014 |
Ian Rogers <irogers@google.com> |
Revert "Make clang the default compiler on host."
This reverts commit 87f8b4cf0c1d6aab3eb5d1e99cc4e7cf175ef772.
Change-Id: I91a513042f0f9cf66288a296ad4a3b5da7830c7b
rontend.cc
erification_results.cc
erification_results.h
|
| 87f8b4cf0c1d6aab3eb5d1e99cc4e7cf175ef772 |
07-Mar-2014 |
Ian Rogers <irogers@google.com> |
Make clang the default compiler on host.
Motivation, GCC's compiler warnings are inferior to clang's. -Wthread-safety is
not supported by GCC starting with version 4.7. As this change only effects the
host, performance issues are an impact on host building and testing alone.
Fix clang gtest building on host with BUILD_HOST_64bit.
Fix clang build regressions caused by unused fields.
Fix x86-64 regression caused by requirement to fire-up quick compiler even in an
interpret-only environment. Long-term this code doesn't belong in the quick
compiler.
Change-Id: Ifc2b10177f40d0724cbbf8dab9653ac03cdd1cee
rontend.cc
erification_results.cc
erification_results.h
|
| 39c3bfbd03d85c63cfbe69f17ce5800ccc7d6c13 |
29-Jan-2014 |
Dave Allison <dallison@google.com> |
Make use of profiling information for dex2oat
If the profile file exists, the compiler driver will read it
and store the data in an internal map. Then, when we want to work
out whether to compile a method or not, the map is consulted and if
the method shows up with a high enough percentage of use we compile it.
The profile file itself is created by installd and is writeable by the
app. The file is in /data/dalvik-cache/profiles and is named by
the package name.
This also modifies the profiler itself to:
1. Only count runnable threads (not suspended threads) in the profile
2. Use system properties to allow tuning of the profile parameters
3. Merge profiles from multiple processes using file locking.
Bug: 12877748
Change-Id: Iab2f3a327a2860db2a80d5724277d6c626227f2b
Conflicts:
compiler/dex/frontend.cc
compiler/dex/mir_analysis.cc
compiler/dex/verification_results.cc
compiler/driver/compiler_driver.cc
dex2oat/dex2oat.cc
runtime/class_linker.cc
runtime/runtime.cc
runtime/runtime.h
rontend.cc
ir_analysis.cc
ir_graph.h
erification_results.cc
|
| aa00fe010eb7b61c2de82611ce3f6fc0918a4f9e |
07-Mar-2014 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Add more VerifyObject calls."
|
| c645f1ddb7c40bea6a38eda4b3f83f6b6dec405b |
07-Mar-2014 |
Mathieu Chartier <mathieuc@google.com> |
Add more VerifyObject calls.
Added verify object calls to SirtRef, IndirectReferenceTable,
ReferenceTable.
Removed un-needed verify object in ScopedObjectAccess / DecodeJObject
since object sources are handled.
Bug: 12934910
Change-Id: I55a46a8ea61fed2a77526eda27fd2cce97a9b125
ir_field_info.cc
|
| a24122dc3aaa74b0385bb0ce30959f8a19c4a300 |
07-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Use ScopedArenaAllocator for CacheFieldLoweringInfo pass.
Change-Id: Idcc2edeb865e29b1bc42b108fc58a1f964295317
ir_analysis.cc
ir_field_info.h
|
| a9d7be62735e3356cef7e8ed797c519134a17061 |
07-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Create a scoped arena allocator and use that for LVN."
|
| 91b6ffaf38b71ed2fbbbc3e3bd2a6b4112d55751 |
07-Mar-2014 |
Yevgeny Rouban <yevgeny.y.rouban@intel.com> |
Fix LIR generation for long arithmetic operation
X86Mir2Lir::GenLongArith generated wrong LIR if the first argument
of the operation was promoted. It forgot to swap arguments if
the first was not temp, but the second was temp
Change-Id: I389f72f560ce9924859e17385bc8f64793c77b67
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
uick/x86/int_x86.cc
|
| 719d1a33f6569864f529e5a3fff59e7bca97aad0 |
06-Mar-2014 |
Ian Rogers <irogers@google.com> |
Enable annotalysis on clang ART builds.
Fix clang build errors aswell as restructure locking/mutex code for correct
thread safety analysis support.
Reorder make dependencies so that host builds build first as they should
provide better compilation errors than target.
Remove host's use of -fno-omit-frame-pointer as it has no value with correct
use of CFI, which we should have.
Change-Id: I72cea8da9a3757b1a0b3acb4081feccb7c6cef90
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
erified_method.h
|
| 83cc7ae96d4176533dd0391a1591d321b0a87f4f |
12-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Create a scoped arena allocator and use that for LVN.
This saves more than 0.5s of boot.oat compilation time
on Nexus 5.
TODO: Move other stuff to the scoped allocator. This CL
alone increases the peak memory allocation. By reusing
the memory for other parts of the compilation we should
reduce this overhead.
Change-Id: Ifbc00aab4f3afd0000da818dfe68b96713824a08
it_vector_block_iterator.h
ompiler_ir.h
rontend.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
uick/arm/call_arm.cc
uick/arm/target_arm.cc
uick/codegen_util.cc
uick/local_optimizations.cc
uick/mips/call_mips.cc
uick/mips/target_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/target_x86.cc
sa_transformation.cc
reg_analysis.cc
|
| 51a80d72dc436a4a89c636987b9cedabe774fdd6 |
06-Mar-2014 |
Maxim Kazantsev <maxim.kazantsev@intel.com> |
LongToFp result storage fixed
When converting long values to floating-point, the resulting value
was not stored properly. This was the reason of incorrect results
of arithmetic operations where such conversions were used.
Performance measurement in Quadrant Pro KPI benchmark was blocked
by long-to-fp conversion errors.
This patch ensures that result of long-to-fp conversion is stored
properly.
Change-Id: I94beffcf7f0146c0c6d5b8ae33b020c985843db0
Signed-off-by: Maxim Kazantsev <maxim.kazantsev@intel.com>
uick/x86/fp_x86.cc
|
| a44d4f508fa1642294e79d3ebecd790afe75ea60 |
05-Mar-2014 |
buzbee <buzbee@google.com> |
Fix read of uninitialized memory in InlineIndexOf
The are two flavors of IndexOf that we treat as an intrinsic: a
zero-based verion with 2 args and a 3-arg version that also takes
a start position. The same code is used for both, but Valgrind
reminded us that we shouldn't try loading a RegLocation for the
non-extent 3rd arg in the 2 argument version.
We got lucky in that the bug was benign - the generated code would
still be correct.
Change-Id: I0bc7798c8034d35007ffe6d6d62f9ceb91fc44fd
uick/gen_invoke.cc
uick/x86/target_x86.cc
|
| a1a7074eb8256d101f7b5d256cda26d7de6ce6ce |
03-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite kMirOpSelect for all IF_ccZ opcodes.
Also improve special cases for ARM and add tests.
Change-Id: I06f575b9c7b547dbc431dbfadf2b927151fe16b9
ir_graph.h
ir_optimization.cc
uick/arm/int_arm.cc
uick/codegen_util.cc
uick/mir_to_lir.h
uick/x86/int_x86.cc
|
| 093aad184b4451639951a7e012d9b55cbf8c8a07 |
04-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Remove unreachable catch entries in GenSpecialCase()."
|
| 2da882315a61072664f7ce3c212307342e907207 |
27-Feb-2014 |
Andreas Gampe <agampe@google.com> |
Initial changes towards Generic JNI option
Some initial changes that lead to an UNIMPLEMENTED. Works
by not compiling for JNI right now and tracking native methods
which have neither quick nor portable code. Uses new trampoline.
Change-Id: I5448654044eb2717752fd7359f4ef8bd5c17be6e
ompiler_ir.h
rontend.cc
uick/codegen_util.cc
|
| 00e1ec6581b5b7b46ca4c314c2854e9caa647dd2 |
28-Feb-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "Revert "Rework Quick compiler's register handling""
This reverts commit 86ec520fc8b696ed6f164d7b756009ecd6e4aace.
Ready. Fixed the original type, plus some mechanical changes
for rebasing.
Still needs additional testing, but the problem with the original
CL appears to have been a typo in the definition of the x86
double return template RegLocation.
Change-Id: I828c721f91d9b2546ef008c6ea81f40756305891
ir_graph.h
ir_optimization.cc
uick/arm/arm_lir.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_storage.h
reg_analysis.cc
|
| f796ca0715d0cb6f5afe00b3df00e80f99e186f7 |
03-Mar-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Incorrect result of the "mul-long by 1" operation"
|
| 20daf93b38870290e13518ad4db0ccfcd7d9f018 |
03-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Fix 64-bit build DCHECK failure in mir_fieldinfo.cc .
Change-Id: I6021862b42358d4d1bfb8059470da08117a34336
ir_field_info.cc
|
| be0e546730e532ef0987cd4bde2c6f5a1b14dd2a |
26-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Cache field lowering info in mir_graph.
Change-Id: I9f9d76e3ae6c31e88bdf3f59820d31a625da020f
b_optimizations.h
ex_to_dex_compiler.cc
ocal_value_numbering.cc
ocal_value_numbering_test.cc
ir_analysis.cc
ir_field_info.cc
ir_field_info.h
ir_graph.cc
ir_graph.h
ass_driver.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
|
| cc261bfd336eddac18b85d4eb47f6c905d495241 |
03-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Remove non-existent ARM insn kThumb2SubsRRI12."
|
| ae9fd93c39a341e2dffe15c61cc7d9e841fa92c4 |
11-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Tell GDB about Quick ART generated code
This is actually a lot of work. To do this, we need:
.debug_info
.debug_abbrev
.debug_frame
.debug_str
These are generated into the OAT file by OatWriter and ElfWriterQuick.
Since the Quick ART runtime doesn't use dlopen to load the OAT files,
GDB can't find this information. Use the alternate GDB JIT interface,
which can be invoked at runtime. To use this interface, an ELF image
needs to be built in memory. Read the information from the OAT file,
fixup the addresses to point to the real locations, add a symbol table
to hold the .text symbol, and then let GDB know about the information,
which will be read from the runtime address space.
This is quite primitive now, and could be cleaned up considerably. It
probably needs symbol table entries for the methods, and descriptions of
parameters and return types.
Currently only supported for X86.
This defaults to enabled for debug builds. Added dexoat --gen-gdb-info
and --no-gen-gdb-info flags to override.
Change-Id: I4d18b2370f6dfaa00c8cc1925f10717be3bd1a62
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/codegen_util.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| 3d504075f7c1204d581923460754bf6d3714b13f |
01-Mar-2014 |
Ian Rogers <irogers@google.com> |
Make out arguments non-reference types.
Also, tidy some portable related code.
Change-Id: I67c8aa52eef8b556ca117ecda1b1e75465ba06a5
ompiler_ir.h
rontend.cc
|
| b48b9eb6d181a1f52e2e605cf26a21505f1d46ed |
01-Mar-2014 |
Ian Rogers <irogers@google.com> |
Fix clang to compile and run host tests.
Don't use the computed goto interpreter with clang 3.4 as it causes compilation
to hang.
Avoid inclusion of LLVM_(HOST|DEVICE)_BUILD_MK except for with portable as it
sets clang incompatible cflags.
Most fixes are self-evident, for the quick dex file method inliner the enums
were being used with ostreams, so fix the enums and operator out python script
to allow this.
Note this change effects portable but this is untestable as portable was broken
by ELF file and mc linker changes.
Change-Id: Ia54348f6b1bd3f76d3b71c6e8c5f97626386b903
rontend.h
ass.h
ortable/mir_to_gbc.cc
ortable/mir_to_gbc.h
uick/dex_file_method_inliner.h
|
| dbb8c49d540edd2a39076093163c7218f03aa502 |
28-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Remove non-existent ARM insn kThumb2SubsRRI12.
For kOpSub/kOpAdd, prefer modified immediate encodings
because they set flags.
Change-Id: I41dcd2d43ba1e62120c99eaf9106edc61c41e157
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
|
| 39d95e695e2ef1fbd420eba6ceaa40c688099c30 |
28-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Remove unreachable catch entries in GenSpecialCase().
Fix debug build CHECK failure when we generate special
method implementation and drop unreachable catch handlers.
Bug: 13164331
Change-Id: I00e9841a2db8acaf1e81e1d9702e155c5b7e72e2
uick/mir_to_lir.cc
|
| b1f1d642093418612c0a27ce4203b421bb6eb767 |
27-Feb-2014 |
buzbee <buzbee@google.com> |
Workaround for range ops spanning vreg gap
The Dalvik runtime model includes two stacks: an interpreted stack
holding the Dalvik virtual registers, and a native stack used by
the runtime system itself. The interpreted stack closely follows
the Dalvik byte-code frame layout and invoke model, in which a
callee's incoming argument are physically located in the out region
of the caller's frame. Further, the non-argument vregs of a method
are contiguous with its in argument region.
The Art runtime model retains the notion of a callee's incoming
arguments being physically located in the out region of a caller's
frame. However, because Art uses a single-stack model, a method's
incoming argument region is not contiguous with its non-argument
virtual register storage. There is a gap between them that is used
to store the native return PC of the caller, as well as the callee
save register spill region.
The Dalvik's bytecode instruction set includes several "range"
format instructions (invoke-static-range, fill-array-data-range,
etc.). These instructions define a contiguous range of virtual
registers as arguments. Given the current Dalvik bytecode definition,
there is no rule preventing an operand range from spanning the
incoming argument and normal vregs. In Dalvik, this would not have
been an issue. In Art, it adds complexity to correctly copy a
range of arguments with a potential gap somewhere in the middle.
We don't believe this is a common situation. This workaround CL
ensures correct behavior by detecting the spanning case and falling
back to the interpreter.
If it turns out this is a more common case than expected, compiler
support can be added. More likely, though, is that we will disallow
spanning ranges in a future revision of the bytecode (going forward,
existing range-spanning bytecode will continue to be supported).
Fix for internal tracking bug 13216301
Fix for external bug https://code.google.com/p/android/issues/detail?id=66371
Change-Id: I9562aa5ab0aae8ebf333c8b72caac8a1be33ab3c
ir_analysis.cc
ir_graph.cc
ir_graph.h
|
| b565506a63e75dac4a8bb9dd54dabf5259e5b95f |
27-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Move arena_bit_vector.h/cc to compiler/utils."
|
| a1ce1fef2d49d1d537776a5308ace7102a815fe5 |
25-Feb-2014 |
Brian Carlstrom <bdc@google.com> |
Split up CommonTest into CommonRuntimeTest and CommonCompilerTest
Change-Id: I8dcf6b29a5aecd445f1a3ddb06386cf81dbc9c70
uick/mir_to_lir.h
|
| 86ec520fc8b696ed6f164d7b756009ecd6e4aace |
26-Feb-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "Rework Quick compiler's register handling"
This reverts commit 2c1ed456dcdb027d097825dd98dbe48c71599b6c.
Change-Id: If88d69ba88e0af0b407ff2240566d7e4545d8a99
ir_graph.h
ir_optimization.cc
uick/arm/arm_lir.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_storage.h
reg_analysis.cc
|
| 0e33643519b68a343a7466dcaba12b8567777cc3 |
26-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Move arena_bit_vector.h/cc to compiler/utils.
Also move MIR's BasicBlock related code from arena_bit_vector.h to
bit_vector_block_iterator.cc.
Change-Id: I85c224b387d31cf57a1ef1f1a36eaadf22f1c85d
rena_bit_vector.cc
rena_bit_vector.h
it_vector_block_iterator.cc
it_vector_block_iterator.h
ompiler_enums.h
ir_graph.h
sa_transformation.cc
|
| 2c1ed456dcdb027d097825dd98dbe48c71599b6c |
20-Feb-2014 |
buzbee <buzbee@google.com> |
Rework Quick compiler's register handling
For historical reasons, the Quick backend found it convenient
to consider all 64-bit Dalvik values held in registers
to be contained in a pair of 32-bit registers. Though this
worked well for ARM (with double-precision registers also
treated as a pair of 32-bit single-precision registers) it doesn't
play well with other targets. And, it is somewhat problematic
for 64-bit architectures.
This is the first of several CLs that will rework the way the
Quick backend deals with physical registers. The goal is to
eliminate the "64-bit value backed with 32-bit register pair"
requirement from the target-indendent portions of the backend
and support 64-bit registers throughout.
The key RegLocation struct, which describes the location of
Dalvik virtual register & register pairs, previously contained
fields for high and low physical registers. The low_reg and
high_reg fields are being replaced with a new type: RegStorage.
There will be a single instance of RegStorage for each RegLocation.
Note that RegStorage does not increase the space used. It is
16 bits wide, the same as the sum of the 8-bit low_reg and
high_reg fields.
At a target-independent level, it will describe whether the physical
register storage associated with the Dalvik value is a single 32
bit, single 64 bit, pair of 32 bit or vector. The actual register
number encoding is left to the target-dependent code layer.
Because physical register handling is pervasive throughout the
backend, this restructuring necessarily involves large CLs with
lots of changes. I'm going to roll these out in stages, and
attempt to segregate the CLs with largely mechanical changes from
those which restructure or rework the logic.
This CL is of the mechanical change variety - it replaces low_reg
and high_reg from RegLocation and introduces RegStorage. It also
includes a lot of new code (such as many calls to GetReg())
that should go away in upcoming CLs.
The tentative plan for the subsequent CLs is:
o Rework standard register utilities such as AllocReg() and
FreeReg() to use RegStorage instead of ints.
o Rework the target-independent GenXXX, OpXXX, LoadValue,
StoreValue, etc. routines to take RegStorage rather than
int register encodings.
o Take advantage of the vector representation and eliminate
the current vector field in RegLocation.
o Replace the "wide" variants of codegen utilities that take
low_reg/high_reg pairs with versions that use RegStorage.
o Add 64-bit register target independent codegen utilities
where possible, and where not virtualize with 32-bit general
register and 64-bit general register variants in the target
dependent layer.
o Expand/rework the LIR def/use flags to allow for more registers
(currently, we lose out on 16 MIPS floating point regs as
well as ARM's D16..D31 for lack of space in the masks).
o [Possibly] move the float/non-float determination of a register
from the target-dependent encoding to RegStorage. In other
words, replace IsFpReg(register_encoding_bits).
At the end of the day, all code in the target independent layer
should be using RegStorage, as should much of the target dependent
layer. Ideally, we won't be using the physical register number
encoding extracted from RegStorage (i.e. GetReg()) until the
NewLIRx() layer.
Change-Id: Idc5c741478f720bdd1d7123b94e4288be5ce52cb
ir_graph.h
ir_optimization.cc
uick/arm/arm_lir.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
eg_storage.h
reg_analysis.cc
|
| c17ebe866beb50eb6da1e6a47555cb4731467f3b |
26-Feb-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
Incorrect result of the "mul-long by 1" operation
ART handles "mul-long by 1" as a special case and try to alloc a new pair
of regs through the EvalLocWide method and then put there the multiplicand
through the StoreValueWide method. But in case when both multiplicand and
multiplier are constants, it will not place correct values in a new reg pair
and result of calculations will be incorrect. The new solution uses the
only StoreValueWide method.
Change-Id: I3d6947737c92c5a12f2840003b17a427e31d288f
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/gen_loadstore.cc
uick/x86/int_x86.cc
|
| b55c898c6e3a1569a03cedbfc6dbf93d8d8ff3dd |
25-Feb-2014 |
Bill Buzbee <buzbee@android.com> |
Merge "Implements a BasicBlock iterator using the ArenaBitVector."
|
| f7a82b422fa0428fb5678d91804610d56398b478 |
11-Feb-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
Implements a BasicBlock iterator using the ArenaBitVector.
Added the implementation of a BasicBlock iterator using the ArenaBitVector.
This patch only adds the implementation of the iterator and does not yet use
it everywhere it could be.
Added one example in ssa_transformation.cc of its use.
Change-Id: Ia85d58320c80c48a43609265ea5318a416c71f18
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
rena_bit_vector.cc
rena_bit_vector.h
sa_transformation.cc
|
| a028595f52b61e855d6dcf75f6bdf129d5568895 |
25-Feb-2014 |
Hiroshi Yamauchi <yamauchi@google.com> |
Merge "Fix hardcoded offsets in x86 String.indexOf."
|
| 2e589aa58a1372909f95e731fd6b8895f6359c3a |
25-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Encode VmapTable entries offset by 2 to reduce size.
We're using special values 0xffff and 0xfffe for an
fp register marker and for method pointer, respectively.
These values were being encoded as 3 bytes each and
this changes their encoding to 1 byte.
Bug: 9437697
Change-Id: Ic1720e898b131a5d3f6ca87d8e1ecdf76fb4160a
uick/codegen_util.cc
|
| e19c91fdb88ff6fd4e88bc5984772dcfb1e86f80 |
25-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Fix hardcoded offsets in x86 String.indexOf.
Use runtime code that will work for 32 and 64 bit too. The old code
copied constants from the runtime .S file and is correct for 32 bit code
only.
Change-Id: I668e1d7f2db8186518c358bde0759633be0d7c40
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/target_x86.cc
|
| 67f8f404a242752651771ab34df18f8eab910cb3 |
25-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Fix typo from previous commit that lead to performance regression."
|
| a36aeb30e806e0c899592bbaeee2b94bac4ab585 |
25-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix typo from previous commit that lead to performance regression.
Change-Id: I851654ae28522dd0358137578593d030e7eb9256
ir_optimization.cc
|
| 6449c62e40ef3a9bb75f664f922555affb532ee4 |
11-Feb-2014 |
Brian Carlstrom <bdc@google.com> |
Create CompilerOptions
Package up most compiler related options in CompilerOptions. Details include:
- Includes compiler filter, method thresholds, SEA IR mode.
- Excludes those needed during Runtime::Init such as CompilerCallbacks and VerificationResults.
- Pass CompilerOptions to CompilerDriver.
- Remove CompilerOptions from Runtime.
- Add ability to pass options for app and image dex2oat to runtime via
-Xcompiler-option and -Ximage-compiler-option respectively.
Other
- Replace 2x CompilerCallbacks implementations with one.
- Factor out execv code for use by both image and oat generation.
- More OatFile error_msg reporting.
- DCHECK for SuspendAll found trying to run valgrind.
Change-Id: Iecb57da907be0c856d00c3cd634b5042a229e620
rontend.cc
ir_analysis.cc
ir_graph.h
erification_results.cc
erification_results.h
|
| 9a509efcd68644616817f59ed7d442ed6f024ff9 |
21-Feb-2014 |
Brian Carlstrom <bdc@google.com> |
Merge "Convert some LOG(DEBUG) messages into more approriate levels"
|
| 9c86a0279aaf953377aa9e2277592e68bf814989 |
21-Feb-2014 |
Ian Rogers <irogers@google.com> |
Revert "Annotate used fields."
This reverts commit 7f6cf56942c8469958b273ea968db253051c5b05.
Change-Id: Ic389a194c3404ecb5bb563a405bf4a0d6336ea0d
b_optimizations.h
ocal_value_numbering.cc
ocal_value_numbering_test.cc
ir_analysis.cc
ir_annotations.cc
ir_annotations.h
ir_graph.cc
ir_graph.h
ass_driver.cc
uick/gen_common.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
|
| f59f18b2bd5432bb083205680c69fe64aaf60f39 |
17-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Fix and rewrite local value numbering.
Fix memory versioning to take aliasing and method calls
into account. Use more instructions for the null check
elimination. Return the local value name of the register
defined by the instruction if applicable.
Change-Id: I4560bc680ae1ad553a7a00fa092c937e3da9fbbe
ocal_value_numbering.cc
ocal_value_numbering.h
ocal_value_numbering_test.cc
ir_annotations.h
ir_graph.h
|
| 4dc23380cd99967d65c4f3b3f540cb0c78e9f546 |
21-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Annotate used fields."
|
| b3558e1bfe96398fc3d9bfddda2821b768a3f9a7 |
21-Feb-2014 |
Brian Carlstrom <bdc@google.com> |
Convert some LOG(DEBUG) messages into more approriate levels
Change-Id: Iace4b1e38e5bb116af78f665dad2bb6cd25c8ec7
ass_driver.cc
|
| 4028a6c83a339036864999fdfd2855b012a9f1a7 |
20-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Inline x86 String.indexOf
Take advantage of the presence of a constant search char or start index
to tune the generated code.
Change-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/x86_lir.h
|
| 7f6cf56942c8469958b273ea968db253051c5b05 |
29-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Annotate used fields.
Annotate all fields used by a method early during the
compilation, check acces rights and record field offset,
volatility, etc. Use these annotations when generating code
for IGET/IPUT/SGET/SPUT instructions.
Change-Id: I4bbf5cca4fecf53c9bf9c93ac1793e2f40c16b5f
b_optimizations.h
ir_analysis.cc
ir_annotations.cc
ir_annotations.h
ir_graph.cc
ir_graph.h
ass_driver.cc
uick/gen_common.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
|
| f3e2cc4a38389aa75eb8ee3973a535254bf1c8d2 |
18-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Code cleanup to avoid LLVM dependency when building with quick only.
Change-Id: I0985c227d775c72fd23975d4c9bf673ba32615c2
ompiler_ir.h
ir_graph.cc
uick/x86/target_x86.cc
|
| 818f2107e6d2d9e80faac8ae8c92faffa83cbd11 |
18-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Re-apply: Initial check-in of an optimizing compiler.
The classes and the names are very much inspired by V8/Dart.
It currently only supports the RETURN_VOID dex instruction,
and there is a pretty printer to check if the building of the
graph is correct.
Change-Id: I28e125dfee86ae6ec9b3fec6aa1859523b92a893
rena_allocator.cc
rena_allocator.h
rena_allocator_test.cc
rena_bit_vector.h
ackend.h
ompiler_ir.h
rowable_array.h
ir_graph.h
uick/mir_to_lir.h
|
| 1af0c0b88a956813eb0ad282664cedc391e2938f |
19-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Initial check-in of an optimizing compiler."
g++ warnings turned into errors.
This reverts commit 68a5fefa90f03fdf5a238ac85c9439c6b03eae96.
Change-Id: I09bb95d9cc13764ca8a266c41af04801a34b9fd0
rena_allocator.cc
rena_allocator.h
rena_allocator_test.cc
rena_bit_vector.h
ackend.h
ompiler_ir.h
rowable_array.h
ir_graph.h
uick/mir_to_lir.h
|
| 68a5fefa90f03fdf5a238ac85c9439c6b03eae96 |
18-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Initial check-in of an optimizing compiler.
The classes and the names are very much inspired by V8/Dart.
It currently only supports the RETURN_VOID dex instruction,
and there is a pretty printer to check if the building of the
graph is correct.
Change-Id: Id5ef1b317ab997010d4e3888e456c26bef1ab9c0
rena_allocator.cc
rena_allocator.h
rena_allocator_test.cc
rena_bit_vector.h
ackend.h
ompiler_ir.h
rowable_array.h
ir_graph.h
uick/mir_to_lir.h
|
| 2befd09cf4fe89a18a655f3e1dd310831bfa769f |
18-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Expose inline method identification for debugger."
|
| 46861fccd9b5efb3226e2003310f01e748aec0a1 |
18-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "GenSpecialCase support for x86"
|
| 84c072c348006d87a370ad6e746e2d976cbe62f2 |
17-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Expose inline method identification for debugger.
Also, record only those getter/setter functions which
we really intend to inline in the short term (and which
actually have a special implementation emitted).
Change-Id: Icb8d71707a65cb6fabae5bc9118e5f3eaf7b63dd
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| df8d416733642347c92ae2b4175b8fd0af401f31 |
18-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Rewrite the compiler interface for CompilerDriver."
|
| f5df8974173124faddb8e2b6a331959afdb94fdf |
14-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Rewrite the compiler interface for CompilerDriver.
Change-Id: I15fa9afe7ffb7283ebda8d788a1e02793e3f75a6
ompiler_ir.h
rontend.cc
ir_optimization.cc
ortable/mir_to_gbc.cc
|
| b52b2195c21ce53ef71e576d674dc549dd4b4949 |
18-Feb-2014 |
Ian Rogers <irogers@google.com> |
Merge "Optimize x86 long V*V by skipping imul"
|
| 89925e948c49616689eb4959aaf0e4ff1de18161 |
15-Feb-2014 |
Ian Rogers <irogers@google.com> |
Merge "Fixed result storage of instruction with long constant operand"
|
| de99bba92b4beac4c347772177f47bdd61e8f376 |
14-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Optimize x86 long V*V by skipping imul
The algorithm for long multiplication can take advantage of the fact
that we are multiplying a value by itself by converting 1L*2H + 2L*1H
into (2H*1L)+(2H*1L), thus converting a multiply into an addition.
Change-Id: I259a25699a8787badd943318e99bafdd06587ec6
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/int_x86.cc
|
| 79aa423fce400db3f551a3874e69e7cc4fb4f68f |
13-Feb-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
x86 compiler should handle the "div/rem by 1" case
The current implementation of the (div/rem)/imm algorithm in
ART's x86 compiler (X86Mir2Lir::GenDivRemLit) handles the only
case when imm == -1, imm >= 2 and imm <= -2, but in the case
when imm == 1, the result of calculation is incorrect.
This patch adds handler of the "div/rem by 1" case.
Change-Id: I4bcdcd9c17f5ccb6c60e7c359c00e04cd07f5bee
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
uick/x86/int_x86.cc
|
| 3bc01748ef1c3e43361bdf520947a9d656658bf8 |
06-Feb-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
GenSpecialCase support for x86
Moved GenSpecialCase from being ARM specific to common code to allow
it to be used by x86 quick as well.
Change-Id: I728733e8f4c4da99af6091ef77e5c76ae0fee850
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_graph.cc
ir_graph.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/target_arm.cc
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| 653f2bf126ee55f0a8033d840040bb00d74ea593 |
13-Feb-2014 |
Maxim Kazantsev <maxim.kazantsev@intel.com> |
Fixed result storage of instruction with long constant operand
When generating native code from .dex file, ART needs to store
operation results correctly. There were incorrect results in
computations with long constant arguments. The cause is
inappropriate usage of registers storing result of such
operation which is not yet spilled into memory and is still
required for following instructions. There were mov-s into
these registers.
This patch ensures that the result of long operation with constant
operand will be stored properly.
Change-Id: Id65801eb76f0efb67515b73b8d01423205da1892
Signed-off-by: Maxim Kazantsev <maxim.kazantsev@intel.com>
uick/x86/int_x86.cc
|
| ed8081ab1e7fd5dc1d3429fc116ee02e450bbc0f |
12-Feb-2014 |
Ian Rogers <irogers@google.com> |
Merge "Support to generate inline long to FP bytecodes for x86"
|
| 7655968112fa08844f3a810bd6203fdde4d5f58f |
12-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Generate ARM special methods from InlineMethod data."
|
| 614c2b4e219631e8c190fd9fd5d4d9cd343434e1 |
29-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Support to generate inline long to FP bytecodes for x86
long-to-float and long-to-double are now generated inline instead of calling
a helper routine. The conversion is done by using x87.
Change-Id: I196e526afec1be212898baceca8527549c3655b6
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
uick/mir_to_lir-inl.h
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/x86_lir.h
|
| 0177e53ea521ad58b70c305700dab32f1ac773b7 |
12-Feb-2014 |
Ian Rogers <irogers@google.com> |
Work in the direction of hard float quick ABIs.
Pass a shorty to ArtMethod::Invoke so that register setup can use it.
Document x86-64 ABI.
Add extra debug output for one JNI native method registration fails, namely a
dump of the Class and its dex file's location.
Add hack to get testing of OatMethod's without GC maps working in 64bit.
Change-Id: Ic06b68e18eac33637df2caf5e7e775ff95ae70f3
uick/x86/x86_lir.h
|
| abaf927f29f6feceb3df3e6ced7d01970ba0dbe9 |
11-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Re-apply: Implement cumulative timings for CompilerDriver."
|
| ea3fa0b4ba13d7bd7f7c1cd85202ccbe141a35ae |
10-Feb-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Re-apply: Implement cumulative timings for CompilerDriver.
The bug was due to how the test infrastructure works:
a compiler driver surives the stack where it is allocated.
Change-Id: I345fe0e4afb2bd15937233db8afb350f09429558
rontend.cc
|
| b1e61ad59958f70fe4db6e134b9c8dfc47733a30 |
11-Feb-2014 |
Ian Rogers <irogers@google.com> |
Merge "Tweak Mir2Lir::GenInstanceofCallingHelper for X86"
|
| 6607d97166984ce578817269f9775c15b9044190 |
10-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Tweak Mir2Lir::GenInstanceofCallingHelper for X86
Make this virtual, and split out the X86 logic. Take advantage of SETcc
instruction for X86.
I don't think I can do much more due to need to preserve arguments for
the calls.
Change-Id: I10e3eaa61b61ceac384267e3078bb6f75c37cee4
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/gen_common.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 41ccc3b70dee0b43b3de6421c0643905720f40e3 |
11-Feb-2014 |
Ian Rogers <irogers@google.com> |
Merge "Added inlined abs method with float and double type"
|
| 35d7e414134bd9f3d39e018a756617b21d49c877 |
10-Feb-2014 |
Ian Rogers <irogers@google.com> |
Merge "Support Direct Method/Type access for X86"
|
| 6c92e7d619986ecb02a379068bd6623cd5852cea |
10-Feb-2014 |
Ian Rogers <irogers@google.com> |
Merge "Rewrite GenInlinedCharAt for x86"
|
| 55d0eac918321e0525f6e6491f36a80977e0d416 |
06-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Support Direct Method/Type access for X86
Thumb generates code to optimize calls to methods within core.oat.
Implement this for X86 as well, but take advantage of mov with 32 bit
immediate and call relative with 32 bit immediate.
Fix some incorrect return locations for long inlines.
Change-Id: I1907bdfc7574f3d0aa76c7fad13dc537acdf1ed3
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 502c2a84888b7da075049dcaaeb0156602304f65 |
06-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Generate ARM special methods from InlineMethod data.
Change-Id: I204b01660a1e515879524018d1371e31f41da59b
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
|
| c9bf407643329fee7eb2603fdace46eebf618cc6 |
10-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Fix special getter/setter generation.
Change-Id: I381618bdcc46c51b50e94042f332db99c3a71a38
uick/arm/call_arm.cc
|
| 2bc47809febcf36369dd40877b8226318642b428 |
10-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Revert "Revert "Check FastInstance() early for special getters and setters.""
This reverts commit 632e458dc267fadfb8120be3ab02701e09e64875.
Change-Id: I5098c41ee84fbbb39397133a7ecfd367fecebe42
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 632e458dc267fadfb8120be3ab02701e09e64875 |
08-Feb-2014 |
Ian Rogers <irogers@google.com> |
Revert "Check FastInstance() early for special getters and setters."
This reverts commit 5dc5727261e87ba8a418e2d0e970c75f67e4ab79.
Change-Id: I3299c8ca5c3ce3f2de994bab61ea16a734f1de33
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| dbb17e378b538133750e56375bbdbb217db7b248 |
07-Feb-2014 |
Yixin Shou <yixin.shou@intel.com> |
Added inlined abs method with float and double type
This patch added the implementation for inlining java.lang.Math.abs()
method with float and double type.
Change-Id: Ic99471b4ab4176e4a0153bef383bb49944fb636f
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| 5dc5727261e87ba8a418e2d0e970c75f67e4ab79 |
05-Feb-2014 |
Vladimir Marko <vmarko@google.com> |
Check FastInstance() early for special getters and setters.
Perform the FastInstance() check for getters and setters
when they are detected by the inliner. This will help avoid
the FastInstance() check for inlining.
We also record the field offset and whether the field is
volatile and whether the method is static for use when
inlining or generating the special accessors.
Change-Id: I3f832fc9ae263883b8a984be89a3b7793398b55a
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| ef7d42fca18c16fbaf103822ad16f23246e2905d |
06-Jan-2014 |
Ian Rogers <irogers@google.com> |
Object model changes to support 64bit.
Modify mirror objects so that references between them use an ObjectReference
value type rather than an Object* so that functionality to compress larger
references can be captured in the ObjectRefererence implementation.
ObjectReferences are 32bit and all other aspects of object layout remain as
they are currently.
Expand fields in objects holding pointers so they can hold 64bit pointers. Its
expected the size of these will come down by improving where we hold compiler
meta-data.
Stub out x86_64 architecture specific runtime implementation.
Modify OutputStream so that reads and writes are of unsigned quantities.
Make the use of portable or quick code more explicit.
Templatize AtomicInteger to support more than just int32_t as a type.
Add missing, and fix issues relating to, missing annotalysis information on the
mutator lock.
Refactor and share implementations for array copy between System and uses
elsewhere in the runtime.
Fix numerous 64bit build issues.
Change-Id: I1a5694c251a42c9eff71084dfdd4b51fff716822
rena_allocator.cc
uick/gen_invoke.cc
|
| 2b724cbb4cb096d3e061c3ab720954608016ee0c |
06-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Rewrite GenInlinedCharAt for x86
Take advantage of memory addressing modes and use constant index values
directly for x86.
Change-Id: I4476862f415908ebc38ba2bc59ec4d23785f6173
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/gen_invoke.cc
|
| 2c498d1f28e62e81fbdb477ff93ca7454e7493d7 |
30-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Specializing x86 range argument copying
The ARM implementation of range argument copying was specialized in some cases.
For all other architectures, it would fall back to generating memcpy. This patch
updates the x86 implementation so it does not call memcpy and instead generates
loads and stores, favoring movement of 128-bit chunks.
Change-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ompiler_enums.h
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/utility_mips.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 67c39c4aefca23cb136157b889c09ee200b3dec6 |
01-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Support Literal pools for x86
They are being used to store double constants, which are very
expensive to generate into XMM registers. Uses the 'Compiler
Temporary' support just added. The MIR instructions are scanned for
a reference to a double constant, a packed switch or a FillArray.
These all need the address of the start of the method, since 32
bit x86 doesn't have a PC-relative addressing mode.
If needed, a compiler temporary is allocated, and the address of
the base of the method is calculated, and stored. Later uses can
just refer to the saved value.
Trickiness comes when generating the load from the literal area,
as the offset is unknown before final assembler. Assume a 32 bit
displacement is needed, and fix this if it wasn't necessary.
Use LoadValue to load the 'base of method' pointer. Fix an incorrect
test in GetRegLocation.
Change-Id: I53ffaa725dabc370e9820c4e0e78664ede3563e6
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
ir_graph.h
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 6a5ed25e8e692b1a70bfe6385329a3d5f90959ca |
06-Feb-2014 |
Ian Rogers <irogers@google.com> |
Merge "Redo x86 int arithmetic"
|
| bcec6fba95ee7974d3f7b81c3c02e7eb3ca3df00 |
17-Jan-2014 |
Dave Allison <dallison@google.com> |
Make slow paths easier to write
This adds a class LIRSlowPath that allows for deferred compilation
of slow paths. Using this object you can add code that will be
invoked out of line using a forward branch. The intention is to
move the slow paths out of the main flow and avoid branch-over
constructs that will almost always trigger. The forward branch
to the slow path code will be predicted false and this will
be correct most of the time. The slow path code returns to the
instruction after the original branch using an unconditional branch.
This is used in the following opcodes: sput, sget, const-string,
check-cast, const-class.
Others will follow.
Bug: 10864890
Change-Id: I17130c5dc20d369bc6bbf50b8cf04343263e888e
rowable_array.h
uick/codegen_util.cc
uick/gen_common.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
|
| d69835d841cb7663faaa2f1996e73e8c0b3f6d76 |
03-Feb-2014 |
buzbee <buzbee@google.com> |
Art Compiler: fix compiler temps
AOSP CL 78835 "Enable compiler temporaries" built on some earlier
work to enable the compiler to add temps in the style of Dalvik's
vRegs during MIR optimizations. However, it missed an existing
fixed-size array whose size depended on the number of temps allocated.
The allocation of this array must be delayed until after the
number of compiler temps is known.
The result was array overrun, and strange failures.
Change-Id: I986a3b557e2323e00ba852584de03a02931b3c78
uick/codegen_util.cc
uick/ralloc_util.cc
|
| feb2b4e2d1c6538777bb80b60f3a247537b6221d |
28-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Redo x86 int arithmetic
Make Mir2Lir::GenArithOpInt virtual, and implement an x86 version of it
to allow use of memory operands and knowledge of the fact that x86 has
(mostly) two operand instructions. Remove x86 specific code from the
generic version.
Add StoreFinalValue (matches StoreFinalValueWide) to handle the non-wide
cases. Add some x86 helper routines to simplify generation.
Change-Id: I6c13689c6da981f2570ab5af7a97f9816108b7ae
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/gen_common.cc
uick/gen_loadstore.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/utility_x86.cc
|
| 316116b8f11998fa07e532366482ae9493c1a1c6 |
01-Feb-2014 |
Ian Rogers <irogers@google.com> |
Merge "Remove redundant compare for x86 OpDecAndBranch"
|
| 616ffafa3130d0ef9cdd18c7adbf4e688026a724 |
31-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Enable compiler temporaries"
|
| da7a69b3fa7bb22d087567364b7eb5a75824efd8 |
09-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Enable compiler temporaries
Compiler temporaries are a facility for having virtual register sized space
for dealing with intermediate values during MIR transformations. They receive
explicit space in managed frames so they can have a home location in case they
need to be spilled. The facility also supports "special" temporaries which
have specific semantic purpose and their location in frame must be tracked.
The compiler temporaries are treated in the same way as virtual registers
so that the MIR level transformations do not need to have special logic. However,
generated code needs to know stack layout so that it can distinguish between
home locations.
MIRGraph has received an interface for dealing with compiler temporaries. This
interface allows allocation of wide and non-wide virtual register temporaries.
The information about how temporaries are kept on stack has been moved to
stack.h. This is was necessary because stack layout is dependent on where the
temporaries are placed.
Change-Id: Iba5cf095b32feb00d3f648db112a00209c8e5f55
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
b_optimizations.cc
ompiler_ir.h
rontend.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ortable/mir_to_gbc.cc
uick/codegen_util.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
reg_analysis.cc
|
| f0c3718cf42e2c45859f136e05bceb224871eae6 |
31-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Address another opportunity for reducing x86 sequence for GP pair to XMM"
|
| 39a548933c7d083647ccb1d508240198ffff5a5c |
31-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Improve GenConstString, GenS{get,put} for x86"
|
| 95e3eebaace21eb7d7169c8af8c5b04d65557a69 |
31-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "x86 updates GenInlinedUnsafePut/GenInstanceofFinal"
|
| 75ba13f244098f42584637b8fd3f6d74d2fc291a |
28-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Reduce PassDriver overhead, clean up Pass and PassDriver.
Remove name lookup map and use vector for the pass list.
Add traversal mode kNoNodes to skip BasicBlock traversal.
Replace the warn_override parameter with a DCHECK.
Move iterators from arena to the stack. Style cleanup.
Change-Id: I4bf10e28caa65efb98ce82a4d7486d803ceca535
b_optimizations.cc
b_optimizations.h
ataflow_iterator-inl.h
ataflow_iterator.h
rowable_array.h
ass.h
ass_driver.cc
ass_driver.h
|
| f7a0c5e644615fc9667eb578f1de5d05ce818435 |
28-Jan-2014 |
Hiroshi Yamauchi <yamauchi@google.com> |
Merge "Embed array class pointers at array allocation sites."
|
| f43adf68df93993e8dbf23d06da8d4fcf81e72b5 |
28-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Address another opportunity for reducing x86 sequence for GP pair to XMM
Making use of punpckldq to interleave two 32-bit values in xmm registers
in OpRegCopyWide.
Change-Id: Ibe3b9de88d69a081f08b79fee834837d0157a4a3
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
uick/x86/int_x86.cc
|
| df8ee2ea9908db3dde463fed68391b0040517653 |
28-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
x86 updates GenInlinedUnsafePut/GenInstanceofFinal
Allow x86 to inline GenInlinedUnsafePut by freeing up a temporary
register early. Make an x86 specific version of GenInstanceofFinal that
uses compare to memory and a setCC instruction.
Change-Id: I67788d7ae83776b0b9069fe4b379452190774992
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 2730db03beee4d6687ddfb5000c33c0370fbc6eb |
27-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Add VerfiedMethod to DexCompilationUnit.
Avoid some mutex locking and map lookups.
Change-Id: I8e0486af77e38dcd065569572a6b985eb57f4f63
ex_to_dex_compiler.cc
ir_graph.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/mir_to_lir.cc
erification_results.cc
erification_results.h
|
| c7f832061fea59fd6abd125f26c8ca1faec695a5 |
24-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Refactor verification results.
Rename VerificationMethodsData to VerificationResults.
Create new class VerifiedMethod to hold all the data for
a given method.
Change-Id: Ife1ac67cede20f3a2f9c7f5345f08a851cf1ed20
uick/codegen_util.cc
erification_results.cc
erification_results.h
erified_method.cc
erified_method.h
erified_methods_data.cc
erified_methods_data.h
|
| 766e9295d2c34cd1846d81610c9045b5d5093ddd |
27-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Improve GenConstString, GenS{get,put} for x86
Rewrite GenConstString for x86 to skip calling ResolveString when the
string is already resolved. Also try to avoid a register copy if the
Method* is in a promoted register.
Implement the TODO for GenS{get,put} to use compare to memory for x86 by
adding a new codegen function to compare directly to memory. Implement
a default implementation that uses a temporary register for RISC
architectures.
Change-Id: Ie163cca3d3d841aa10c50dc6592ec30af7a7cbc9
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/codegen_util.cc
uick/gen_common.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/utility_x86.cc
|
| bb8f0ab736b61db8f543e433859272e83f96ee9b |
28-Jan-2014 |
Hiroshi Yamauchi <yamauchi@google.com> |
Embed array class pointers at array allocation sites.
Following https://android-review.googlesource.com/#/c/79302, embed
array class pointers at array allocation sites in the compiled code.
Change-Id: I67a1292466dfbb7f48e746e5060e992dd93525c5
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| 7ea5dafc81b2bba7cabad26130bb75dc8f709803 |
28-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Improve x86 long multiply and shifts"
|
| 6e65720d99bd3387b72d528a46291f1ed8184ede |
27-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Remove the link from dalvik instruction back to kMirOpCheck."
|
| 4376c87eb45b287fad77a16738e76ba28956ab7d |
23-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Remove the link from dalvik instruction back to kMirOpCheck.
Free the MIR::meta for another use on PUT/GET instructions.
Change-Id: Ic5a5cc5026e2076031d7b8ce7f2b36c185bfc93a
ocal_value_numbering.cc
ir_graph.cc
ir_graph.h
uick/mir_to_lir.cc
|
| b429d1dc99b39eadd11f228e520e08b34ba3caf9 |
27-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Support GenSelect for x86"
|
| e27b3bf2c1044bfbfbe874affd3758a73009c6c6 |
23-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Support GenSelect for x86
kMirOpSelect is an extended MIR that has been generated in order
to remove trivial diamond shapes where the conditional is an
if-eqz or if-nez and on each of the paths there is a move or
const bytecode with same destination register.
This patch enables x86 to generate code for this extended MIR.
A) Handling the constant specialization of kMirOpSelect:
1) When the true case is zero and result_reg is not same as src_reg:
xor result_reg, result_reg
cmp $0, src_reg
mov t1, $false_case
cmovnz result_reg, t1
2) When the false case is zero and result_reg is not same as src_reg:
xor result_reg, result_reg
cmp $0, src_reg
mov t1, $true_case
cmovz result_reg, t1
3) All other cases (we do compare first to set eflags):
cmp $0, src_reg
mov result_reg, $true_case
mov t1, $false_case
cmovnz result_reg, t1
B) Handling the move specialization of kMirOpSelect:
1) When true case is already in place:
cmp $0, src_reg
cmovnz result_reg, false_reg
2) When false case is already in place:
cmp $0, src_reg
cmovz result_reg, true_reg
3) When neither cases are in place:
cmp $0, src_reg
mov result_reg, true_reg
cmovnz result_reg, false_reg
Change-Id: Ic7c50823208fe82019916476a0a77c6a271679fe
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ir_optimization.cc
uick/mir_to_lir.h
uick/x86/int_x86.cc
uick/x86/utility_x86.cc
|
| d3266bcc340d653e178e3ab9d74512c8db122eee |
24-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Reduce x86 sequence for GP pair to XMM
Added support for punpckldq which is useful for interleaving
32-bit values from two xmm registers.
This new instruction is now used for transfers from GP pairs
to XMM in order to reduce path length.
Change-Id: I70d9b69449dfcfb9a94a628deb74a7cffe96bac7
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
uick/x86/assemble_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 787bbf8d181284afb564dd36fea8a6453337b888 |
24-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "64bit printf flag clean-up for MIR graph."
|
| e4a8d914d4e6a2fc8015609a91cf2f6e5ea7d2ec |
24-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Revert "Remove the link from dalvik instruction back to kMirOpCheck.""
|
| c6dbf900f797aa7461d50dc4e6a996f067b97203 |
24-Jan-2014 |
Ian Rogers <irogers@google.com> |
Revert "Remove the link from dalvik instruction back to kMirOpCheck."
This reverts commit 8a3e7e769de02b5b412163cf70da9b9fbaf3b848.
Change-Id: I03a0d6180c350569b39cee2ea194903dbdfca963
ocal_value_numbering.cc
ir_graph.cc
ir_graph.h
uick/mir_to_lir.cc
|
| 4708dcd68eebf1173aef1097dad8ab13466059aa |
22-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Improve x86 long multiply and shifts
Generate inline code for long shifts by constants and do long
multiplication inline. Convert multiplication by a constant to a
shift when we can. Fix some x86 assembler problems and add the new
instructions that were needed (64 bit shifts).
Change-Id: I6237a31c36159096e399d40d01eb6bfa22ac2772
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/x86_lir.h
|
| 23b03b5b5fdaa517eda3b8b358752672cf6046b1 |
24-Jan-2014 |
Ian Rogers <irogers@google.com> |
64bit printf flag clean-up for MIR graph.
Change-Id: Ib956e48ce4061e05a5d39cfacb0d58388f5c1a25
ir_graph.cc
|
| a278ac31a1beeebd093ec64026d27a02fdc28807 |
24-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Improve x86 long divide"
|
| 57103556271b1cab119a1f0470f113c8b32cd375 |
24-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Fix X86Mir2Lir::LoadBaseIndexedDisp causing SEGV"
|
| 67122a03a4c66e01c4b64364a3701fe6ec3c5a18 |
24-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "64bit friendly printf modifiers in LIR dumping."
|
| 2bf31e67694da24a19fc1f328285cebb1a4b9964 |
23-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Improve x86 long divide
Implement inline division for literal and variable divisors. Use the
general case for dividing by a literal by using a double length multiply
by the appropriate constant with fixups. This is the Hacker's Delight
algorithm.
Change-Id: I563c250f99d89fca5ff8bcbf13de74de13815cfe
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/x86_lir.h
|
| ae427c3ba8d05599919c16f0c7c8983919cf7da3 |
24-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Fix X86Mir2Lir::LoadBaseIndexedDisp causing SEGV
If you are loading an 'array' long/double value, the generated code
could cause a SEGV, because the destination for the first load is the
same as the index register. The case for the base register being the
same as the destination was handled, but not the index register.
With this change, Calculator properly runs on the emulator.
Change-Id: Ib7e652938cdc9e127fb80ee2f541a4225a5e9ab7
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/utility_x86.cc
|
| 3f5b42f1d31c877abca2571a51dd0a5055a9b94c |
24-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Optimize x86 long arithmetic"
|
| 8a3e7e769de02b5b412163cf70da9b9fbaf3b848 |
23-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Remove the link from dalvik instruction back to kMirOpCheck.
Free the MIR::meta for another use on PUT/GET instructions.
Change-Id: I39ee5122227f449212cf6960e11b9561b8a6de7b
ocal_value_numbering.cc
ir_graph.cc
ir_graph.h
uick/mir_to_lir.cc
|
| e1cf6d895d0093dd5d1c81f6083bb4db63325a8e |
24-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Merge "Move fused cmp branch ccode to MIR::meta."
|
| 107c31e598b649a8bb8d959d6a0377937e63e624 |
24-Jan-2014 |
Ian Rogers <irogers@google.com> |
64bit friendly printf modifiers in LIR dumping.
Also correct header file inclusion ordering.
Change-Id: I8fb99e80cf1487e8b2278d4c1d110d14ed18c086
uick/arm/codegen_arm.h
uick/arm/target_arm.cc
uick/codegen_util.cc
uick/mips/target_mips.cc
uick/x86/target_x86.cc
|
| be1ca55db3362f5b100c4c65da5342fd299520bb |
15-Jan-2014 |
Hiroshi Yamauchi <yamauchi@google.com> |
Use direct class pointers at allocation sites in the compiled code.
- Rather than looking up a class from its type ID (and checking if
it's resolved/initialized, resolving/initializing if not), use
direct class pointers, if possible (boot-code-to-boot-class pointers
and app-code-to-boot-class pointers.)
- This results in a 1-2% speedup in Ritz MemAllocTest on Nexus 4.
- Embedding the object size (along with class pointers) caused a 1-2%
slowdown in MemAllocTest and isn't implemented in this change.
- TODO: do the same for array allocations.
- TODO: when/if an application gets its own image, implement
app-code-to-app-class pointers.
- Fix a -XX:gc bug.
cf. https://android-review.googlesource.com/79460/
- Add /tmp/android-data/dalvik-cache to the list of locations to
remove oat files in clean-oat-host.
cf. https://android-review.googlesource.com/79550
- Add back a dropped UNLIKELY in FindMethodFromCode().
cf. https://android-review.googlesource.com/74205
Bug: 9986565
Change-Id: I590b96bd21f7a7472f88e36752e675547559a5b1
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| e02d48fb24747f90fd893e1c3572bb3c500afced |
15-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Optimize x86 long arithmetic
Be smarter about taking advantage of a constant operand for x86 long
add/sub/and/or/xor. Using instructions with immediates and generating
results directly into memory reduces the number of temporary registers
and avoids hardcoded register usage.
Also rewrite the existing non-const x86 arithmetic to avoid fixed
register use, and use the fact that x86 instructions are two operand.
Pass the opcode to the XXXLong() routines to easily detect two operand
DEX opcodes.
Add a new StoreFinalValueWide() routine, which is similar to StoreValueWide,
but doesn't do an EvalLoc to allocate registers. The src operand must
already be in registers, and it just updates the dest location, and
calls the right live/dirty routines to get the src into the dest
properly.
Change-Id: Iefc16e7bc2236a73dc780d3d5137ae8343171f62
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_loadstore.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
|
| a894607bca7eb623bc957363e4b36f44cfeea1b6 |
22-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Move fused cmp branch ccode to MIR::meta.
This a small refactoring towards removing the large
DecodedInstruction from the MIR class.
Change-Id: I10f9ed5eaac42511d864c71d20a8ff6360292cec
ir_graph.h
ir_optimization.cc
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
|
| a0dac3e82231654be01be1e31a62dd40ea4a03a6 |
23-Jan-2014 |
Yixin Shou <yixin.shou@intel.com> |
Remove redundant compare for x86 OpDecAndBranch
For x86 OpDecAndBranch, use the flag set by the subtract to remove
the redundant compare when generating the branch to target.
Change-Id: I11e52f6d46df74cfaeeadac524dace94e2c60703
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
uick/x86/int_x86.cc
|
| 05bded260758869a5e0cf6ab55f082a586c1fb47 |
21-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up frontend.h includes and forward declarations.
Remove unused and add needed includes and forward
declarations. Explicitly include "invoke_type.h" instead
of relying on indirect inclusion via "dex_file.h".
Change-Id: Ic7a2e0e9a1f29f10008ca42a1183e357d132fd88
rontend.h
|
| 650be76eb3c38ff905ec1d9675d73e5cb9a82dac |
20-Jan-2014 |
Brian Carlstrom <bdc@google.com> |
Revert "Implement cumulative timings for CompilerDriver."
This reverts commit df013175d1aa04641e5c6175f8c786e547d31654.
rontend.cc
|
| f3f139f1cd4a9231c2f7ed8e799aa8adeb77f4d4 |
17-Jan-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Merge "Implement cumulative timings for CompilerDriver."
|
| 775c47204e273c5e8f4323e42ed34f9579aa05dd |
16-Jan-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
Pass Framework Cleanup
Fixed an end-of-program memory leak and added const as qualifiers
for various parameters.
The memory leak involves the pass array holder that would not be freed.
The solution now uses a template getter that holds the unique instance.
Change-Id: Ie8f5b0e5f4249f92851e8ba14e4238952edffee6
ass_driver.cc
ass_driver.h
|
| df013175d1aa04641e5c6175f8c786e547d31654 |
13-Jan-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement cumulative timings for CompilerDriver.
Change-Id: I3b04de7f2717273f356b8120f68d69e2379bab2f
rontend.cc
|
| a3058e7761c8fbe185f329f473c6ef9e01d681d7 |
15-Jan-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix memory error when dumping timings.
Use the pass name instead of a stack allocated std::string.
Change-Id: Ic87cf9cb7cc3c7bd847cc69c9aa1203d07136062
ass_driver.cc
|
| 4e97c539408f47145526f0062c1c06df99146a73 |
07-Jan-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
Added pass framework
The patch adds a Middle-End pass system and normalizes the current
passes into the pass framework.
Passes have:
- A start, work, and end functions.
- A gate to determine to apply the pass.
- Can provide a CFG dump folder.
mir_dataflow.cc, mir_graph.cc, mir_optimization.cc, ssa_transformation.cc:
- Changed due to moving code into bb_optimizations.cc.
- Moved certain functions from private to public due to needed from the passes.
pass.cc, pass.h:
- Pass base class
pass_driver.cc, pass_driver.h:
- The pass driver implementation.
frontend.cc:
- Replace the function calls to the passes with the pass driver.
Change-Id: I88cd82efbf6499df9e6c7f135d7e294dd724a079
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
b_optimizations.cc
b_optimizations.h
ataflow_iterator.h
rontend.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ass.h
ass_driver.cc
ass_driver.h
sa_transformation.cc
|
| d61ba4ba6fcde666adb5d5c81b1c32f0534fb2c8 |
13-Jan-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "Revert "Better support for x86 XMM registers""
This reverts commit 8ff67e3338952c70ccf3b609559bf8cc0f379cfd.
Fix applied to loc.fp usage.
Change-Id: I1eb3005392544fcf30c595923ed25bcee2dc4859
ompiler_enums.h
ir_graph.h
uick/arm/arm_lir.h
uick/gen_common.cc
uick/gen_loadstore.cc
uick/mips/mips_lir.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
reg_analysis.cc
|
| d0a515562772d7c637160e8779c4f253ee169c3a |
10-Jan-2014 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
Add suffix parameter to DumpCFG
In a lot of cases it is practical to dump CFGs. However the current dumper
has a unique naming convention. By adding an optional suffix, we can dump
the same CompilationUnit before and after an optimization by using a different
suffix.
Also, by making it optional, the change is minimal.
Change-Id: Ibd7f217ed59c093580cad9c177f9fc174a0afc11
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ir_graph.cc
ir_graph.h
|
| 0adc680c388913a63666797e907f87c4c6b0b4ea |
08-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Add conditional move support to x86 and allow GenMinMax to use it"
|
| ef6a776af2b4b8607d5f91add0ed0e8497100e31 |
20-Dec-2013 |
Ian Rogers <irogers@google.com> |
Inline codegen for long-to-double on ARM.
Change-Id: I4fc443c1b942a2231d680fc2c7a1530c86104584
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/fp_arm.cc
|
| 988e6ea9ac66edf1e205851df9bb53de3f3763f3 |
08-Jan-2014 |
Ian Rogers <irogers@google.com> |
Fix -O0 builds.
Use snprintf rather than sprintf to avoid Werror failures.
Work around an annotalysis bug when compiling -O0.
Change-Id: Ie7e0a70dbceea5fa85f98262b91bcdbd74fdef1c
uick/arm/target_arm.cc
uick/dex_file_to_method_inliner_map.h
uick/mips/target_mips.cc
uick/x86/target_x86.cc
|
| bd288c2c1206bc99fafebfb9120a83f13cf9723b |
21-Dec-2013 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Add conditional move support to x86 and allow GenMinMax to use it
X86 supports conditional moves which is useful for reducing branchiness.
This patch adds support to the x86 backend to generate conditional reg
to reg operations. Both encoder and decoder support was added for cmov.
The x86 version of GenMinMax used for generating inlined version Math.min/max
has been updated to make use of the conditional move support.
Change-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
ompiler_enums.h
uick/arm/codegen_arm.h
uick/arm/utility_arm.cc
uick/mips/codegen_mips.h
uick/mips/utility_mips.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 5ddb4104ac605d66693b55b79f26f8b8a5505e63 |
07-Jan-2014 |
Ian Rogers <irogers@google.com> |
Remove intialized static storage from dex cache.
The initialized static storage array is used by compiled code to determine if
for a sget/sput class initialization is necessary. The compiled code typically
doesn't require this test as the class is pre-initialized or the class being
accessed is the same as the current method.
Change-Id: Icbc45e692b3d0ac61e559e69edb6c9b29439e571
uick/gen_common.cc
|
| 53ee14a160fba2c71b811c97268400c50eb08249 |
03-Jan-2014 |
Ian Rogers <irogers@google.com> |
Merge "Avoid inliner spam wrt String.length."
|
| dce164adfbf679d7ec9c9dc778fa3fb596011740 |
03-Jan-2014 |
Ian Rogers <irogers@google.com> |
Avoid inliner spam wrt String.length.
Also, remove a use of std::map for our preferred SafeMap and be more explicit
with types.
Change-Id: I7b9a4bb1f73c22490fe416503e050671e7c99fe0
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 5115473c81ec855a5646a5f755afb26aa7f2b1e9 |
02-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Fix oatdump "compilercallbacks" option for runtime.
The "compilercallbacks" runtime option replaced "compiler"
in I708ca13227c809e07917ff3879a89722017e83a9 .
Fix a comment in codegen_util.cc .
Change-Id: I2c5ebd56dd96f0ee8e62b602bfe45357565471ff
uick/codegen_util.cc
|
| 6e3cb66b3885c5b9ed31bf55e2d2f8594c4f840d |
21-Dec-2013 |
Jean Christophe Beyler <jean.christophe.beyler@intel.com> |
DataflowIterator normalization
The patch normalizes the data flow iterators. The reasoning behind it is
to allow passing the base class around without knowing what underlying iterator
is used. This will thus allow called functions to call the
specified Next function. This feature will be required for future patches.
- Made DataflowIterator a base class with an abstract Next function
- Updated each derived class to use the same Next function signature
- Added comments and doxygen comments
Change-Id: I3b9bce6326675575172f0ebd3681369d40d55661
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
ataflow_iterator-inl.h
ataflow_iterator.h
|
| 090dd4489eeffb5f10051a5d9c1ed71b0a6bc4b9 |
20-Dec-2013 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Eliminate redundant x86 compare for GenDivZeroCheck
For x86, the ALU operations on general purpose registers update the flags.
Thus, when generating the zero check for divide/remainder operations, the
compare is not needed.
Change-Id: I07bfdf7d5491d3e3e9d98a932472d7f18d5b46d3
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
uick/mir_to_lir.h
uick/x86/int_x86.cc
|
| dac68ba16604085a8b7986c16956ad76caafe17e |
20-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix build: style issue."
|
| 459f4dfae3c8732fd4303a6e4df2e351d7d54f14 |
20-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Fix build: style issue.
Change-Id: I3407b9073776b2b40638491d9316111fa793e4ab
ompiler_enums.h
|
| 47d79fd31295b29e4abeb6d3fc318e6a6dd1e97c |
20-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Clean up usage of carry flag condition codes."
|
| 58af1f9385742f70aca4fcb5e13aba53b8be2ef4 |
19-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Clean up usage of carry flag condition codes.
On X86, kCondUlt and kCondUge are bound to CS and CC,
respectively, while on ARM it's the other way around. The
explicit binding in ConditionCode was wrong and misleading
and could lead to subtle bugs. Therefore, we detach those
constants and clean up usage. The CS and CC conditions are
now effectively unused but we keep them around as they may
eventually be useful.
And some minor cleanup and comments.
Change-Id: Ic5ed81d86b6c7f9392dd8fe9474b3ff718fee595
ompiler_enums.h
uick/arm/call_arm.cc
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/int_mips.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
|
| b122a4bbed34ab22b4c1541ee25e5cf22f12a926 |
20-Nov-2013 |
Ian Rogers <irogers@google.com> |
Tidy up memory barriers.
Change-Id: I937ea93e6df1835ecfe2d4bb7d84c24fe7fc097b
uick/arm/int_arm.cc
|
| e40687d053b89c495b6fbeb7a766b01c9c7e039c |
19-Dec-2013 |
Narayan Kamath <narayan@google.com> |
Merge "Fix SEGV when dumping MIR CFG"
|
| 412d4f833d8c6b43ef9725cda15bc97012d9ecdf |
18-Dec-2013 |
Mark Mendell <mark.p.mendell@intel.com> |
Improve x86 Fused long compare to literal
Generate better x86 code for the fused long comparison/branch
if one of the arguments is a literal. Use the algorithm from ARM,
tweaked for x86.
Change-Id: I872ba5dfaeeaaba6beff756d2eb6f9c6d018ce3e
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| e47ee2489a5947fc77351538d186302529b94798 |
18-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Enhance GenArrayGet, GenArrayPut for x86"
|
| 343adb52d3f031b6b5e005ff51f9cb04df219b21 |
18-Dec-2013 |
Mark Mendell <mark.p.mendell@intel.com> |
Enhance GenArrayGet, GenArrayPut for x86
As pointed out by Ian Rogers, the x86 versions didn't optimize
handling of constant index expressions. Added that support,
simplified checking of constant indices, and removed the use of
a temporary register for the 'wide' cases by using x86 scaled
addressing mode.
Change-Id: I82174e4e3674752d00d7c4730496f59d69f5f173
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 1d6df5bc3b21ccd8173c8b26c8a41b3480d14d86 |
18-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Change safecast data from set to an ordered vector."
|
| 5dce0c9721af5f9024765c16958ad2f77389aa15 |
18-Dec-2013 |
Sebastien Hertz <shertz@google.com> |
Generate devirtualization map only for native compilation.
Since devirtualization is only supported by the quick compiler, we do not need
to generate devirtualization map for non-compiled method.
Bug: 12171022
Change-Id: Ic7d6882396a05b70c4b8067bd14b7a339e0a93ab
erified_methods_data.cc
|
| a9faa706acb5a2e571ebfbc7d20f95504b3d8cdc |
17-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Change safecast data from set to an ordered vector.
This saves memory and improves performance.
Bug: 12167380
Change-Id: Ica8d9291cdd515e8eab03814fb75a85d424eb629
erified_methods_data.cc
erified_methods_data.h
|
| 778127aed722b9702a382f1276c0f05447c654be |
18-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Fix build - style issues.
Change-Id: I40540dac2a51ef326e642116b5c64fb581c849f2
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
|
| 5bb149e1e33e89216af87a4c3809e02413277772 |
17-Dec-2013 |
Mark Mendell <mark.p.mendell@intel.com> |
Fix SEGV when dumping MIR CFG
I turned on kDebugDumpCFG to try to dump the CFGs, and I found
that they caused a segmentation violation. The problem was that
the orig_sreg was -1, and IsConst then blew up.
Change-Id: Ib9acda0b11ce486e878ef2ccfae3b1bc1f82fdfb
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
ir_graph.h
|
| 5816ed48bc339c983b40dc493e96b97821ce7966 |
27-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Detect special methods at the end of verification.
This moves special method handling to method inliner
and prepares for eventual inlining of these methods.
Change-Id: I51c51b940fb7bc714e33135cd61be69467861352
ompiler_enums.h
rontend.cc
rontend.h
ir_analysis.cc
ir_graph.cc
ir_graph.h
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| 2b5eaa2b49f7489bafdadc4b4463ae27e4261817 |
13-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Move compiler code out of method verifier.
We want to detect small methods for inlining at the end of
the method verification. Instead of adding more compiler
code to the runtime, we create a callback from the runtime
into the compiler, so that we can keep the code there.
Additionally, we move the compiler-related code that was
already in the method verifier to the compiler since it
doesn't really belong to the runtime in the first place.
Change-Id: I708ca13227c809e07917ff3879a89722017e83a9
uick/codegen_util.cc
erified_methods_data.cc
erified_methods_data.h
|
| 0bf1f266869776c2dd21b3242599d74ac80855f0 |
17-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix 64-bit CAS for x86."
|
| 07dc96d370c4844c7a279c01cedf24a272b9f4f3 |
16-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Per-DexFile locking for inliner initialization."
|
| 12f96283471dea664d26c185b2185445cdc49a46 |
16-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Fix minor style issues
Follow-up to I082aa20041c933ae5fc78f12ddf491d1c775c683.
Change-Id: Ia334b192bdba231b0b9a2b2f2d7d18fcff2ca836
uick/x86/assemble_x86.cc
uick/x86/x86_lir.h
|
| bff1ef0746048978b877c0664f758d2d6006f27d |
13-Dec-2013 |
Mark Mendell <mark.p.mendell@intel.com> |
Implement GenInlinedSqrt for x86
Implemented this using the hardware instruction, which handles
NaN properly.
Tested manually using host mode.
Change-Id: I082aa20041c933ae5fc78f12ddf491d1c775c683
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
uick/x86/assemble_x86.cc
uick/x86/fp_x86.cc
uick/x86/x86_lir.h
|
| e13717e796d338b08ea66f6a7e3470ca44de707f |
20-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Per-DexFile locking for inliner initialization.
And clean up lock and compiler driver naming.
Change-Id: I1562c7f55c4b0174a36007ba6199360da06169ff
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/dex_file_to_method_inliner_map.cc
uick/dex_file_to_method_inliner_map.h
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| a6fd8ba27bc84dfb942a8fa4ea987bcb39f0f3f1 |
13-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Fix 64-bit CAS for x86.
Bug: 12117970
Change-Id: I9fbba2291124a2594161782c89dc62201cf01c08
uick/x86/assemble_x86.cc
uick/x86/int_x86.cc
|
| 8ff6e5967f93ec1188e34834c1f1240b516e32dc |
12-Dec-2013 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Don't rely on gcc extensions"
|
| 460536209b741bc469f1b0857775449abb2102fb |
12-Dec-2013 |
Bernhard Rosenkränzer <Bernhard.Rosenkranzer@linaro.org> |
Don't rely on gcc extensions
Make the code more compatible with different compilers.
clang doesn't allow extra static qualifiers on template
specializations, const qualifiers on function types,
or inline attributes on lambda functions, and is more
picky about casting away constness with reinterpret_cast.
These modifications are compatible with both gcc and
clang.
Change-Id: I739b10df2780bec537827a13679fd2bcc2cc7188
Signed-off-by: Bernhard Rosenkränzer <Bernhard.Rosenkranzer@linaro.org>
ortable/mir_to_gbc.cc
|
| ff8d298c9a937822492e85b264bc0c4a3b3642a9 |
12-Dec-2013 |
Sebastien Hertz <shertz@google.com> |
Merge "Remove unused method in DEX-to-DEX."
|
| 45c1165558eb8f9c81843b63ed362079a60c8387 |
11-Dec-2013 |
Mark Mendell <mark.p.mendell@intel.com> |
Define missing static constexpr variables
This will prevent link errors when undefined symbols when compiling at
-O0. Normally, this isn't a problem, but causes failure when compiling
at -O0 to maximize debugability
Change-Id: Iafe187b6b9344fead1bbc73004e376fad821756b
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
rena_allocator.cc
uick/dex_file_method_inliner.cc
|
| 1ebe2173d9c6144da16fd6c8790d14bcc9b38fa0 |
11-Dec-2013 |
Sebastien Hertz <shertz@google.com> |
Remove unused method in DEX-to-DEX.
Change-Id: Ice5f91b45a0ad85576475a613193f143fd76ad9f
ex_to_dex_compiler.cc
|
| cdcfdfcb704416882beec98f5a790a65c9b798ae |
11-Dec-2013 |
buzbee <buzbee@google.com> |
Art: fix basic block optimization pass
A bracket mismatch in Change 70885 inadvertently prevented the basic
block optimization pass from running in most cases. Fixed here.
Change-Id: I33f2687904cc05c90f74fb3bdc8f312d009cc0ac
ir_optimization.cc
|
| 8d4122f24d1d964e91444300045936b42986e00e |
10-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Get rid of platform-specific method inliners."
|
| b8a0c235fdfefc79477d963bb1f2fe5728f9f1c2 |
10-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Unsafe.compareAndSwapLong() intrinsic for x86."
|
| dce88522902a7f9771af87b364bbd07e656e0d1c |
10-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Add support for emitting x86 kArray instructions."
|
| 867a2b35e67ddcbec089964e8f3cd9a827186e48 |
10-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Get rid of platform-specific method inliners.
The DexFileToMethodInlinerMap dependency on CompilerDriver
and its instruction set makes it impossible to implement
verification-time checking for methods we want to inline.
Therefore, we get rid of the platform-specific method
inliners and rely on the backend's existing ability to
recognize when it can actually emit an intrinsic function.
Change-Id: I57947db93f13a26c1c794cb3584130321106306f
rontend.cc
rontend.h
uick/arm/arm_dex_file_method_inliner.cc
uick/arm/arm_dex_file_method_inliner.h
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/dex_file_to_method_inliner_map.cc
uick/dex_file_to_method_inliner_map.h
uick/mips/mips_dex_file_method_inliner.cc
uick/mips/mips_dex_file_method_inliner.h
uick/x86/x86_dex_file_method_inliner.cc
uick/x86/x86_dex_file_method_inliner.h
|
| 8171fc34bf74ed0df02385787d916bc13eb7f160 |
26-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Don't prefix GC map by length.
Bug: 11767815
Change-Id: I063917aefdf7674ee1a77736db059c9ee95ea075
uick/codegen_util.cc
|
| 400455c23d6a9a849d090b9e60ff53c4422e461b |
09-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Rename ClobberCalleeSave to *Caller*, fix it for x86."
|
| 31c2aac7137b69d5622eea09597500731fbee2ef |
09-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Rename ClobberCalleeSave to *Caller*, fix it for x86.
Change-Id: I6a72703a11985e2753fa9b4520c375a164301433
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/target_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| 73e08b37512a2d38cdbaf9a3869dbd7554e6e1b1 |
21-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix Mir2Lir::AllocFreeTemp() to return -1 on failure.
Change-Id: I190de54de347fe3f4c9bcd07b2117ad91ea5c9a3
uick/mips/utility_mips.cc
uick/ralloc_util.cc
|
| 06606b9c4a1c00154ed15f719ad8ea994e54ee8e |
02-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Performance improvement for mapping table creation.
Avoid the raw mapping tables altogether.
Change-Id: I6d1c786325d369e899a75f15701edbafdd14363f
uick/codegen_util.cc
uick/mir_to_lir.h
|
| 70b797d998f2a28e39f7d6ffc8a07c9cbc47da14 |
03-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Unsafe.compareAndSwapLong() intrinsic for x86.
Change-Id: Idbc5371a62dfdd84485a657d4548990519200205
ompiler_enums.h
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/x86_dex_file_method_inliner.cc
uick/x86/x86_lir.h
|
| 057c74a3a2d50d1247d4e6472763ca6f59060762 |
03-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Add support for emitting x86 kArray instructions.
And factor out a lot of common code.
Change-Id: Ib1f135e341404f8a6f92fcef0047ec04577d32cd
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
|
| 7ceee468756c8ba05fd8b6e82e98856a6d74bf51 |
02-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Unsafe.compareAndSwapInt()/Object() intrinsics for x86."
|
| c29bb614c60e0eb9a2bacf90f6dfce796344021e |
27-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Unsafe.compareAndSwapInt()/Object() intrinsics for x86.
Bug: 11391018
Change-Id: I0a97375103917b0e9e20f199304c17a7f849c361
uick/x86/assemble_x86.cc
uick/x86/int_x86.cc
uick/x86/x86_dex_file_method_inliner.cc
uick/x86/x86_lir.h
|
| 1e6cb63d77090ddc6aa19c755d7066f66e9ff87e |
28-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Delta-encoding of mapping tables.
Both PC offsets and dalvik offsets are delta-encoded. Since
PC offsets are increasing, the deltas are then compressed as
unsigned LEB128. Dalvik offsets are not monotonic, so their
deltas are compressed as signed LEB128.
This reduces the size of the mapping tables by about 30%
on average, 25% from the PC offset and 5% from the dalvik
offset delta encoding.
Bug: 9437697
Change-Id: I600ab9c22dec178088d4947a811cca3bc8bd4cf4
uick/codegen_util.cc
uick/mir_to_lir.h
|
| f246af27f8c0736640eb7ae78225ef6c0c0a9f0e |
27-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix intrinsic Long.reverseBytes().
Allocate temporary only if needed and initialize it from
the correct register.
Change-Id: Ifdc0e8b586e1ef90fb817687eb86e05fba1dadbe
uick/gen_invoke.cc
|
| 1da1e2fceb0030b4b76b43510b1710a9613e0c2e |
15-Nov-2013 |
buzbee <buzbee@google.com> |
More compile-time tuning
Another round of compile-time tuning, this time yeilding in the
vicinity of 3% total reduction in compile time (which means about
double that for the Quick Compile portion).
Primary improvements are skipping the basic block combine optimization
pass when using Quick (because we already have big blocks), combining
the null check elimination and type inference passes, and limiting
expensive local value number analysis to only those blocks which
might benefit from it.
Following this CL, the actual compile phase consumes roughly 60%
of the total dex2oat time on the host, and 55% on the target (Note,
I'm subtracting out the Deduping time here, which the timing logger
normally counts against the compiler).
A sample breakdown of the compilation time follows (this taken on
PlusOne.apk w/ a Nexus 4):
39.00% -> MIR2LIR: 1374.90 (Note: includes local optimization & scheduling)
10.25% -> MIROpt:SSATransform: 361.31
8.45% -> BuildMIRGraph: 297.80
7.55% -> Assemble: 266.16
6.87% -> MIROpt:NCE_TypeInference: 242.22
5.56% -> Dedupe: 196.15
3.45% -> MIROpt:BBOpt: 121.53
3.20% -> RegisterAllocation: 112.69
3.00% -> PcMappingTable: 105.65
2.90% -> GcMap: 102.22
2.68% -> Launchpads: 94.50
1.16% -> MIROpt:InitRegLoc: 40.94
1.16% -> Cleanup: 40.93
1.10% -> MIROpt:CodeLayout: 38.80
0.97% -> MIROpt:ConstantProp: 34.35
0.96% -> MIROpt:UseCount: 33.75
0.86% -> MIROpt:CheckFilters: 30.28
0.44% -> SpecialMIR2LIR: 15.53
0.44% -> MIROpt:BBCombine: 15.41
(cherry pick of 9e8e234af4430abe8d144414e272cd72d215b5f3)
Change-Id: I86c665fa7e88b75eb75629a99fd292ff8c449969
ataflow_iterator-inl.h
ataflow_iterator.h
rontend.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ortable/mir_to_gbc.cc
uick/arm/assemble_arm.cc
uick/local_optimizations.cc
uick/mips/assemble_mips.cc
uick/mir_to_lir.cc
uick/x86/assemble_x86.cc
reg_analysis.cc
|
| 3e5af82ae1a2cd69b7b045ac008ac3b394d17f41 |
21-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Intrinsic Unsafe.CompareAndSwapLong() for ARM.
(cherry picked from cb53fcd79b1a5ce608208ec454b5c19f64aaba37)
Change-Id: Iadd3cc8b4ed390670463b80f8efd579ce6ece226
uick/arm/arm_dex_file_method_inliner.cc
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/int_arm.cc
uick/mir_to_lir.h
|
| 73fbaadee029f310362c9d83a52177f00f2e5d77 |
09-Aug-2013 |
Stephen Hines <srhines@google.com> |
Update ART for LLVM merge up to r187914.
Removed NoFramePointerElimNonLeaf because this is now only specified via
a function attribute (and thus covered by existing cases).
Switch to llvm::sys::fs::F_* enums.
Remove unused DisableSimplifyLibCalls().
(cherry picked from commit 1961a2716cf02f597f06c27a0850daa2dc917586)
Change-Id: Ic7b311b635483a44265c89d47f37f4202a5b18f7
ortable/mir_to_gbc.cc
|
| 1c282e2b9a9b432e132b2c332f861cad9feb4a73 |
21-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Refactor intrinsic CAS, prepare for 64-bit version.
Bug: 11391018
Change-Id: Ic0f740e0cd0eb47f2c915f81be02f52f7721f8a3
uick/arm/arm_dex_file_method_inliner.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mips/mips_dex_file_method_inliner.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/x86_dex_file_method_inliner.cc
|
| 2247984899247b1402408d39731ff64048f0e274 |
19-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Clean up kOpCmp on ARM.
kThumb2CmnRI8M is now used.
Change-Id: I300299258ed99d86c300dee45c904c360dd44638
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
|
| ba9ece9c58de90b39c39b29dbdaee54b1654c066 |
19-Nov-2013 |
Narayan Kamath <narayan@google.com> |
Fix inlining for String.indexOf / String.isEmpty.
Before vs After:
Equals URI 1544014.6 ==============================
Equals URI 992997.6 ========================
bug: 11551453
Change-Id: I41045fda59b4c69a209d6b895dc7c2bdd1fc4e89
uick/dex_file_method_inliner.cc
|
| e4a50ee34695a9d90cf03fbb1e8afd1e434f6ee1 |
18-Nov-2013 |
Mathieu Chartier <mathieuc@google.com> |
Fix build.
cpplint errors.
Change-Id: I11141f6e19b56a3f53d6e52f3013f4d20f33f102
rontend.cc
rontend.h
uick/dex_file_method_inliner.cc
uick/dex_file_to_method_inliner_map.cc
uick/dex_file_to_method_inliner_map.h
|
| 259b592d2f61aa8addd3f6d8aa04523773f1008a |
18-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix build: add required spaces after //.
Change-Id: I332b3d514d02900ec9b485a46aa9e27c084f1bd6
uick/mips/mips_dex_file_method_inliner.cc
uick/x86/x86_dex_file_method_inliner.cc
|
| 3cebbc759a1e34d5900d35933bb364e160072c1e |
18-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Rewrite intrinsics detection." into dalvik-dev
|
| 332b7aa6220124dc638b9f7e59611c376473f128 |
18-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Improve Thumb2 instructions' use of constant operands.
Rename instructions using modified immediate to use suffix
I8M. Many were using I8 which may lead to confusion with
Thumb I8 instructions and some were using other suffixes.
Add and use CmnRI8M, increase constant range of AddRRI12 and
SubRRI12 and use BicRRI8M for applicable kOpAnd constants.
In particular, this should marginaly improve Math.abs(float)
and Math.abs(double) by converting x & 0x7fffffff to BIC.
Bug: 11579369
Change-Id: I0f17a9eb80752d2625730a60555152cdffed50ba
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
|
| 5c96e6b4dc354a7439b211b93462fbe8edea5e57 |
14-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Rewrite intrinsics detection.
Intrinsic methods should be treated as a special case of
inline methods. They should be detected early and used to
guide other optimizations. This CL rewrites the intrinsics
detection so that it can be moved to any compilation phase.
Change-Id: I4424a6a869bd98b9c478953c9e3bcaf1c6de2b33
rontend.cc
rontend.h
uick/arm/arm_dex_file_method_inliner.cc
uick/arm/arm_dex_file_method_inliner.h
uick/codegen_util.cc
uick/dex_file_method_inliner.cc
uick/dex_file_method_inliner.h
uick/dex_file_to_method_inliner_map.cc
uick/dex_file_to_method_inliner_map.h
uick/gen_invoke.cc
uick/mips/mips_dex_file_method_inliner.cc
uick/mips/mips_dex_file_method_inliner.h
uick/mir_to_lir.h
uick/x86/x86_dex_file_method_inliner.cc
uick/x86/x86_dex_file_method_inliner.h
|
| b5856431731298348b917e75a0e57672672eeb59 |
15-Nov-2013 |
Ian Rogers <irogers@google.com> |
Merge "Fix memory leaks relating to timing logger." into dalvik-dev
|
| 5fe9af720048673e62ee29597a30bb9e54c903c5 |
14-Nov-2013 |
Ian Rogers <irogers@google.com> |
Fix memory leaks relating to timing logger.
Bug: 11670287.
We use pointers to uninitialized values for control-flow in the timing logger
code, add TODO comments to clean this up later.
Remove base namespace and other bits of tidying.
Change-Id: I1e6600a1e92f974c8f58f3a405a4e4abb4d9f80f
ompiler_ir.h
rontend.cc
|
| 17189ac098b2f156713db1821b49db7b2f018bbe |
08-Nov-2013 |
buzbee <buzbee@google.com> |
Quick compiler compile-time/memory use improvement
This CL delivers a surprisingly large reduction in compile time,
as well as a significant reduction in memory usage by conditionally
removing a CFG construction feature introduced to support LLVM
bitcode generation.
In short, bitcode requires all potential exception edges to be
explicitly present in the CFG. The Quick compiler (based on the
old JIT), can ignore, at least for the purposes of dataflow
analysis, potential throw points that do not have a corresponding
catch block.
To support LLVM, we create a target basic block for every
potentially throwing instruction to give us a destination for
the exception edge. Then, following the check elimination pass,
we remove blocks whose edges have gone away.
However, if we're not using LLVM, we can skip the creation of
those things in the first place. The savings are significant.
Single-threaded compilation time on the host looks to be reduced
by something in the vicinity of 10%. We create roughly 60% fewer
basic blocks (and, importantly, the creation of fewer basic
block nodes has a multiplying effect on memory use reduction
because it results in fewer dataflow bitmaps).
Some basic block redution stats:
boot: 2325802 before, 844846 after.
Phonesky: 485472 before, 156014 after.
PlusOne: 806232 before, 243156 after.
Thinkfree: 864498 before, 264858 after.
Another nice side effect of this change is giving the basic
block optimization pass generally larger scope.
For arena memusage in the boot class path (compiled on the host):
Average Max
Before: 50,863 88,017,820
After: 41,964 4,914,208
The huge reduction in max arena memory usage is due to the
collapsing of a large initialization method. Specifically, with complete
exception edges org.ccil.cowan.tagsoup.Scheme requires 13,802
basic blocks. With exception edges collapsed, it requires 4.
This change also caused 2 latent bugs to surface.
1) The dex parsing code did not expect that the target of a switch statement
could reside in the middle of the same basic block ended by that same switch
statement.
2) The x86 backend introduced a 5-operand LIR instruction for indexed memops.
However, there was no corresponding change to the use/def mask creation code.
Thus, the 5th operand was never included in the use/def mask. This allowed
the instruction scheduling code to incorrectly move a use above a definition.
We didn't see this before because the affected x86 instructions were only used
for aget/aput, and prior to this CL those Dalvik opcodes caused a basic
block break because of the implied exception edge - which prevented the code
motion.
And finally, also included is some minor tuning of register use weighting.
Change-Id: I3f2cab7136dba2bded71e9e33b452b95e8fffc0e
rontend.cc
rontend.h
ocal_value_numbering.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
uick/mir_to_lir-inl.h
|
| 25724efbf84cce5734d1869e636cf59bc3f95941 |
12-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix CompilationUnit's UniquePtr usage.
CompilationUnit defined in compiler_ir.h uses UniquePtr with
forward-declared MIRGraph, so the ctor/dtor must be defined
in a compilation unit that actually includes MIRGraph's
definition. Otherwise the build would depend on the order of
includes.
Change-Id: I53096c5f1c975843bad3c375d4ce72a9c0656264
ompiler_ir.h
rontend.cc
|
| e21a40730ae51d8dfd0633dc021765a7839f70dc |
07-Nov-2013 |
Brian Carlstrom <bdc@google.com> |
Revert "Update ART for LLVM merge up to r187914."
This reverts commit f7ee11632e3dfda29d553d8962be9747d5ce6dfd.
ortable/mir_to_gbc.cc
|
| da5bd6a2d53113edce5761ff67d7d3eee8c830a6 |
07-Nov-2013 |
Brian Carlstrom <bdc@google.com> |
am 7ed8d7f3: Merge "Update ART for LLVM merge up to r187914."
* commit '7ed8d7f33665689a9538281fbb5c4915463dc2a6':
Update ART for LLVM merge up to r187914.
|
| 73b9eea49175748ee1eb8fcb439d65d7666c3905 |
06-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Improve Mir2Lir::GenIntrinsic() performance." into dalvik-dev
|
| f7ee11632e3dfda29d553d8962be9747d5ce6dfd |
09-Aug-2013 |
Stephen Hines <srhines@google.com> |
Update ART for LLVM merge up to r187914.
Removed NoFramePointerElimNonLeaf because this is now only specified via
a function attribute (and thus covered by existing cases).
Switch to llvm::sys::fs::F_* enums.
Remove unused DisableSimplifyLibCalls().
(cherry picked from commit 1961a2716cf02f597f06c27a0850daa2dc917586)
Change-Id: Idc2e3fb73d798a62b6ebf6f55aff5c715b2c62f7
ortable/mir_to_gbc.cc
|
| 7020278bce98a0735dc6abcbd33bdf1ed2634f1d |
23-Oct-2013 |
Dave Allison <dallison@google.com> |
Support hardware divide instruction
Bug: 11299025
Uses sdiv for division and a combo of sdiv, mul and sub for modulus.
Only does this on processors that are capable of the sdiv instruction, as determined
by the build system.
Also provides a command line arg --instruction-set-features= to allow cross compilation.
Makefile adds the --instruction-set-features= arg to build-time dex2oat runs and defaults
it to something obtained from the target architecture.
Provides a GetInstructionSetFeatures() function on CompilerDriver that can be
queried for various features. The only feature supported right now is hasDivideInstruction().
Also adds a few more instructions to the ARM disassembler
b/11535253 is an addition to this CL to be done later.
Change-Id: Ia8aaf801fd94bc71e476902749cf20f74eba9f68
ompiler_ir.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/gen_common.cc
|
| 94b400d56bb246d54a1606a3ca3f0b2157acc1fa |
05-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Improve Mir2Lir::GenIntrinsic() performance.
GenIntrinsic() spends most time just comparing the method's
declaring class name to the class names we're looking for
without hiting anything. Reduce the number of comparisons
by splitting the path for java.lang.* and other calls.
Change-Id: Ic0d42ee2bde9e86b602b421c11fb2315de774a29
uick/gen_invoke.cc
|
| e508a2090b19fe705fbc6b99d76474037a74bbfb |
04-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix unaligned Memory peek/poke intrinsics.
Change-Id: Id454464d0b28aa37f5239f1c6589ceb0b3bbbdea
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| 3beafe10c49c30ee28e1dc2f16b9f50c8074648c |
01-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Add intrinsics for Memory peek/poke." into dalvik-dev
|
| 65636e5de2375839e29e3e19ee7a7db737901cf0 |
24-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Add intrinsics for Memory peek/poke.
Add intrinsics for single memory access (non-array)
peek/poke methods in libcore.io.Memory.
Change-Id: I5d66a5b14ea89875d8afb8252eb293f7d637b83f
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| cdb4b715e77f427838b97da9bdb6654f561296ab |
01-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix intrinsic Long.reverseBytes().
Change-Id: I6cfab7e072f406439f0bde73f192149f0a6e58f7
uick/gen_invoke.cc
|
| 0b1191cfece83f6f8d4101575a06555a2d13387a |
28-Oct-2013 |
Bill Buzbee <buzbee@google.com> |
Revert "Revert "Null check elimination improvement""
This reverts commit 31aa97cfec5ee76b2f2496464e1b6f9e11d21a29.
..and thereby brings back change 380165, which was reverted
because it was buggy.
Three problems with the original CL:
1. The author ran the pre-submit tests, but used -j24 and
failed to search the output for fail messages.
2. The new null check analysis pass uses an interative
approach to identify whether a null check is needed. It
is possible that the null-check-required state may
oscillate, and a logic error caused it to stick in the
"no check needed" state.
3. Our old nemesis Dalvik untyped constants, in which 0 values
can be used both as object reference and non-object references.
This CL conservatively treats all CONST definitions as
potential object definitions for the purposes of null
check elimination.
Change-Id: I3c1744e44318276e42989502a314585e56ac57a0
ir_dataflow.cc
ir_graph.h
ir_optimization.cc
uick/codegen_util.cc
sa_transformation.cc
|
| 7195dd860e424057bd9a17d501269d9b50673f11 |
30-Oct-2013 |
Ian Rogers <irogers@google.com> |
Merge "Don't use UTF16 length as length for MUTF8." into dalvik-dev
|
| dfb325e0ddd746cd8f7c2e3723b3a573eb7cc111 |
30-Oct-2013 |
Ian Rogers <irogers@google.com> |
Don't use UTF16 length as length for MUTF8.
Bug 11367555.
Change-Id: Ia0b07072a1a49d435c3b71ed9a668b316b7ff5d8
uick/gen_invoke.cc
|
| c844a0f04e07bb0b8761e2648392251d522c89c1 |
29-Oct-2013 |
Jeff Hao <jeffhao@google.com> |
Merge "Implement Interface Method Tables (IMT)." into dalvik-dev
|
| 88474b416eb257078e590bf9bc7957cee604a186 |
24-Oct-2013 |
Jeff Hao <jeffhao@google.com> |
Implement Interface Method Tables (IMT).
Change-Id: Idf7fe85e1293453a8ad862ff2380dcd5db4e3a39
ompiler_enums.h
uick/arm/target_arm.cc
uick/gen_invoke.cc
uick/mips/target_mips.cc
uick/x86/target_x86.cc
|
| 6bdf1fff5f841f3997d4b488f00647f7aa2cdaa3 |
29-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Add intrinsics for {Short,Int,Long}.reverseBytes().
Change-Id: I34a2ec642f59fc4ff18aed59769a9e8d7e361098
uick/gen_invoke.cc
uick/mir_to_lir.h
|
| a8b4caf7526b6b66a8ae0826bd52c39c66e3c714 |
24-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Add byte swap instructions for ARM and x86.
Change-Id: I03fdd61ffc811ae521141f532b3e04dda566c77d
ompiler_enums.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/utility_arm.cc
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
|
| 17088bbded68e35da8050a40206dfd3cbba9e6d2 |
28-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Fix invalid DCHECK for movzx/movsx.
k86Movzx8RM and kMovsx8RM don't have to use eax/ecx/edx/ebx.
The incorrect check could fail for LoadBaseDisp() with
kUnsignedByte or kSignedByte.
Change-Id: I777f14cf372c7b211ad8c595d4a8a47533bdd0fc
uick/x86/assemble_x86.cc
|
| ba150c37d582eeeb8c11ba5245edc281cf31793c |
28-Aug-2013 |
Brian Carlstrom <bdc@google.com> |
Omit OatMethodOffsets for classes without compiled code
Change-Id: If0d290f4aebc778ff12d8fed017c270ad2ac3220
rena_allocator_test.cc
rena_bit_vector.h
|
| 3c2a6e2468e3e519ade6c3cfcaad7cd34243cdf1 |
26-Oct-2013 |
Ian Rogers <irogers@google.com> |
Merge "Revert "Null check elimination improvement"" into dalvik-dev
|
| 31aa97cfec5ee76b2f2496464e1b6f9e11d21a29 |
26-Oct-2013 |
Ian Rogers <irogers@google.com> |
Revert "Null check elimination improvement"
This reverts commit 4db179d1821a9e78819d5adc8057a72f49e2aed8.
Change-Id: I059c15c85860c6c9f235b5dabaaef2edebaf1de2
ir_dataflow.cc
ir_optimization.cc
uick/codegen_util.cc
sa_transformation.cc
|
| 75fabbe71ec82836787b34e7250d992da64c6be0 |
26-Oct-2013 |
Ian Rogers <irogers@google.com> |
Merge "Populate dex cache for sharpened calls." into dalvik-dev
|
| 83883d7fddf30fdb8b6903560fa1337ab991e74c |
22-Oct-2013 |
Ian Rogers <irogers@google.com> |
Populate dex cache for sharpened calls.
We ensured the resolved method was in the dex cache, but for a sharpened call
this is abstract. Ensure that the concrete method is also resolved.
Limit the use of direct dex cache based dispatch to cases where we know how to
patch the dex cache.
Bug 11389002
Change-Id: I08252686a53b5948650632837c74bcd5cbf8a862
uick/gen_invoke.cc
|
| dbf39a79d17f226936430b025ce1f0beeac2f441 |
25-Oct-2013 |
buzbee <buzbee@google.com> |
Merge "Add timing logger to Quick compiler" into dalvik-dev
|
| a61f49539a59b610e557b5513695295639496750 |
23-Aug-2013 |
buzbee <buzbee@google.com> |
Add timing logger to Quick compiler
Current Quick compiler breakdown for compiling the boot class path:
MIR2LIR: 29.674%
MIROpt:SSATransform: 17.656%
MIROpt:BBOpt: 11.508%
BuildMIRGraph: 7.815%
Assemble: 6.898%
MIROpt:ConstantProp: 5.151%
Cleanup: 4.916%
MIROpt:NullCheckElimination: 4.085%
RegisterAllocation: 3.972%
GcMap: 2.359%
Launchpads: 2.147%
PcMappingTable: 2.145%
MIROpt:CodeLayout: 0.697%
LiteralData: 0.654%
SpecialMIR2LIR: 0.323%
Change-Id: I9f77e825faf79e6f6b214bb42edcc4b36f55d291
ompiler_ir.h
rontend.cc
rontend.h
uick/arm/assemble_arm.cc
uick/codegen_util.cc
uick/mips/assemble_mips.cc
uick/mir_to_lir.cc
uick/x86/assemble_x86.cc
|
| bbf88131e138634c5e24c4cf5c5ca753fa742850 |
25-Oct-2013 |
buzbee <buzbee@google.com> |
Merge "Null check elimination improvement" into dalvik-dev
|
| 7f835b491b71a030f2a04e8e55a291bbab95eb1a |
25-Oct-2013 |
Brian Carlstrom <bdc@google.com> |
Merge "Refactor ArenaBitVector to create more general BitVector" into dalvik-dev
|
| 413e89f277ec6ba1bdf2040f5b5611f29a27a447 |
22-Oct-2013 |
Brian Carlstrom <bdc@google.com> |
Refactor ArenaBitVector to create more general BitVector
Change-Id: Ib26f2884de9ce7d620048bdf5ed6dec639622e41
rena_bit_vector.cc
rena_bit_vector.h
sa_transformation.cc
|
| 4db179d1821a9e78819d5adc8057a72f49e2aed8 |
23-Oct-2013 |
buzbee <buzbee@google.com> |
Null check elimination improvement
See b/10862777
Improves the null check elimination pass by tracking visibility
of object definitions, rather than successful uses of object
dereferences. For boot class path, increases static null
check elimination success rate from 98.4% to 98.6%. Reduces
size of boot.oat by ~300K bytes.
Fixes loop nesting depth computation, which is used by register
promotion, and tweaked the heuristics.
Fixes a bug in verbose listing output in which a basic block
id is directly dereferenced, rather than first being converted
to a pointer.
Change-Id: Id01c20b533cdb12ea8fc4be576438407d0a34cec
ir_dataflow.cc
ir_optimization.cc
uick/codegen_util.cc
sa_transformation.cc
|
| 8a70bcc04a6a95f5236ae9e41060254c1496dfbe |
24-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Merge "Fix x86 code generation for 0x0F 0x3A 0x?? instructions." into dalvik-dev
|
| fd7e33f67d535e9f4363ef8c1b56ca7aede3b1a6 |
24-Oct-2013 |
Ian Rogers <irogers@google.com> |
Merge "Throw IOException at source of failing to open a dex file." into dalvik-dev
|
| e6ed00ba91da535fbe1d0b5a5705e99da149d82e |
24-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Fix x86 code generation for 0x0F 0x3A 0x?? instructions.
Change-Id: I9b2b2190787d1e5674818159aa96e513d6325b54
uick/x86/assemble_x86.cc
uick/x86/x86_lir.h
|
| 8d31bbd3d6536de12bc20e3d29cfe03fe848f9da |
13-Oct-2013 |
Ian Rogers <irogers@google.com> |
Throw IOException at source of failing to open a dex file.
Before is:
java.lang.ClassNotFoundException: Didn't find class "GCBench" on path: DexPathList[[zip file "/disk2/dalvik-dev/out/host/linux-x86/framework/GCBench.jar"],nativeLibraryDirectories=[/disk2/dalvik-dev/out/host/linux-x86/lib]]
at dalvik.system.BaseDexClassLoader.findClass(BaseDexClassLoader.java:56)
at java.lang.ClassLoader.loadClass(ClassLoader.java:511)
at java.lang.ClassLoader.loadClass(ClassLoader.java:469)
Suppressed: java.lang.ClassNotFoundException: GCBench
at java.lang.Class.classForName(Native Method)
at java.lang.BootClassLoader.findClass(ClassLoader.java:781)
at java.lang.BootClassLoader.loadClass(ClassLoader.java:841)
at java.lang.ClassLoader.loadClass(ClassLoader.java:504)
... 1 more
Caused by: java.lang.NoClassDefFoundError: Class "LGCBench;" not found
... 5 more
And after is:
java.lang.ClassNotFoundException: Didn't find class "GCBench" on path: DexPathList[[zip file "/disk2/dalvik-dev/out/host/linux-x86/framework/GCBench.jar"],nativeLibraryDirectories=[/disk2/dalvik-dev/out/host/linux-x86/lib]]
at dalvik.system.BaseDexClassLoader.findClass(BaseDexClassLoader.java:56)
at java.lang.ClassLoader.loadClass(ClassLoader.java:511)
at java.lang.ClassLoader.loadClass(ClassLoader.java:469)
Suppressed: java.io.IOException: Zip archive '/disk2/dalvik-dev/out/host/linux-x86/framework/GCBench.jar' doesn't contain classes.dex
at dalvik.system.DexFile.openDexFile(Native Method)
at dalvik.system.DexFile.<init>(DexFile.java:80)
at dalvik.system.DexFile.<init>(DexFile.java:59)
at dalvik.system.DexPathList.loadDexFile(DexPathList.java:268)
at dalvik.system.DexPathList.makeDexElements(DexPathList.java:235)
at dalvik.system.DexPathList.<init>(DexPathList.java:113)
at dalvik.system.BaseDexClassLoader.<init>(BaseDexClassLoader.java:48)
at dalvik.system.PathClassLoader.<init>(PathClassLoader.java:38)
at java.lang.ClassLoader.createSystemClassLoader(ClassLoader.java:128)
at java.lang.ClassLoader.access$000(ClassLoader.java:65)
at java.lang.ClassLoader$SystemClassLoader.<clinit>(ClassLoader.java:81)
at java.lang.ClassLoader.getSystemClassLoader(ClassLoader.java:137)
Suppressed: java.lang.ClassNotFoundException: GCBench
at java.lang.Class.classForName(Native Method)
at java.lang.BootClassLoader.findClass(ClassLoader.java:781)
at java.lang.BootClassLoader.loadClass(ClassLoader.java:841)
at java.lang.ClassLoader.loadClass(ClassLoader.java:504)
... 1 more
Caused by: java.lang.NoClassDefFoundError: Class "LGCBench;" not found
... 5 more
Also, move dex file verifier messages out of logs.
In the process the ClassLinker::dex_lock_ needed tidying to cover a smaller
scope. Bug 11301553.
Change-Id: I80058652e11e7ea63457cc01a0cb48afe1c15543
rena_allocator.cc
|
| a8d24bf578a1022ff14f89f650074dc39b9667fe |
21-Oct-2013 |
buzbee <buzbee@google.com> |
Merge "64-bit prep" into dalvik-dev
|
| 0d82948094d9a198e01aa95f64012bdedd5b6fc9 |
12-Oct-2013 |
buzbee <buzbee@google.com> |
64-bit prep
Preparation for 64-bit roll.
o Eliminated storing pointers in 32-bit int slots in LIR.
o General size reductions of common structures to reduce impact
of doubled pointer sizes:
- BasicBlock struct was 72 bytes, now is 48.
- MIR struct was 72 bytes, now is 64.
- RegLocation was 12 bytes, now is 8.
o Generally replaced uses of BasicBlock* pointers with 16-bit Ids.
o Replaced several doubly-linked lists with singly-linked to save
one stored pointer per node.
o We had quite a few uses of uintptr_t's that were a holdover from
the JIT (which used pointers to mapped dex & actual code cache
addresses rather than trace-relative offsets). Replaced those with
uint32_t's.
o Clean up handling of embedded data for switch tables and array data.
o Miscellaneous cleanup.
I anticipate one or two additional CLs to reduce the size of MIR and LIR
structs.
Change-Id: I58e426d3f8e5efe64c1146b2823453da99451230
rena_bit_vector.h
ompiler_enums.h
ompiler_ir.h
ataflow_iterator-inl.h
ataflow_iterator.h
ir_analysis.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ortable/mir_to_gbc.cc
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/utility_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
sa_transformation.cc
|
| b917ea1a62aa0ab8eca3f689ef64b5be34e11abb |
18-Oct-2013 |
Ian Rogers <irogers@google.com> |
Fix intrinsification of floatToRawIntBits.
Accidentially lost in quick refactoring in
commit fa57c47f1b72916371a9c2d5c1389219bce655b4.
Change-Id: Ic83cf257306efa66a236f2034ffbff3b53579090
uick/gen_invoke.cc
|
| 379067c3970fb225332cca25301743f5010d3ef9 |
16-Oct-2013 |
Ian Rogers <irogers@google.com> |
Don't clobber array reg if its needed for card marking
Change-Id: I4377717a2431ffd7e8fafc2e2cca7c1285b38668
uick/arm/int_arm.cc
uick/mips/int_mips.cc
|
| 773aab1e8992b2834153eb23c976a4eb0da51a71 |
14-Oct-2013 |
Ian Rogers <irogers@google.com> |
Correct free-ing of temp register.
Bug 11199874.
The card mark was potentially using a register freed just before. Make the
free-ing of temps strongly correspond to their allocation.
Change-Id: I3d1e8c923b7fd8b3666e841d3ff9a46e6eb58318
uick/arm/int_arm.cc
uick/mips/int_mips.cc
uick/x86/int_x86.cc
|
| 409fe94ad529d9334587be80b9f6a3d166805508 |
11-Oct-2013 |
buzbee <buzbee@google.com> |
Quick assembler fix
This CL re-instates the select pattern optimization disabled by
CL 374310, and fixes the underlying problem: improper handling of
the kPseudoBarrier LIR opcode. The bug was introduced in the
recent assembler restructuring. In short, LIR pseudo opcodes (which
have values < 0), should always have size 0 - and thus cause no
bits to be emitted during assembly. In this case, bad logic caused
us to set the size of a kPseudoBarrier opcode via lookup through the
EncodingMap.
Because all pseudo ops are < 0, this meant we did an array underflow
load, picking up whatever garbage was located before the EncodingMap.
This explains why this error showed up recently - we'd previuosly just
gotten a lucky layout.
This CL corrects the faulty logic, and adds DCHECKs to uses of
the EncodingMap to ensure that we don't try to access w/ a
pseudo op. Additionally, the existing is_pseudo_op() macro is
replaced with IsPseudoLirOp(), named similar to the existing
IsPseudoMirOp().
Change-Id: I46761a0275a923d85b545664cadf052e1ab120dc
ir_optimization.cc
uick/arm/assemble_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/local_optimizations.cc
uick/mips/assemble_mips.cc
uick/mips/target_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/target_x86.cc
|
| 41cdd43bd6968a06b1344efdd57ccf302f997a0e |
11-Oct-2013 |
Ian Rogers <irogers@google.com> |
Disable select instruction generation on ARM.
Change-Id: I114547d44605b06b2fed396b2fbad03935f66ebc
ir_optimization.cc
|
| 252a00273bc945ebe4a1d77d82d085fdff2ae769 |
10-Oct-2013 |
Sebastien Hertz <shertz@google.com> |
Merge "Add missing references." into dalvik-dev
|
| 74e256b8e442417d4ba2054c771c1e4f41062768 |
04-Oct-2013 |
Sebastien Hertz <shertz@google.com> |
Add missing references.
This mainly avoids implicit copies when extracting an object from a container.
Change-Id: If4d0e6153e8c2b48345fde5bb546b4c65649fcf3
sa_transformation.cc
|
| a9a8254c920ce8e22210abfc16c9842ce0aea28f |
04-Oct-2013 |
Ian Rogers <irogers@google.com> |
Improve quick codegen for aput-object.
1) don't type check known null.
2) if we know types in verify don't check at runtime.
3) if we're runtime checking then move all the code out-of-line.
Also, don't set up a callee-save frame for check-cast, do an instance-of test
then throw an exception if that fails.
Tidy quick entry point of Ldivmod to Lmod which it is on x86 and mips.
Fix monitor-enter/exit NPE for MIPS.
Fix benign bug in mirror::Class::CannotBeAssignedFromOtherTypes, a byte[]
cannot be assigned to from other types.
Change-Id: I9cb3859ec70cca71ed79331ec8df5bec969d6745
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| c68fb2094b562186a571f496fc46ad2b85b02a39 |
02-Oct-2013 |
Ian Rogers <irogers@google.com> |
Merge "Inflate contended lock word by suspending owner." into dalvik-dev
|
| d9c4fc94fa618617f94e1de9af5f034549100753 |
02-Oct-2013 |
Ian Rogers <irogers@google.com> |
Inflate contended lock word by suspending owner.
Bug 6961405.
Don't inflate monitors for Notify and NotifyAll.
Tidy lock word, handle recursive lock case alongside unlocked case and move
assembly out of line (except for ARM quick). Also handle null in out-of-line
assembly as the test is quick and the enter/exit code is already a safepoint.
To gain ownership of a monitor on behalf of another thread, monitor contenders
must not hold the monitor_lock_, so they wait on a condition variable.
Reduce size of per mutex contention log.
Be consistent in calling thin lock thread ids just thread ids.
Fix potential thread death races caused by the use of FindThreadByThreadId,
make it invariant that returned threads are either self or suspended now.
Code size reduction on ARM boot.oat 0.2%.
Old nexus 7 speedup 0.25%, new nexus 7 speedup 1.4%, nexus 10 speedup 2.24%,
nexus 4 speedup 2.09% on DeltaBlue.
Change-Id: Id52558b914f160d9c8578fdd7fc8199a9598576a
uick/arm/call_arm.cc
uick/arm/int_arm.cc
uick/gen_common.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
|
| b48819db07f9a0992a72173380c24249d7fc648a |
15-Sep-2013 |
buzbee <buzbee@google.com> |
Compile-time tuning: assembly phase
Not as much compile-time gain from reworking the assembly phase as I'd
hoped, but still worthwhile. Should see ~2% improvement thanks to
the assembly rework. On the other hand, expect some huge gains for some
application thanks to better detection of large machine-generated init
methods. Thinkfree shows a 25% improvement.
The major assembly change was to establish thread the LIR nodes that
require fixup into a fixup chain. Only those are processed during the
final assembly pass(es). This doesn't help for methods which only
require a single pass to assemble, but does speed up the larger methods
which required multiple assembly passes.
Also replaced the block_map_ basic block lookup table (which contained
space for a BasicBlock* for each dex instruction unit) with a block id
map - cutting its space requirements by half in a 32-bit pointer
environment.
Changes:
o Reduce size of LIR struct by 12.5% (one of the big memory users)
o Repurpose the use/def portion of the LIR after optimization complete.
o Encode instruction bits to LIR
o Thread LIR nodes requiring pc fixup
o Change follow-on assembly passes to only consider fixup LIRs
o Switch on pc-rel fixup kind
o Fast-path for small methods - single pass assembly
o Avoid using cb[n]z for null checks (almost always exceed displacement)
o Improve detection of large initialization methods.
o Rework def/use flag setup.
o Remove a sequential search from FindBlock using lookup table of 16-bit
block ids rather than full block pointers.
o Eliminate pcRelFixup and use fixup kind instead.
o Add check for 16-bit overflow on dex offset.
Change-Id: I4c6615f83fed46f84629ad6cfe4237205a9562b4
ompiler_enums.h
rontend.cc
ir_analysis.cc
ir_graph.cc
ir_graph.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/local_optimizations.cc
uick/mips/assemble_mips.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| d91d6d6a80748f277fd938a412211e5af28913b1 |
26-Sep-2013 |
Ian Rogers <irogers@google.com> |
Introduce Signature type to avoid string comparisons.
Method resolution currently creates strings to then compare with strings formed
from methods in other dex files. The temporary strings are purely created for
the sake of comparisons. This change creates a new Signature type that
represents a method signature but not as a string. This type supports
comparisons and so can be used when searching for methods in resolution.
With this change malloc is no longer the hottest method during dex2oat (now its
memset) and allocations during verification have been reduced. The verifier is
commonly what is populating the dex cache for methods and fields not declared
in the dex file itself.
Change-Id: I5ef0542823fbcae868aaa4a2457e8da7df0e9dae
uick/codegen_util.cc
uick/mir_to_lir.h
|
| fc0e94bed3f88ed7e50854fd8dfaf5dcb345250f |
24-Sep-2013 |
Ian Rogers <irogers@google.com> |
StringPiece clean up.
Profile guided clean up.
Try to avoid creating StringPieces with the contents of a dex file where
the length is known.
Try to avoid RegTypeCache::FromDescriptor when there's a class available.
Make ConstantType::ConstantValue inlinable.
Saving of about 50ms from a 2 threaded ThinkFree compile on host.
Change-Id: I47a12c3c76f46e2c9805be1c3a3e3870fe1f5d85
uick/gen_invoke.cc
|
| 8b2c0b9abc3f520495f4387ea040132ba85cae69 |
19-Sep-2013 |
Ian Rogers <irogers@google.com> |
Use class def index from java.lang.Class.
Bug: 10244719
Depends on:
https://googleplex-android-review.git.corp.google.com/362363
This removes the computation of the dex file index, when necessary this is
computed by searching the dex file. Its only necessary in
dalvik.system.DexFile.defineClassNative and DexFile::FindInClassPath, the
latter not showing up significantly in profiling with this change.
Change-Id: I20c73a3b17d86286428ab0fd21bc13f51f36c85c
ompiler_ir.h
ex_to_dex_compiler.cc
rontend.cc
rontend.h
ir_graph.cc
ir_graph.h
uick/codegen_util.cc
|
| 1fc5800def46a2fa6cbd235fcb8af099ee35a127 |
18-Sep-2013 |
buzbee <buzbee@google.com> |
Art compiler: minor instruction assembler fix
During the assembly phase, we iteratively walk through the LIR
encoding instructions until we can complete a full pass without
without having to change the sequence because of displacement
overflow.
In the (fairly common) situation in which a 16-bit cbnz/cbz
can't reach the target, we expand it to a compare and branch sequence
Initially, we use a 16-bit Thumb1 unconditional branch, which itself
may be expanded in a future pass to a 32-bit branch.
The original cbnz/cbz LIR is converted into a cmp, and a new branch
instruction is inserted following. The problem here is that by doing
a following insertion, that new instruction will be the next one
considered to determine if it can reach it's target. Because it
is new, though, it's starting offset will show as zero - making it
much more likely that it will be treated as a displacement overflow
and be converted to a 32-bit branch.
This is not a correctness issue - the bad offset will be corrected
on the next pass, but it does result in unnecessary uses of 32-bit
branches where 16-bit ones would work.
Change-Id: Ie68a93fd319f0f7c603e1d870588047ad6a0779f
uick/arm/assemble_arm.cc
|
| c729a6b936d59562bd9fb830a595d9ff65dfd129 |
15-Sep-2013 |
buzbee <buzbee@google.com> |
Improve promotion of double-precision regs
Minor rework of the double allocation mechanism to more explicitly
manage the allocation of preserved floating point single pairs as
doubles.
Change-Id: Id9db4b0e86e5ef54a5db587f367e00efdf7e98d6
uick/mir_to_lir.h
uick/ralloc_util.cc
|
| cd6f5fe5b08dd6bcc05cbc77355593bf3540caa0 |
14-Sep-2013 |
buzbee <buzbee@google.com> |
Merge "Timely color fix" into dalvik-dev
|
| d0a03b8099347dee6e4bab3af95e14cd5a03b29c |
14-Sep-2013 |
buzbee <buzbee@google.com> |
Timely color fix
See b/10690000
For efficiency, the Quick compiler will not flush incoming register
arguments to the frame if their underlying Dalvik virtual registers
have been promoted to physical registers. In this case, though,
there was a bug on Arm devices in that an incoming Double was promoted
to physical floating point registers, but not in a usable form. The
entry code generation saw that both halves of the double were promoted,
but failed to check if it was in a form usable as a double.
In this particular case, it meant that subsequent uses of the incoming
argument referred to the uninitialized home location in the frame,
resulting in garbage color values.
That's the bug. Another problem is that the incoming double should
never have been promoted to an unusable state in the first place - but
that's merely an efficiency issue and will be addressed in another CL.
Note: no good way to generate a regression test for this issue. The
bug triggered because of an unusual sequence of events driving register
promotion that can't easily (or robustly) be triggered from Java source.
Change-Id: I7242422277193a04376461134dde71e9dec55576
uick/gen_invoke.cc
|
| 2de2aa1a96dfa5bebc004f29b5dbfafd37039cee |
13-Sep-2013 |
Jeff Hao <jeffhao@google.com> |
Make inlined CAS32 loop until store is successful if values match.
The native implementation of compareAndSwap uses android_atomic_cas,
which will repeat the strex until it succeeds. The compiled version
was changed to do the same.
Bug: 10530407
Change-Id: I7efb3f92d0d0610fcc5a885e2c97f1d701b5a4ea
uick/arm/int_arm.cc
|
| b048dd2b662c19644361f4396a1e8d6213445ee8 |
12-Sep-2013 |
Mathieu Chartier <mathieuc@google.com> |
Merge "Add valgrind support to compiler arena allocator." into dalvik-dev
|
| 75165d015cc737f951d4264f8c55012298abdb18 |
12-Sep-2013 |
Mathieu Chartier <mathieuc@google.com> |
Add valgrind support to compiler arena allocator.
Change-Id: Id9974301d3810bfac968ee562b01a11098e402c2
rena_allocator.cc
rena_allocator.h
|
| 77695d2e13d522426c973546391c07ac88242bc2 |
12-Sep-2013 |
Jeff Hao <jeffhao@google.com> |
am 715084a2: am 9d7e507f: am 95848d01: Revert "Fix CAS intrinsic to clear exclusive if values don\'t match."
* commit '715084a24a9db1b898c38bbf4a8a7383da76e326':
Revert "Fix CAS intrinsic to clear exclusive if values don't match."
|
| 95848d01adae14c6a9ba433f6789a9462edb8e7d |
12-Sep-2013 |
Jeff Hao <jeffhao@google.com> |
Revert "Fix CAS intrinsic to clear exclusive if values don't match."
Ian is correct. I can still see this bug even with this change.
This reverts commit 3a0831507637028a439712dedaaddd7cd0893995.
Change-Id: I780f2de926f1ff7576adc679c56a6cf491dad127
uick/arm/int_arm.cc
|
| 3a0831507637028a439712dedaaddd7cd0893995 |
12-Sep-2013 |
Jeff Hao <jeffhao@google.com> |
Fix CAS intrinsic to clear exclusive if values don't match.
The LDREX has a matching STREX if the values match, but it needed
a CLREX for the case where they didn't.
Bug: 10530407
Change-Id: I46b474cca326a251536e7f214c80486694431386
(cherry picked from commit 78765e84a3654357a03f84b76985556cf7d9731a)
uick/arm/int_arm.cc
|
| 78765e84a3654357a03f84b76985556cf7d9731a |
12-Sep-2013 |
Jeff Hao <jeffhao@google.com> |
Fix CAS intrinsic to clear exclusive if values don't match.
The LDREX has a matching STREX if the values match, but it needed
a CLREX for the case where they didn't.
Bug: 10530407
Change-Id: I46b474cca326a251536e7f214c80486694431386
uick/arm/int_arm.cc
|
| bd663de599b16229085759366c56e2ed5a1dc7ec |
11-Sep-2013 |
buzbee <buzbee@google.com> |
Compile-time tuning: register/bb utilities
This CL yeilds about a 4% improvement in the compilation phase
of dex2oat (single-threaded; multi-threaded compilation is
more difficult to accurately measure). The register utilities
could stand to be completely rewritten, but this gets most of the
easy benefit.
Next up: the assembly phase.
Change-Id: Ife5a474e9b1a6d9e501e888dda6749d34eb77e96
rowable_array.h
ir_graph.cc
ir_graph.h
uick/arm/codegen_arm.h
uick/arm/target_arm.cc
uick/codegen_util.cc
uick/mips/codegen_mips.h
uick/mips/target_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/codegen_x86.h
uick/x86/target_x86.cc
|
| fffd663bd276ee5fd8fda6641689546042429981 |
10-Sep-2013 |
buzbee <buzbee@google.com> |
Merge "More Quick compile-time tuning: labels & branches" into dalvik-dev
|
| 252254b130067cd7a5071865e793966871ae0246 |
09-Sep-2013 |
buzbee <buzbee@google.com> |
More Quick compile-time tuning: labels & branches
This CL represents a roughly 3.5% performance improvement for the
compile phase of dex2oat. Move of the gain comes from avoiding
the generation of dex boundary LIR labels unless a debug listing
is requested. The other significant change is moving from a basic block
ending branch model of "always generate a fall-through branch, and then
delete it if we can" to a "only generate a fall-through branch if we need
it" model.
The data motivating these changes follow. Note that two area of
potentially attractive gain remain: restructing the assembler model and
reworking the register handling utilities. These will be addressed
in subsequent CLs.
--- data follows
The Quick compiler's assembler has shown up on profile reports a bit
more than seems reasonable. We've tried a few quick fixes to apparently
hot portions of the code, but without much gain. So, I've been looking at
the assembly process at a somewhat higher level. There look to be several
potentially good opportunities.
First, an analysis of the makeup of the LIR graph showed a surprisingly
high proportion of LIR pseudo ops. Using the boot classpath as a basis,
we get:
32.8% of all LIR nodes are pseudo ops.
10.4% are LIR instructions which require pc-relative fixups.
11.8% are LIR instructions that have been nop'd by the various
optimization passes.
Looking only at the LIR pseudo ops, we get:
kPseudoDalvikByteCodeBoundary 43.46%
kPseudoNormalBlockLabel 21.14%
kPseudoSafepointPC 20.20%
kPseudoThrowTarget 6.94%
kPseudoTarget 3.03%
kPseudoSuspendTarget 1.95%
kPseudoMethodExit 1.26%
kPseudoMethodEntry 1.26%
kPseudoExportedPC 0.37%
kPseudoCaseLabel 0.30%
kPseudoBarrier 0.07%
kPseudoIntrinsicRetry 0.02%
Total LIR count: 10167292
The standout here is the Dalvik opcode boundary marker. This is just a
label inserted at the beginning of the codegen for each Dalvik bytecode.
If we're also doing a verbose listing, this is also where we hang the
pretty-print disassembly string. However, this label was also
being used as a convenient way to find the target of switch case
statements (and, I think at one point was used in the Mir->GBC conversion
process).
This CL moves the use of kPseudoDalvikByteCodeBoundary labels to only
verbose listing runs, and replaces the codegen uses of the label with
the kPseudoNormalBlockLabel attached to the basic block that contains the
switch case target. Great savings here - 14.3% reduction in the number of
LIR nodes needed. After this CL, our LIR pseudo proportions drop to 21.6%
of all LIR. That's still a lot, but much better. Possible further
improvements via combining normal labels with kPseudoSafepointPC labels
where appropriate, and also perhaps reduce memory usage by using a
short-hand form for labels rather than a full LIR node. Also, many
of the basic block labels are no longer branch targets by the time
we get to assembly - cheaper to delete, or just ingore?
Here's the "after" LIR pseudo op breakdown:
kPseudoNormalBlockLabel 37.39%
kPseudoSafepointPC 35.72%
kPseudoThrowTarget 12.28%
kPseudoTarget 5.36%
kPseudoSuspendTarget 3.45%
kPseudoMethodEntry 2.24%
kPseudoMethodExit 2.22%
kPseudoExportedPC 0.65%
kPseudoCaseLabel 0.53%
kPseudoBarrier 0.12%
kPseudoIntrinsicRetry 0.04%
Total LIR count: 5748232
Not done in this CL, but it will be worth experimenting with actually
deleting LIR nodes from the graph when they are optimized away, rather
than just setting the NOP bit. Keeping them around is invaluable
during debugging - but when not debugging it may pay off if the cost of
node removal is less than the cost of traversing through dead nodes
in subsequent passes.
Next up (and partially in this CL - but mostly to be done in follow-on
CLs) is the overall assembly process. Inherited from the trace JIT,
the Quick compiler has a fairly simple-minded approach to instruction
assembly. First, a pass is made over the LIR list to assign offsets
to each instruction. Then, the assembly pass is made - which generates
the actual machine instruction bit patterns and pushes the instruction
data into the code_buffer. However, the code generator takes the "always
optimistic" approach to instruction selection and emits the shortest
instruction. If, during assembly, we find that a branch or load doesn't
reach, that short-form instruction is replaces with a longer sequence.
Of course, this invalidates the previously-computed offset calculations.
Assembly thus is an iterative process: compute offsets and then assemble
until we survive an assembly pass without invalidation. This seems
like a likely candidate for improvement. First, I analyzed the
number of retries required, and the reason for invalidation over the
boot classpath load.
The results: more than half of methods don't require a retry, and
very few require more than 1 extra pass:
5 or more: 6 of 96334
4 or more: 22 of 96334
3 or more: 140 of 96334
2 or more: 1794 of 96334 - 2%
1 or more: 40911 of 96334 - 40%
0 retries: 55423 of 96334 - 58%
The interesting group here is the one that requires 1 retry. Looking
at the reason, we see three typical reasons:
1. A cbnz/cbz doesn't reach (only 7 bits of offset)
2. A 16-bit Thumb1 unconditional branch doesn't reach.
3. An unconditional branch which branches to the next instruction
is encountered, and deleted.
The first 2 cases are the cost of the optimistic strategy - nothing
much to change there. However, the interesting case is #3 - dead
branch elimination. A further analysis of the single retry group showed
that 42% of the methods (16305) that required a single retry did so
*only* because of dead branch elimination. The big question here is
why so many dead branches survive to the assembly stage. We have
a dead branch elimination pass which is supposed to catch these - perhaps
it's not working correctly, should be moved later in the optimization
process, or perhaps run multiple times.
Other things to consider:
o Combine the offset generation pass with the assembly pass. Skip
pc-relative fixup assembly (other than assigning offset), but push
LIR* for them into work list. Following the main pass, zip through
the work list and assemble the pc-relative instructions (now that we
know the offsets). This would significantly cut back on traversal
costs.
o Store the assembled bits into both the code buffer and the LIR.
In the event we have to retry, only the pc-relative instructions
would need to be assembled, and we'd finish with a pass over the
LIR just to dumb the bits into the code buffer.
Change-Id: I50029d216fa14f273f02b6f1c8b6a0dde5a7d6a6
rowable_array.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/int_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/local_optimizations.cc
uick/mips/assemble_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/x86/assemble_x86.cc
|
| 02ed4c04468ca5f5540c5b704ac3e2f30eb9e8f4 |
06-Sep-2013 |
Ian Rogers <irogers@google.com> |
Move disassembler out of runtime.
Bug: 9877500.
Change-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29
rena_allocator.cc
ex_to_dex_compiler.cc
ortable/mir_to_gbc.cc
uick/mir_to_lir.cc
|
| 28c2300d9a85f4e7288fb5d94280332f923b4df3 |
07-Sep-2013 |
buzbee <buzbee@google.com> |
More compile-time tuning
Small, but measurable, improvement.
Change-Id: Ie3c7180f9f9cbfb1729588e7a4b2cf6c6d291c95
rena_bit_vector.cc
rena_bit_vector.h
ir_graph.h
uick/codegen_util.cc
reg_analysis.cc
|
| 9f799db0e4124d3158cde6ead854289fba10f3aa |
07-Sep-2013 |
buzbee <buzbee@google.com> |
Merge "Compile-time tuning" into dalvik-dev
|
| 56c717860df2d71d66fb77aa77f29dd346e559d3 |
06-Sep-2013 |
buzbee <buzbee@google.com> |
Compile-time tuning
Specialized the dataflow iterators and did a few other minor tweaks.
Showing ~5% compile-time improvement in a single-threaded environment;
less in multi-threaded (presumably because we're blocked by something
else).
Change-Id: I2e2ed58d881414b9fc97e04cd0623e188259afd2
ataflow_iterator-inl.h
ataflow_iterator.h
rowable_array.h
ir_analysis.cc
ir_dataflow.cc
ir_optimization.cc
ortable/mir_to_gbc.cc
uick/codegen_util.cc
uick/local_optimizations.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
sa_transformation.cc
reg_analysis.cc
|
| 9b297bfc588c7d38efd12a6f38cd2710fc513ee3 |
06-Sep-2013 |
Ian Rogers <irogers@google.com> |
Refactor CompilerDriver::Compute..FieldInfo
Don't use non-const reference arguments.
Move ins before outs.
Change-Id: I7b251156388d8f07513b3da62ebfd29e5fd9ff76
ex_to_dex_compiler.cc
uick/arm/call_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/mir_to_lir.h
|
| 65ec92cf13c9d11c83711443a02e4249163d47f1 |
06-Sep-2013 |
Ian Rogers <irogers@google.com> |
Refactor CompilerDriver::ComputeInvokeInfo
Don't use non-const reference arguments.
Move ins before outs.
Change-Id: I4a7b8099abe91ea60f93a56077f4989303fa4876
ex_to_dex_compiler.cc
ir_dataflow.cc
uick/gen_invoke.cc
|
| 866709c85da0c0d2c76968713e4dc4a35dce27fd |
06-Sep-2013 |
Sebastien Hertz <shertz@google.com> |
Merge "Disable devirtualization detection in DEX-to-DEX compiler." into dalvik-dev
|
| 1e54d68ce8e77dfe63340275d11a072c5184c89a |
06-Sep-2013 |
Sebastien Hertz <shertz@google.com> |
Disable devirtualization detection in DEX-to-DEX compiler.
This CL allows the DEX-to-DEX compiler to disable devirtualization detection.
This allows to quicken invoke-virtual/range instructions that used to be
eligible for devirtualization.
Bug: 10632943
Change-Id: I6c9f4d3249cf42b47f004be5825b3186fa83501e
ex_to_dex_compiler.cc
ir_dataflow.cc
uick/gen_invoke.cc
|
| d1946a2621553968599ca4db0f4200877c30186f |
04-Sep-2013 |
Mathieu Chartier <mathieuc@google.com> |
am 22955837: Merge "Multi threaded hashed deduplication during compilation." into klp-dev
* commit '22955837e20f126845ff0e516dfa6f74ec81d240':
Multi threaded hashed deduplication during compilation.
|
| 193bad9b9cfd10642043fa2ebbfc68bd5f9ede4b |
30-Aug-2013 |
Mathieu Chartier <mathieuc@google.com> |
Multi threaded hashed deduplication during compilation.
Moved deduplication to be in the compiler driver instead of oat
writer. This enables deduplication to be performed on multiple
threads. Also added a hash function to avoid excessive comparison
of byte arrays.
Improvements:
Before (alloats host):
real 1m6.967s
user 4m22.940s
sys 1m22.610s
Thinkfree.apk (target mako):
0m23.74s real 0m50.95s user 0m9.50s system
0m24.62s real 0m50.61s user 0m10.07s system
0m24.22s real 0m51.44s user 0m10.09s system
0m23.70s real 0m51.05s user 0m9.97s system
0m23.50s real 0m50.74s user 0m10.63s system
After (alloats host):
real 1m5.705s
user 4m44.030s
sys 1m29.990s
Thinkfree.apk (target mako):
0m23.32s real 0m51.38s user 0m10.00s system
0m23.49s real 0m51.20s user 0m9.80s system
0m23.18s real 0m50.80s user 0m9.77s system
0m23.52s real 0m51.22s user 0m10.02s system
0m23.50s real 0m51.55s user 0m9.46s system
Bug: 10552630
Change-Id: Ia6d06a747b86b0bfc4473b3cd68f8ce1a1c7eb22
uick/codegen_util.cc
|
| 6e288203c06c71c945935830b91a215a273bf8e6 |
30-Aug-2013 |
Brian Carlstrom <bdc@google.com> |
Revert "Update ART for LLVM merge up to r187914."
This reverts commit 70814f7746793934a29e010211ef6e652ad75cd2.
ortable/mir_to_gbc.cc
|
| 70814f7746793934a29e010211ef6e652ad75cd2 |
09-Aug-2013 |
Stephen Hines <srhines@google.com> |
Update ART for LLVM merge up to r187914.
Removed NoFramePointerElimNonLeaf because this is now only specified via
a function attribute (and thus covered by existing cases).
Switch to llvm::sys::fs::F_* enums.
Remove unused DisableSimplifyLibCalls().
(cherry picked from commit 1961a2716cf02f597f06c27a0850daa2dc917586)
Change-Id: I49e691b6771f7e3f77fe583841ea51b06ee7cfdf
ortable/mir_to_gbc.cc
|
| e0948e13d5a4552e6a2728087573c07961e4a4f9 |
29-Aug-2013 |
Brian Carlstrom <bdc@google.com> |
Make DexFiles opened from files readonly by default, but writable during dex2oat
Bug: 9618388
Change-Id: I83f2e16ee8446a79a94a84971146d807bb0c9ee0
ex_to_dex_compiler.cc
|
| a7d56cf5e0fe6da41969f6dd841aef0d73f09d93 |
29-Aug-2013 |
Ian Rogers <irogers@google.com> |
Revert "Update ART for LLVM merge up to r187914."
This reverts commit eaeab46304a139da495de941e853ce9acdace175.
Change-Id: I854e09c9c988702de08a9ff642619761d1d57639
(cherry picked from commit 03feadd72f6205f0b88fe69aaa30c69d1b2e8c2d)
ortable/mir_to_gbc.cc
|
| eaeab46304a139da495de941e853ce9acdace175 |
09-Aug-2013 |
Stephen Hines <srhines@google.com> |
Update ART for LLVM merge up to r187914.
Removed NoFramePointerElimNonLeaf because this is now only specified via
a function attribute (and thus covered by existing cases).
Switch to llvm::sys::fs::F_* enums.
Remove unused DisableSimplifyLibCalls().
(cherry picked from commit 1961a2716cf02f597f06c27a0850daa2dc917586)
Change-Id: I5ee58031e423838cdc8968675192f9b63a7d867d
ortable/mir_to_gbc.cc
|
| 11b63d13f0a3be0f74390b66b58614a37f9aa6c1 |
27-Aug-2013 |
buzbee <buzbee@google.com> |
Quick compiler: division by literal fix
The constant propagation optimization pass attempts to identify
constants in Dalvik virtual registers and handle them more efficiently.
The use of small constants in divison, though, was handled incorrectly
in that the high level code correctly detected the use of a constant,
but the actual code generation routine was only expecting the use of
a special constant form opcode.
see b/10503566
Change-Id: I88aa4d2eafebb2b1af1a1e88049f1845aefae261
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/gen_common.cc
uick/mips/codegen_mips.h
uick/mips/int_mips.cc
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
|
| f6c4b3ba3825de1dbb3e747a68b809c6cc8eb4db |
25-Aug-2013 |
Mathieu Chartier <mathieuc@google.com> |
New arena memory allocator.
Before we were creating arenas for each method. The issue with doing this
is that we needed to memset each memory allocation. This can be improved
if you start out with arenas that contain all zeroed memory and recycle
them for each method. When you give memory back to the arena pool you do
a single memset to zero out all of the memory that you used.
Always inlined the fast path of the allocation code.
Removed the "zero" parameter since the new arena allocator always returns
zeroed memory.
Host dex2oat time on target oat apks (2 samples each).
Before:
real 1m11.958s
user 4m34.020s
sys 1m28.570s
After:
real 1m9.690s
user 4m17.670s
sys 1m23.960s
Target device dex2oat samples (Mako, Thinkfree.apk):
Without new arena allocator:
0m26.47s real 0m54.60s user 0m25.85s system
0m25.91s real 0m54.39s user 0m26.69s system
0m26.61s real 0m53.77s user 0m27.35s system
0m26.33s real 0m54.90s user 0m25.30s system
0m26.34s real 0m53.94s user 0m27.23s system
With new arena allocator:
0m25.02s real 0m54.46s user 0m19.94s system
0m25.17s real 0m55.06s user 0m20.72s system
0m24.85s real 0m55.14s user 0m19.30s system
0m24.59s real 0m54.02s user 0m20.07s system
0m25.06s real 0m55.00s user 0m20.42s system
Correctness of Thinkfree.apk.oat verified by diffing both of the oat files.
Change-Id: I5ff7b85ffe86c57d3434294ca7a621a695bf57a9
rena_allocator.cc
rena_allocator.h
rena_bit_vector.cc
rena_bit_vector.h
ompiler_ir.h
rontend.cc
rowable_array.h
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
uick/arm/call_arm.cc
uick/arm/target_arm.cc
uick/codegen_util.cc
uick/local_optimizations.cc
uick/mips/call_mips.cc
uick/mips/target_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/target_x86.cc
sa_transformation.cc
reg_analysis.cc
|
| 4b8c13ee44c4c959d7b8de9adff7ce6df48c31d0 |
24-Aug-2013 |
Brian Carlstrom <bdc@google.com> |
Fix sort order to make register promotion stable
Also some minor oatdump fixes
Change-Id: I5679835bf684b98d130b77ecf00bda5f6547d383
uick/ralloc_util.cc
|
| ec0cf9b8217ceaddbb53faa78c3cf34b07ac87b1 |
22-Aug-2013 |
Brian Carlstrom <bdc@google.com> |
Revert "Update ART for LLVM merge up to r187914."
This reverts commit b8a874ca3b13007f4bf688963483ffb3c76e0d7d.
ortable/mir_to_gbc.cc
|
| b8a874ca3b13007f4bf688963483ffb3c76e0d7d |
09-Aug-2013 |
Stephen Hines <srhines@google.com> |
Update ART for LLVM merge up to r187914.
Removed NoFramePointerElimNonLeaf because this is now only specified via
a function attribute (and thus covered by existing cases).
Switch to llvm::sys::fs::F_* enums.
Remove unused DisableSimplifyLibCalls().
(cherry picked from commit 1961a2716cf02f597f06c27a0850daa2dc917586)
Change-Id: I7403dca575104de2ceb5fc0619611366a8058e5d
ortable/mir_to_gbc.cc
|
| 677ffa4eb84bcf667b1ae43559b61aff85a1322d |
22-Aug-2013 |
Ian Rogers <irogers@google.com> |
Don't skip compilation for portable builds.
Portable build fix.
Change-Id: If4e5efedb232d52257714af020c50a52843cbad8
rontend.cc
|
| fe9ca4028f379688ecba6132ac3738171176b3e4 |
21-Aug-2013 |
buzbee <buzbee@google.com> |
Compiler filter update
Tweak of the compiler filter to give better results for applications
which are not dominated by tight arithmetic loops. Deleted
the "DeferCompilation" setting - it didn't differ enough from the
"Space" setting. Added "Everything" setting to support forced
compilation (for images and testing). Previously used "Speed"
for that purpose, but in the speed setting there are some things we
don't want to compile.
Change-Id: Ia53b14f2044fc9738c1a4c1318f8204f2c25abe3
ir_analysis.cc
ir_graph.h
|
| b7767e8db32cac29370852170871a6769388195f |
20-Aug-2013 |
Brian Carlstrom <bdc@google.com> |
Revert "Update ART for LLVM merge up to r187914."
This reverts commit 6a94caa048121858ee8e71f84caf7b9ae1f940df.
ortable/mir_to_gbc.cc
|
| 6a94caa048121858ee8e71f84caf7b9ae1f940df |
09-Aug-2013 |
Stephen Hines <srhines@google.com> |
Update ART for LLVM merge up to r187914.
Removed NoFramePointerElimNonLeaf because this is now only specified via
a function attribute (and thus covered by existing cases).
Switch to llvm::sys::fs::F_* enums.
Remove unused DisableSimplifyLibCalls().
(cherry picked from commit 1961a2716cf02f597f06c27a0850daa2dc917586)
(cherry picked from commit 6e6819f7b8b4820ae2b1003a516fe9aa60fa478e)
Change-Id: I4fb59f291bb58c7ed8575f71a44f7c59f653a5ec
ortable/mir_to_gbc.cc
|
| 9329e6d1a8ff8d3775c4a9db9a7bb97694bc267d |
19-Aug-2013 |
buzbee <buzbee@google.com> |
More suspend check repair.
The previous fix to the suspend check optimization mechanism left
a bug in the handling of constant-folded branches.
Change-Id: Ib71f1cb9f17203bee26746006e568d448666962d
ir_graph.cc
ir_graph.h
ir_optimization.cc
uick/mir_to_lir.cc
|
| cbcfaf3a410e35730c4daeaff6c791665764925a |
19-Aug-2013 |
buzbee <buzbee@google.com> |
Fix suspend check optimization
Art's Quick compiler currently uses a convervative mechanism
to ensure that a safe point will be reached within a "small" amount
of time. Explicit suspend checks are placed prior to backwards
branches and on returns. There are a lot of ways to optimize,
which we'll get to in the future, but for now the only optimization
is to detect a backwards branch that targets a return block. That's
a common pattern in dex, and simple to detect. In those cases, we can
suppress the suspend check on the backwards branch knowing that the
return will do it.
However, the notion of what is a backwards branch got a bit muddied
with some mir optimizations that transform the graph by changing the
sense of branches. What started off as a taken backwards branch may
turn into a fallthrough backwards branch.
This CL avoid the confusion by marking branches backwards based on
their original dex targets rather than using the post-transform test
of backwardness.
Change-Id: I9b30be168c801af51bae7f66ecd442edcb115a18
ir_graph.cc
ir_graph.h
ir_optimization.cc
uick/mir_to_lir.cc
|
| be6810d714bbf0c9c3c1d7d919e1aef5a3b52a20 |
14-Aug-2013 |
Brian Carlstrom <bdc@google.com> |
Revert "Update ART for LLVM merge up to r187914."
This reverts commit 6e6819f7b8b4820ae2b1003a516fe9aa60fa478e.
ortable/mir_to_gbc.cc
|
| 6e6819f7b8b4820ae2b1003a516fe9aa60fa478e |
09-Aug-2013 |
Stephen Hines <srhines@google.com> |
Update ART for LLVM merge up to r187914.
Removed NoFramePointerElimNonLeaf because this is now only specified via
a function attribute (and thus covered by existing cases).
Switch to llvm::sys::fs::F_* enums.
Remove unused DisableSimplifyLibCalls().
(cherry picked from commit 1961a2716cf02f597f06c27a0850daa2dc917586)
Change-Id: Idc2e3fb73d798a62b6ebf6f55aff5c715b2c62f7
ortable/mir_to_gbc.cc
|
| ea46f950e7a51585db293cd7f047de190a482414 |
30-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Refactor java.lang.reflect implementation
Cherry-picked from commit ed41d5c44299ec5d44b8514f6e17f802f48094d1.
Move to ArtMethod/Field instead of AbstractMethod/Field and have
java.lang.reflect APIs delegate to ArtMethod/ArtField.
Bug: 10014286.
Change-Id: Iafc1d8c5b62562c9af8fb9fd8c5e1d61270536e7
ex_to_dex_compiler.cc
uick/gen_common.cc
uick/gen_invoke.cc
|
| 73a79074c06d8b0a8c14946438c59c3821d88fe7 |
13-Aug-2013 |
Stephen Hines <srhines@google.com> |
Revert "Update ART for LLVM merge up to r187914."
This reverts commit 1961a2716cf02f597f06c27a0850daa2dc917586.
ortable/mir_to_gbc.cc
|
| 34de74bb9d91534ab7ebbd1f73ee1d96db894b4c |
13-Aug-2013 |
Stephen Hines <srhines@google.com> |
Merge "Update ART for LLVM merge up to r187914." into klp-dev
|
| a49bdffd3826ea45b5d8f435b2add160871351bb |
31-Jul-2013 |
Ian Rogers <irogers@google.com> |
Don't add barriers to clinit methods.
Change-Id: I13e6c008feb8c19e452d6e2f88b2bbbcac997de5
(cherry picked from commit 9fc16eb43fe938f0cddb13638bd7cbc2ea9534a2)
ex_to_dex_compiler.cc
|
| 96faf5b363d922ae91cf25404dee0e87c740c7c5 |
10-Aug-2013 |
Ian Rogers <irogers@google.com> |
Uleb128 compression of vmap and mapping table.
Bug 9437697.
Change-Id: I30bcb97d12cd8b46d3b2cdcbdd358f08fbb9947a
(cherry picked from commit 1809a72a66d245ae598582d658b93a24ac3bf01e)
uick/codegen_util.cc
uick/mir_to_lir.h
|
| 468532ea115657709bc32ee498e701a4c71762d4 |
05-Aug-2013 |
Ian Rogers <irogers@google.com> |
Entry point clean up.
Create set of entry points needed for image methods to avoid fix-up at load time:
- interpreter - bridge to interpreter, bridge to compiled code
- jni - dlsym lookup
- quick - resolution and bridge to interpreter
- portable - resolution and bridge to interpreter
Fix JNI work around to use JNI work around argument rewriting code that'd been
accidentally disabled.
Remove abstact method error stub, use interpreter bridge instead.
Consolidate trampoline (previously stub) generation in generic helper.
Simplify trampolines to jump directly into assembly code, keeps stack crawlable.
Dex: replace use of int with ThreadOffset for values that are thread offsets.
Tidy entry point routines between interpreter, jni, quick and portable.
Change-Id: I52a7c2bbb1b7e0ff8a3c3100b774212309d0828e
(cherry picked from commit 848871b4d8481229c32e0d048a9856e5a9a17ef9)
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.h
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
|
| 1961a2716cf02f597f06c27a0850daa2dc917586 |
09-Aug-2013 |
Stephen Hines <srhines@google.com> |
Update ART for LLVM merge up to r187914.
Removed NoFramePointerElimNonLeaf because this is now only specified via
a function attribute (and thus covered by existing cases).
Switch to llvm::sys::fs::F_* enums.
Remove unused DisableSimplifyLibCalls().
Change-Id: I792e3a31f5dc289459aeacac995e7c828b6063d3
ortable/mir_to_gbc.cc
|
| ee17e0aa4d24deb11c1766bfcc6a864519df1c1e |
31-Jul-2013 |
buzbee <buzbee@google.com> |
Compilation filter
This CL introduces a static compilation filter mechanism intended
to allow us to reduce compilation time and space requirements until
we have a profiling mechanism in place.
It supports 5 modes of filtering:
o interpret-only (compile nothing)
o deferred-compilation (compile only those methods believe to be
compute-intensive)
o space (optimized for space)
o balanced (best return on space investment)
o speed (compile everything)
A future CL will allow the default filtering mode to be set
via system property. For now, you can pass it in via command
line as follows:
dalvikvm -compiler-filter:[interpret-only|defer-compilation|
space|balanced|speed]
or dex2oat --runtime-arg -compiler-filter:[one of the above modes]
Creating a file named art/SMALL_ART will force the filter
default to interpret-only. Later on we'll move this capability
to a persistent system property.
or modify kDefaultCompilerFilter in runtime.h
It also changes the compiler driver to allow the compilers to
decline to compile a method by return NULL.
Change-Id: Ic73411818f8bb845a4a19a05b0395c50902c534f
(cherry picked from commit a024a0686c3b0fea13f362bff70d65981e5febc5)
rontend.cc
rontend.h
ir_analysis.cc
ir_graph.h
|
| 1b8b2e49fdfee50cafafe01d73346af6dfcf231d |
31-Jul-2013 |
Sebastien Hertz <shertz@google.com> |
Merge "Adds a DEX-to-DEX compilation level." into dalvik-dev
|
| 75021222d9c03a80fa5c136db0d5fb8d82d04031 |
16-Jul-2013 |
Sebastien Hertz <shertz@google.com> |
Adds a DEX-to-DEX compilation level.
This CL adds a DEX-to-DEX compilation level which allows the DEX-to-DEX
compiler to ensure correctness on classes with soft-failed verification.
Bug: 9307738
Change-Id: If051336bf81370bca55872c8c75ccd573d8ca391
ex_to_dex_compiler.cc
|
| 0b12b9318c29d7c32d5a605e0b1dc309872c8a37 |
31-Jul-2013 |
buzbee <buzbee@google.com> |
resolved conflicts for merge of 2724776a to dalvik-dev
Change-Id: I7f55e92b7d4d2c57812bc6eb7daa7bb5b77cacc2
|
| 2724776ad521eebb1c7f0e4be56d6e6ab4764f86 |
28-Jul-2013 |
buzbee <buzbee@google.com> |
Support inline dex data, take 2
Allow switch and array data blocks to appear interspersed
with Dex code (rather than just at the end).
Bug 10040419
Change-Id: Ia2850070f0e702381eb402f604d675e5a0b101de
ir_graph.cc
|
| 7655f29fabc0a12765de828914a18314382e5a35 |
29-Jul-2013 |
Ian Rogers <irogers@google.com> |
Portable refactorings.
Separate quick from portable entrypoints.
Move architectural dependencies into arch.
Change-Id: I9adbc0a9782e2959fdc3308215f01e3107632b7c
uick/arm/call_arm.cc
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/x86/call_x86.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
|
| 166db04e259ca51838c311891598664deeed85ad |
26-Jul-2013 |
Ian Rogers <irogers@google.com> |
Move assembler out of runtime into compiler/utils.
Other directory layout bits of clean up. There is still work to separate quick
and portable in some files (e.g. argument visitor, proxy..).
Change-Id: If8fecffda8ba5c4c47a035f0c622c538c6b58351
uick/arm/call_arm.cc
uick/arm/int_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
|
| 46a1270fad27d81904ed60d0df56761356af500d |
27-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Revert "Support inline dex data"
This reverts commit 728328a441c6d3172283f3e44d120550997b5887.
ir_graph.cc
|
| 64d8f18c94b23cb4ff908304aef4d9f3f5a85f39 |
27-Jul-2013 |
buzbee <buzbee@google.com> |
Merge "Support inline dex data"
|
| 728328a441c6d3172283f3e44d120550997b5887 |
27-Jul-2013 |
buzbee <buzbee@google.com> |
Support inline dex data
Dx always places switch table and array data following executable
code. However, embedding data inline appears to be legal - and
the Garmin Connect app does this. Unknown is what tool generated
the odd dex code. This CL reworks dex parsing to support inline data.
Further, a verification check to require a move-exception at
the beginning of catch regions is disabled. Dalvik's verifier appears
to only require that if a move-exception exists, it must be at
the beginning of the catch. If there is value to the check
requiring a move-exception, we'll need to enable it based on a
future dex version.
Change-Id: I80c78544993acb999f7c62d32479c3c8455b56cb
ir_graph.cc
|
| 7934ac288acfb2552bb0b06ec1f61e5820d924a4 |
26-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/comments issues
Change-Id: Iae286862c85fb8fd8901eae1204cd6d271d69496
rena_allocator.h
ompiler_enums.h
ataflow_iterator.h
ex_to_dex_compiler.cc
rontend.cc
rontend.h
ocal_value_numbering.h
ir_graph.cc
ir_graph.h
ir_optimization.cc
ortable/mir_to_gbc.cc
uick/arm/arm_lir.h
uick/arm/call_arm.cc
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mips/call_mips.cc
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/fp_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
sa_transformation.cc
reg_analysis.cc
|
| 2b1de652896040e3049814da91c835b2b500af55 |
20-Jul-2013 |
buzbee <buzbee@google.com> |
am 479f83c1: Dex compiler: re-enable method pattern matching
* commit '479f83c196d5a95e36196eac548dc6019e70a5be':
Dex compiler: re-enable method pattern matching
|
| ebd66389dacec3118232fbd426c70dbed573cff1 |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am 4274889d: Fixing cpplint readability/check issues
* commit '4274889d48ef82369bf2c1ca70d84689b4f9e93a':
Fixing cpplint readability/check issues
|
| ac43ae545ffca66aac813ed3e6ab54e3559b5e4e |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am 2d88862f: Fixing cpplint readability/casting issues
* commit '2d88862f0752a7a0e65145b088f49dabd49d4284':
Fixing cpplint readability/casting issues
|
| 58d8b956e7d83bb1b219405be87e135c89b9cdb2 |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am 02c8cc6d: Fixing cpplint whitespace/blank_line, whitespace/end_of_line, whitespace/labels, whitespace/semicolon issues
* commit '02c8cc6d1312a2b55533f02f6369dc7c94672f90':
Fixing cpplint whitespace/blank_line, whitespace/end_of_line, whitespace/labels, whitespace/semicolon issues
|
| 5775391897aa290d96ad903ddbe00f66e7a6a4f8 |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am 6f485c62: Fix cpplint whitespace/indent issues
* commit '6f485c62b9cfce3ab71020c646ab9f48d9d29d6d':
Fix cpplint whitespace/indent issues
|
| d0b495921acbe890892eddd6a7b055acee3d6505 |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am 9b7085a4: Fix cpplint readability/braces issues
* commit '9b7085a4e7c40e7fa01932ea1647a4a33ac1c585':
Fix cpplint readability/braces issues
|
| fbf49d27f4a4e74c5901899a1c4879946b7bdf4e |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
resolved conflicts for merge of 50af9793 to dalvik-dev
Change-Id: I13e7db2b4d4340d2c1a9994a4c6277f04e19d9fb
|
| 479f83c196d5a95e36196eac548dc6019e70a5be |
19-Jul-2013 |
buzbee <buzbee@google.com> |
Dex compiler: re-enable method pattern matching
The dex compiler's mechanism to detect simple methods and emit
streamlined code was disabled during the last big restructuring
(there was a question of how to make it useful for Portable as
well as Quick). This CL does not address the Portable question,
but turns the optimization back on for Quick.
See b/9428200
Change-Id: I9f25b41219d7a243ec64efb18278e5a874766f4d
ir_graph.cc
ir_graph.h
uick/codegen_util.cc
|
| 4274889d48ef82369bf2c1ca70d84689b4f9e93a |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fixing cpplint readability/check issues
Change-Id: Ia81db7238b4a13ff2e585aaac9d5e3e91df1e3e0
ir_graph.cc
uick/arm/int_arm.cc
|
| 2d88862f0752a7a0e65145b088f49dabd49d4284 |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fixing cpplint readability/casting issues
Change-Id: I6821da0e23737995a9b884a04e9b63fac640cd05
uick/codegen_util.cc
uick/gen_invoke.cc
|
| 02c8cc6d1312a2b55533f02f6369dc7c94672f90 |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fixing cpplint whitespace/blank_line, whitespace/end_of_line, whitespace/labels, whitespace/semicolon issues
Change-Id: Ide4f8ea608338b3fed528de7582cfeb2011997b6
ir_graph.cc
ir_optimization.cc
uick/codegen_util.cc
uick/ralloc_util.cc
reg_analysis.cc
|
| 6f485c62b9cfce3ab71020c646ab9f48d9d29d6d |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/indent issues
Change-Id: I7c1647f0c39e1e065ca5820f9b79998691ba40b1
ir_graph.h
ir_optimization.cc
ortable/mir_to_gbc.cc
uick/arm/call_arm.cc
uick/arm/utility_arm.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
|
| 9b7085a4e7c40e7fa01932ea1647a4a33ac1c585 |
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint readability/braces issues
Change-Id: I56b88956510077b0e13aad4caee8898313fab55b
rena_allocator.h
rena_bit_vector.h
ackend.h
ex_to_dex_compiler.cc
rontend.cc
rowable_array.h
ocal_value_numbering.h
ir_graph.cc
uick/arm/utility_arm.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.h
|
| 38f85e4892f6504971bde994fec81fd61780ac30 |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/operators issues
Change-Id: I730bd87b476bfa36e93b42e816ef358006b69ba5
ir_dataflow.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/mips/assemble_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/ralloc_util.cc
reg_analysis.cc
|
| e3409880554bdefe8f0392e949315d234478ab8a |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am 1895ea38: Fix cpplint readability/fn_size issues
* commit '1895ea386ca78573302483f589ebabd8ce1480e7':
Fix cpplint readability/fn_size issues
|
| 1895ea386ca78573302483f589ebabd8ce1480e7 |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint readability/fn_size issues
Change-Id: I1efdb07a948a2af49db1a9d21ccab16dacc03a54
ortable/mir_to_gbc.cc
uick/mir_to_lir.cc
|
| b9070095218595a5d6a37ef874df2794c1761030 |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
resolved conflicts for merge of df62950e to dalvik-dev
Change-Id: I78fbcfc7a2dcbeccb7557ca27302928d7d00debd
|
| 08524597899d0bb021c9165218deff51dc88da50 |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am 0cd7ec2d: Fix cpplint whitespace/blank_line issues
* commit '0cd7ec2dcd8d7ba30bf3ca420b40dac52849876c':
Fix cpplint whitespace/blank_line issues
|
| df62950e7a32031b82360c407d46a37b94188fbb |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/parens issues
Change-Id: Ifc678d59a8bed24ffddde5a0e543620b17b0aba9
rena_bit_vector.h
ataflow_iterator.h
rontend.cc
ir_dataflow.cc
ir_graph.cc
ir_optimization.cc
ortable/mir_to_gbc.cc
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/utility_x86.cc
sa_transformation.cc
reg_analysis.cc
|
| 0cd7ec2dcd8d7ba30bf3ca420b40dac52849876c |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/blank_line issues
Change-Id: Ice937e95e23dd622c17054551d4ae4cebd0ef8a2
rena_allocator.h
rena_bit_vector.h
ackend.h
ataflow_iterator.h
rowable_array.h
ocal_value_numbering.cc
ocal_value_numbering.h
ir_graph.cc
ir_graph.h
ortable/mir_to_gbc.cc
ortable/mir_to_gbc.h
uick/arm/assemble_arm.cc
uick/codegen_util.cc
uick/gen_invoke.cc
uick/local_optimizations.cc
uick/mips/codegen_mips.h
uick/mir_to_lir.h
uick/x86/codegen_x86.h
sa_transformation.cc
|
| 073deb8dda59ba42ad563f0453daa09a359edef7 |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am f69863b3: Fix cpplint whitespace/newline issues
* commit 'f69863b3039fc621ff4250e262d2a024d5e79ec8':
Fix cpplint whitespace/newline issues
|
| f69863b3039fc621ff4250e262d2a024d5e79ec8 |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/newline issues
Change-Id: Ie2049d9f667339e41f36c4f5d09f0d10d8d2c762
rontend.cc
uick/codegen_util.cc
uick/mips/utility_mips.cc
|
| b267c89acd0fcda0e8e2a9eeaeeed9ee048d1abc |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am 93ba893c: Fix cpplint runtime/explicit issues
* commit '93ba893c20532990a430741e0a97212900094e8c':
Fix cpplint runtime/explicit issues
|
| 397f477582243bdffed603a73ff5a06ee295d7fb |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am b1eba213: Fix cpplint whitespace/comma issues
* commit 'b1eba213afaf7fa6445de863ddc9680ab99762ea':
Fix cpplint whitespace/comma issues
|
| 98c19d201b83119cbadd9aa3966fd0fb86064813 |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am 2ce745c0: Fix cpplint whitespace/braces issues
* commit '2ce745c06271d5223d57dbf08117b20d5b60694a':
Fix cpplint whitespace/braces issues
|
| 93ba893c20532990a430741e0a97212900094e8c |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint runtime/explicit issues
Change-Id: I352ba0b427f1ff9b22887693952b180eae0839ba
rena_allocator.h
rena_bit_vector.h
ackend.h
rowable_array.h
ocal_value_numbering.h
|
| b1eba213afaf7fa6445de863ddc9680ab99762ea |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/comma issues
Change-Id: I456fc8d80371d6dfc07e6d109b7f478c25602b65
ir_graph.cc
ir_optimization.cc
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/x86/assemble_x86.cc
uick/x86/x86_lir.h
reg_analysis.cc
|
| 2ce745c06271d5223d57dbf08117b20d5b60694a |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/braces issues
Change-Id: Ide80939faf8e8690d8842dde8133902ac725ed1a
rena_allocator.h
rena_bit_vector.cc
ataflow_iterator.h
rontend.cc
ocal_value_numbering.cc
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ortable/mir_to_gbc.cc
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/local_optimizations.cc
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/call_x86.cc
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
sa_transformation.cc
reg_analysis.cc
|
| 42425b3a8befe092199fde69c95833e31db8fec9 |
18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
am fc0e3219: Fix multiple inclusion guards to match new pathnames
* commit 'fc0e3219edc9a5bf81b166e82fd5db2796eb6a0d':
Fix multiple inclusion guards to match new pathnames
|
| fc0e3219edc9a5bf81b166e82fd5db2796eb6a0d |
17-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix multiple inclusion guards to match new pathnames
Change-Id: Id7735be1d75bc315733b1773fba45c1deb8ace43
rena_allocator.h
rena_bit_vector.h
ackend.h
ompiler_enums.h
ompiler_internals.h
ompiler_ir.h
ataflow_iterator-inl.h
ataflow_iterator.h
rontend.h
rowable_array.h
ocal_value_numbering.h
ir_graph.h
ortable/mir_to_gbc.h
uick/arm/arm_lir.h
uick/arm/codegen_arm.h
uick/mips/codegen_mips.h
uick/mips/mips_lir.h
uick/mir_to_lir-inl.h
uick/mir_to_lir.h
uick/x86/codegen_x86.h
uick/x86/x86_lir.h
|
| 543959c9ede4c09ffaf8749a612a9ac31d6dd356 |
03-Jul-2013 |
Sebastien Hertz <shertz@google.com> |
Support check-cast elision in DEX-to-DEX compiler.
Bug: 9648428
Replaces safe check-cast by 2 consecutive nop instructions.
Change-Id: I2cd99c629a6a00a6e0effc853c3439bc92683d6d
ex_to_dex_compiler.cc
|
| 7940e44f4517de5e2634a7e07d58d0fb26160513 |
12-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Create separate Android.mk for main build targets
The runtime, compiler, dex2oat, and oatdump now are in seperate trees
to prevent dependency creep. They can now be individually built
without rebuilding the rest of the art projects. dalvikvm and jdwpspy
were already this way. Builds in the art directory should behave as
before, building everything including tests.
Change-Id: Ic6b1151e5ed0f823c3dd301afd2b13eb2d8feb81
rena_allocator.cc
rena_allocator.h
rena_bit_vector.cc
rena_bit_vector.h
ackend.h
ompiler_enums.h
ompiler_internals.h
ompiler_ir.h
ataflow_iterator-inl.h
ataflow_iterator.h
ex_to_dex_compiler.cc
rontend.cc
rontend.h
rowable_array.h
ocal_value_numbering.cc
ocal_value_numbering.h
ir_dataflow.cc
ir_graph.cc
ir_graph.h
ir_optimization.cc
ortable/mir_to_gbc.cc
ortable/mir_to_gbc.h
uick/arm/arm_lir.h
uick/arm/assemble_arm.cc
uick/arm/call_arm.cc
uick/arm/codegen_arm.h
uick/arm/fp_arm.cc
uick/arm/int_arm.cc
uick/arm/target_arm.cc
uick/arm/utility_arm.cc
uick/codegen_util.cc
uick/gen_common.cc
uick/gen_invoke.cc
uick/gen_loadstore.cc
uick/local_optimizations.cc
uick/mips/README.mips
uick/mips/assemble_mips.cc
uick/mips/call_mips.cc
uick/mips/codegen_mips.h
uick/mips/fp_mips.cc
uick/mips/int_mips.cc
uick/mips/mips_lir.h
uick/mips/target_mips.cc
uick/mips/utility_mips.cc
uick/mir_to_lir-inl.h
uick/mir_to_lir.cc
uick/mir_to_lir.h
uick/ralloc_util.cc
uick/x86/assemble_x86.cc
uick/x86/call_x86.cc
uick/x86/codegen_x86.h
uick/x86/fp_x86.cc
uick/x86/int_x86.cc
uick/x86/target_x86.cc
uick/x86/utility_x86.cc
uick/x86/x86_lir.h
sa_transformation.cc
reg_analysis.cc
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