| 968056faf5c2cf118321871ebf234fe70db1c3c8 |
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29-Mar-2016 |
Aart Bik <ajcbik@google.com> |
Fix arm64 simplifier bug that tries to remove same statement twice.
With fail-before/pass-after test (on arm64).
Rationale:
This visitor removes statement "forward", which is a bit unusual, and
exposes a bug if statement is revisited and qualifies for removal again.
BUG=27851582
Change-Id: Ia8cddba32b4dfe9fd480852deb358eaa977f0e1f
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| 7fc6350f6f1ab04b52b9cd7542e0790528296cbe |
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09-Feb-2016 |
Artem Serov <artem.serov@linaro.org> |
Integrate BitwiseNegated into shared framework.
Share implementation between arm and arm64.
Change-Id: I0dd12e772cb23b4c181fd0b1e2a447470b1d8702
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| 9ff0d205fd60cba6753a91f613b198ca2d67f04d |
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11-Jan-2016 |
Kevin Brodsky <kevin.brodsky@linaro.org> |
Optimizing: ARM64 negated bitwise operations simplification
Use negated instructions on ARM64 to replace [bitwise operation + not]
patterns, that is:
a & ~b (BIC)
a | ~b (ORN)
a ^ ~b (EON)
The simplification only happens if the Not is only used by the bitwise
operation. It does not happen if both inputs are Not's (this should be
handled by a generic simplification applying De Morgan's laws).
Change-Id: I0e112b23fd8b8e10f09bfeff5994508a8ff96e9c
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| 4a0dad67867f389e01a5a6c0fe381d210f687c0d |
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25-Jan-2016 |
Artem Udovichenko <artem.u@samsung.com> |
Revert "Revert "ARM/ARM64: Extend support of instruction combining.""
This reverts commit 6b5afdd144d2bb3bf994240797834b5666b2cf98.
Change-Id: Ic27a10f02e21109503edd64e6d73d1bb0c6a8ac6
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| 6b5afdd144d2bb3bf994240797834b5666b2cf98 |
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22-Jan-2016 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "ARM/ARM64: Extend support of instruction combining."
The test fails its checker parts.
This reverts commit debeb98aaa8950caf1a19df490f2ac9bf563075b.
Change-Id: I49929e15950c7814da6c411ecd2b640d12de80df
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| debeb98aaa8950caf1a19df490f2ac9bf563075b |
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11-Dec-2015 |
Ilmir Usmanov <i.usmanov@samsung.com> |
ARM/ARM64: Extend support of instruction combining.
Combine multiply instructions in the following way:
ARM64:
MUL/NEG -> MNEG
ARM32 (32-bit integers only):
MUL/ADD -> MLA
MUL/SUB -> MLS
Change-Id: If20f2d8fb060145ab6fbceeb5a8f1a3d02e0ecdb
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| 8626b741716390a0119ffeb88b5b9fcf08e13010 |
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25-Nov-2015 |
Alexandre Rames <alexandre.rames@linaro.org> |
ARM64: Use the shifter operands.
This introduces architecture-specific instruction simplification.
On ARM64 we try to merge shifts and sign-extension operations into
arithmetic and logical instructions.
For example for the Java code
int res = a + (b << 5);
we would generate
lsl w3, w2, #5
add w0, w1, w3
and we now generate
add w0, w1, w2, lsl #5
Change-Id: Ic03bdff44a1c12e21ddff1b0513bd32a730742b7
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| 418318f4d50e0cfc2d54330d7623ee030d4d727d |
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20-Nov-2015 |
Alexandre Rames <alexandre.rames@linaro.org> |
ARM64: Add support for multiply-accumulate.
Change-Id: I88dc313df520480f3fd16bbabda27f9435d25368
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| e6dbf48d7a549e58a3d798bbbdc391e4d091b432 |
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19-Oct-2015 |
Alexandre Rames <alexandre.rames@linaro.org> |
ARM64: Instruction simplification for array accesses.
HArrayGet and HArraySet with variable indexes generate two
instructions on arm64, like
add temp, obj, #data_offset
ldr out, [temp, index LSL #shift_amount]
When we have multiple accesses to the same array, the initial `add`
instruction is redundant.
This patch introduces the first instruction simplification in the
arm64-specific instruction simplification pass. It splits HArrayGet
and HArraySet using the new arm64-specific IR HIntermediateAddress.
After that we run GVN again to squash the multiple occurrences of
HIntermediateAddress.
Change-Id: I2e3d12fbb07fed07b2cb2f3f47f99f5a032f8312
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| 44b9cf937836bb33139123e15ca8b586b5853268 |
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19-Aug-2015 |
Alexandre Rames <alexandre.rames@linaro.org> |
Put in place the ARM64 instruction simplification framework.
This commit introduces and runs the empty InstructionSimplifierArm64
pass. Further commits will introduce arm64-specific transformations in
that pass.
Change-Id: I458f8a2b15470297b87fc1f7ff85bd52155d93ef
|