| c257da7b0fb6737f65aba426add8831e45404755 |
|
02-Feb-2016 |
Artem Serov <artem.serov@linaro.org> |
ARM: Implement Reverse bits and bytes intrinsic.
- IntegerReverse
- LongReverse
- IntegerReverseBytes
- LongReverseBytes
- ShortReverseBytes
Change-Id: I3ec202696b245148a0237ff6e46ac3f1a3f8402a
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| f5c09c3ed5bca4c34d8476dd9ed2714106fafbcf |
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17-Dec-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing/ARM: Fix AddConstant() to adhere to set_cc.
And improve it to use shorter code sequences.
Bug: 26121945
Change-Id: Ia4f1688652c195a7ca19af36d919388a550e2841
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| 7cffc3b0004d32faffc552c0a59286f369b21504 |
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20-Oct-2015 |
Andreas Gampe <agampe@google.com> |
ART: Arm32 packed-switch jump tables
Add jump table support to the thumb2 assembler. Jump tables are
a collection of labels for the case targets, and an anchor label
denoting the position of the jump.
Use the jump table support to implement packed-switch support for
arm32.
Add tests for BindTrackedLabel and JumpTable to the thumb2 assembler
test.
Bug: 24092914
Change-Id: I5c84f193dfebf9e07f48678efc8bd151bb1410dd
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| d2b4ca2d02c86b1ce1826fd2b35ce6c9c58c1ff1 |
|
14-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
Improve Thumb2 bitwise operations.
Allow embedding constants in AND, ORR, EOR. Add ORN to
assembler, use BIC and ORN for AND and ORR when needed.
Change-Id: I24d69ecc7ce6992b9c5eb7a313ff47a942de9661
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| 5bd05a5c9492189ec28edaf6396d6a39ddf03367 |
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13-Oct-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement System.arraycopy intrinsic for arm.
Change-Id: I58ae1af5103e281fe59fbe022b718d6d8f293a5e
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| 9ee23f4273efed8d6378f6ad8e63c65e30a17139 |
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23-Jul-2015 |
Scott Wakeling <scott.wakeling@linaro.org> |
ARM/ARM64: Intrinsics - numberOfTrailingZeros, rotateLeft, rotateRight
Change-Id: I2a07c279756ee804fb7c129416bdc4a3962e93ed
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| 449b10922daacc880374d7862dbb5977c7657f6d |
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08-Sep-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Clean up Thumb2Assembler's AddConstant().
Change-Id: I6a4c32d1bba79879e5514059df6336dc331246c1
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| 73cf0fb75de2a449ce4fe329b5f1fb42eef1372f |
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30-Jul-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Add 16-bit Thumb2 ROR, NEGS and CMP for high registers.
Also clean up the usage of set_cc flag. Define a SetCc
enumeration that specifies whether to set or keep condition
codes or whether we don't care and a 16-bit instruction
should be selected if one exists.
This reduces the size of Nexus 5 boot.oat by 44KiB (when
compiled with Optimizing which is not the default yet).
Change-Id: I047072dc197ea678bf2019c01bcb28943fa9b604
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| cf93a5cd9c978f59113d42f9f642fab5e2cc8877 |
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16-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "Revert "ART: Implement literal pool for arm, fix branch fixup.""
This reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98.
Adjust block label positions. Bad catch block labels were the
reason for the revert.
Change-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310
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| fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98 |
|
16-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "ART: Implement literal pool for arm, fix branch fixup."
This reverts commit f38caa68cce551fb153dff37d01db518e58ed00f.
Change-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40
Reason: broke the tests.
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| f38caa68cce551fb153dff37d01db518e58ed00f |
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29-May-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Implement literal pool for arm, fix branch fixup.
Change-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7
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| 41b175aba41c9365a1c53b8a1afbd17129c87c14 |
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19-May-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Clean up arm64 kNumberOfXRegisters usage.
Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.
Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.
Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.
Bug: 13925192
(cherry picked from commit 80afd02024d20e60b197d3adfbb43cc303cf29e0)
Change-Id: I905257a21de90b5860ebe1e39563758f721eab82
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| 80afd02024d20e60b197d3adfbb43cc303cf29e0 |
|
19-May-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Clean up arm64 kNumberOfXRegisters usage.
Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.
Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.
Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.
Bug: 13925192
Change-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7
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| c66671076b12a0ee8b9d1ae782732cc91beacb73 |
|
15-May-2015 |
Zheng Xu <zheng.xu@arm.com> |
Opt compiler: Speedup div/rem by constants on arm32 and arm64.
This patch also includes:
1. Add java test for div/rem negative constants.
2. Fix a thumb2 encoding issue where the last operand is
"reg, shift #amount" in some instructions.
3. Support a simple filter in arm32 assembler test to filter out
unsupported cases, such as "smull r0, r0, r1, r2".
4. Add smull arm32 assembler test.
5. Add smull/umull thumb2 test.
6. Add test for the thumb2 encoding issue which is fixed in this
patch.
Change-Id: I1601bc9c38f70f11909f2816fe3ec105a158951e
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| ab1eb0d1d047e3478ebb891e5259d2f1d1dd78bd |
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14-Feb-2015 |
Andreas Gampe <agampe@google.com> |
ART: Templatize IsInt & IsUint
Ensure that things are used correctly.
Change-Id: I76f082b32dcee28bbfb4c519daa401ac595873b3
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| 52c489645b6e9ae33623f1ec24143cde5444906e |
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16-Dec-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add support for volatile
- for backends: arm, x86, x86_64
- added necessary instructions to assemblies
- clean up code gen for field set/get
- fixed InstructionDataEquals for some instructions
- fixed comments in compiler_enums
* 003-opcode test verifies basic volatile functionality
Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
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| 3bcc8ea079d867f26622defd0611d134a3b4ae49 |
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28-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Don't use CanHoldArm in the code generator.
CanHoldArm was ARM32 specific. Instead use a virtual
Assembler::ShifterOperandCanHold that both thumb2 and arm32
implement.
Change-Id: I33794a93caf02ee5d78d32a8471d9fd6fe4f0a00
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| 9aec02fc5df5518c16f1e5a9b6cb198a192db973 |
|
19-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add shifts
Added SHL, SHR, USHR for arm, x86, x86_64.
Change-Id: I971f594e270179457e6958acf1401ff7630df07e
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| 8366ca0d7ba3b80a2d5be65ba436446cc32440bd |
|
17-Nov-2014 |
Elliott Hughes <enh@google.com> |
Fix the last users of TARGET_CPU_SMP.
Everyone else assumes SMP.
Change-Id: I7ff7faef46fbec6c67d6e446812d599e473cba39
|
| 981e45424f52735b1c61ae0eac7e299ed313f8db |
|
14-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-char in the optimizing compiler.
- Add support for the int-to-char Dex instruction in the
optimizing compiler.
- Implement the ARM and Thumb-2 UBFX instructions and add
tests for them.
- Generate x86, x86-64 and ARM (but not ARM64) code for
byte to char, short to char, int to char (and char to
char!) HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: I5cd4c6d86f0f6a966c059715b98db35cc8f9de76
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| 51d3fc40637fc73d4156ad617cd451b844cbb75e |
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13-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-byte in the optimizing compiler.
- Add support for the int-to-byte Dex instruction in the
optimizing compiler.
- Implement the ARM and Thumb-2 SBFX instructions.
- Generate x86, x86-64 and ARM (but not ARM64) code for
char to byte, short to byte and int to byte
HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: Ic8b8911b90d4b5281fad15bcee96bc3ee85dc577
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| 6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f |
|
31-Oct-2014 |
Ian Rogers <irogers@google.com> |
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.
Fix associated errors about unused paramenters and implict sign conversions.
For sign conversion this was largely in the area of enums, so add ostream
operators for the effected enums and fix tools/generate-operator-out.py.
Tidy arena allocation code and arena allocated data types, rather than fixing
new and delete operators.
Remove dead code.
Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
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| 19a19cffd197a28ae4c9c3e59eff6352fd392241 |
|
22-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for static fields in optimizing compiler.
Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
|
| 2c4257be8191c5eefde744e8965fcefc80a0a97d |
|
24-Oct-2014 |
Ian Rogers <irogers@google.com> |
Tidy logging code not using UNIMPLEMENTED.
Change-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe
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| c8ccf68b805c92674545f63e0341ba47e8d9701c |
|
30-Sep-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix some -Wpedantic errors
Remove extra semicolons.
Dollar signs in C++ identifiers are an extension.
Named variadic macros are an extension.
Binary literals are a C++14 feature.
Enum re-declarations are not allowed.
Overflow.
Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
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| 45fdb93f04b981f70f7b6d98949ab3986b7331f8 |
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25-Jun-2014 |
Dave Allison <dallison@google.com> |
Support additional instructions in ARM and thumb assemblers
This adds the following support for the ARM and thumb assemblers:
1. Shifting by a register.
2. LDR/STR with a register offset, possibly shifted.
3. LDR(literal).
4. STR PC relative.
Also adds tests for them in the thumb assembler gtest.
Change-Id: Ie467e3c1d06b699cacbdef3482ed9a92e4f1809b
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| 65fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7 |
|
28-Apr-2014 |
Dave Allison <dallison@google.com> |
Thumb2 assembler for JNI compiler and optimizing compiler
This provides a programmatic assembler for the thumb2 instruction set for
ARM. The interface is the same as the ARM assembler and the ARM assembler has
been moved into Arm32Assembler. The assembler handles most 16 and 32 bit instructions
and also allows relocations due to branch expansion. It will also rewrite cbz/cbnz
instructions if they go out of range.
It also changes the JNI compiler to use the thumb2 assembler as opposed
to forcing it to use ARM32. The trampoline compiler still uses ARM due to the
way it returns the address of its generated code. A trampoline in thumb2 is the
same size as that in ARM anyway (8 bytes).
Provides gtest for testing the thumb2 instruction output. This gtest only runs
on the host as it uses arm-eabi-objdump to disassemble the generated code. On the
target the output is not checked but the assembler will still be run to perform
all its checks.
Change-Id: Icd9742b6f13541bec5b23097896727392e3a6fb6
|