| f2bb04304ab545ecef67fc6b8708e3ad41a6005f |
|
25-Apr-2016 |
Vladimir Marko <vmarko@google.com> |
Thumb2: Reduce memory used for fixup dependencies.
Mark fixups for far backward branches as 32-bit from the
beginning and ignore their dependencies since they cannot
be expanded anymore. This reduces the memory used by the
fixup_dependents_ when compiling methods with a lot of
slow paths.
Bug: 28256882
This is a cherry-pick of the fixed revert-revert
Revert "Revert "Thumb2: Reduce memory used for fixup dependencies.""
(cherry picked from commit a64f249add4a0a9e93aa6f246045ca79f5916dcd)
Change-Id: I9ca766b73d9f5a1da5dc10ad070145ac88fbcd53
|
| c257da7b0fb6737f65aba426add8831e45404755 |
|
02-Feb-2016 |
Artem Serov <artem.serov@linaro.org> |
ARM: Implement Reverse bits and bytes intrinsic.
- IntegerReverse
- LongReverse
- IntegerReverseBytes
- LongReverseBytes
- ShortReverseBytes
Change-Id: I3ec202696b245148a0237ff6e46ac3f1a3f8402a
|
| 6fd0ffe8da212723a3ac0256ce350b5872cc61d4 |
|
19-Nov-2015 |
Vladimir Marko <vmarko@google.com> |
Optimizing/Thumb2: Improve load/store for large offsets.
This reduces the boot.oat size on Nexus 5 by 568KiB (0.8%).
Also change 32-bit ADD/SUB immediate to use the recommended
encoding T3 when both T3 and T4 are available.
Change-Id: I174382bda2b22da70560b947f5536acf8c1814a9
|
| 7cffc3b0004d32faffc552c0a59286f369b21504 |
|
20-Oct-2015 |
Andreas Gampe <agampe@google.com> |
ART: Arm32 packed-switch jump tables
Add jump table support to the thumb2 assembler. Jump tables are
a collection of labels for the case targets, and an anchor label
denoting the position of the jump.
Use the jump table support to implement packed-switch support for
arm32.
Add tests for BindTrackedLabel and JumpTable to the thumb2 assembler
test.
Bug: 24092914
Change-Id: I5c84f193dfebf9e07f48678efc8bd151bb1410dd
|
| 9ee23f4273efed8d6378f6ad8e63c65e30a17139 |
|
23-Jul-2015 |
Scott Wakeling <scott.wakeling@linaro.org> |
ARM/ARM64: Intrinsics - numberOfTrailingZeros, rotateLeft, rotateRight
Change-Id: I2a07c279756ee804fb7c129416bdc4a3962e93ed
|
| 611d3395e9efc0ab8dbfa4a197fa022fbd8c7204 |
|
10-Jul-2015 |
Scott Wakeling <scott.wakeling@linaro.org> |
ARM/ARM64: Implement numberOfLeadingZeros intrinsic.
Change-Id: I4042fb7a0b75140475dcfca23e8f79d310f5333b
|
| 663c93448e50599d411b2403585b90513dbf8e3a |
|
22-Jul-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Fix Thumb2 literal fixup.
When processing a load literal during fixup, we use the
current code size to determine whether we need to add the
padding before literals. However, this may change by the end
of the fixup, yet we didn't recalculate to see if the load
literal is pushed out of range.
Instead of making the load literal fixup also depend on all
preceding fixups, add an extra pass over literals when we
need the padding and repeat the fixup loop if needed.
Change-Id: Ia21d660486167a2dcb1ad4afe8acc669b4af669d
|
| cf93a5cd9c978f59113d42f9f642fab5e2cc8877 |
|
16-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "Revert "ART: Implement literal pool for arm, fix branch fixup.""
This reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98.
Adjust block label positions. Bad catch block labels were the
reason for the revert.
Change-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310
|
| fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98 |
|
16-Jun-2015 |
Vladimir Marko <vmarko@google.com> |
Revert "ART: Implement literal pool for arm, fix branch fixup."
This reverts commit f38caa68cce551fb153dff37d01db518e58ed00f.
Change-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40
Reason: broke the tests.
|
| f38caa68cce551fb153dff37d01db518e58ed00f |
|
29-May-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Implement literal pool for arm, fix branch fixup.
Change-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7
|
| c66671076b12a0ee8b9d1ae782732cc91beacb73 |
|
15-May-2015 |
Zheng Xu <zheng.xu@arm.com> |
Opt compiler: Speedup div/rem by constants on arm32 and arm64.
This patch also includes:
1. Add java test for div/rem negative constants.
2. Fix a thumb2 encoding issue where the last operand is
"reg, shift #amount" in some instructions.
3. Support a simple filter in arm32 assembler test to filter out
unsupported cases, such as "smull r0, r0, r1, r2".
4. Add smull arm32 assembler test.
5. Add smull/umull thumb2 test.
6. Add test for the thumb2 encoding issue which is fixed in this
patch.
Change-Id: I1601bc9c38f70f11909f2816fe3ec105a158951e
|
| 4af147eb3296a26eea566f53a7f687194638d46b |
|
07-Apr-2015 |
Roland Levillain <rpl@google.com> |
Exercise art::arm::Thumb2Assembler::StoreToOffset for word pairs.
- Augment compiler/utils/arm/assembler_thumb2_test.cc.
- Ensure art::arm::Thumb2Assembler::StoreToOffset properly
handles IP as (implicit) second source register.
- Remove the parity constraint on the first source register
for art::arm::Thumb2Assembler::ldrd and
art::arm::Thumb2Assembler::strd (as they are not required
by the Thumb-2 encoding).
- Introduce additional versions of
art::arm::Thumb2Assembler::ldrd and
art::arm::Thumb2Assembler::strd accepting a second source
register, which is not necessarily the one following the
first source register, as it is allowed by the Thumb-2
encoding.
Change-Id: I7dba168437a96a5cbb117058e9c547fb1ff5c295
|
| c5a5ac641eb4b32fa6737c390813ce78c66a12d3 |
|
02-Apr-2015 |
Roland Levillain <rpl@google.com> |
Exercise art::arm::Thumb2Assembler::StoreToOffset for words.
Change-Id: Ifa82e69c055eb99e526fc7ab5db54bde988d2caf
|
| dc62c48937a6476ed9c0d739f6b3b5c26f758371 |
|
11-Mar-2015 |
Guillaume "Vermeille" Sanchez <guillaumesa@google.com> |
Make subs and adds alter flags when rn is an immediate
Change-Id: I70e0d78f155bf806222ad12a324dbd8c8fe575a1
|
| 2dae78cbd4394a4498a845c6943992b57bd07b6e |
|
17-Mar-2015 |
Calin Juravle <calin@google.com> |
Revert "Make subs alter flags when rn is an immediate"
This reverts commit 8de00e3f5fcb99bfd7e4dc679ab7333549bec2c1.
Change-Id: Ie9da31279f565f165d51d8c0036928377280e3b8
|
| 8de00e3f5fcb99bfd7e4dc679ab7333549bec2c1 |
|
11-Mar-2015 |
Guillaume "Vermeille" Sanchez <guillaumesa@google.com> |
Make subs alter flags when rn is an immediate
Change-Id: I7ea84fca5f97713871744b8ac4265a84fd6a5248
|
| 2bcf9bf784a0021630d8fe63d7230d46d6891780 |
|
29-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Arm intrinsics for Optimizing compiler
Add arm32 intrinsics to the optimizing compiler.
Change-Id: If4aeedbf560862074d8ee08ca4484b666d6b9bf0
|
| 513ea0c203a86e9d81a8630b56cb62704e126cc2 |
|
02-Feb-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix thumb2 utils assembler
It didn't correctly put down the 16b variants, as it was not
checking the ShifterOperand correctly.
Add one simple test. TODO: exhaustive testing.
Change-Id: Ied08da115f8417a3ca92bd9967c6dcdc102e7510
|
| 52c489645b6e9ae33623f1ec24143cde5444906e |
|
16-Dec-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add support for volatile
- for backends: arm, x86, x86_64
- added necessary instructions to assemblies
- clean up code gen for field set/get
- fixed InstructionDataEquals for some instructions
- fixed comments in compiler_enums
* 003-opcode test verifies basic volatile functionality
Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
|
| ddb7df25af45d7cd19ed1138e537973735cc78a5 |
|
25-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}
Adds:
- float comparison for arm, x86, x86_64 backends.
- ucomis{s,d} assembly to x86 and x86_64.
- vmstat assebmly for thumb2
- new assembly tests
Change-Id: Ie3e19d0c08b3b875cd0a4be4ee4e9c8a4a076290
|
| 981e45424f52735b1c61ae0eac7e299ed313f8db |
|
14-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-char in the optimizing compiler.
- Add support for the int-to-char Dex instruction in the
optimizing compiler.
- Implement the ARM and Thumb-2 UBFX instructions and add
tests for them.
- Generate x86, x86-64 and ARM (but not ARM64) code for
byte to char, short to char, int to char (and char to
char!) HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: I5cd4c6d86f0f6a966c059715b98db35cc8f9de76
|
| 851df20225593b10e698a760ac3cd5243620700b |
|
12-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: Multiview assembler_test, fix x86-64 assembler
Expose "secondary" names for registers so it is possible to test
32b views for 64b architectures.
Add floating-point register testing.
Refactor assembler_test for better code reuse (and simpler adding
of combination drivers).
Fix movss, movsd (MR instead of RM encoding), xchgl, xchgq,
both versions of EmitGenericShift.
Tighten imull(Reg,Imm), imulq(Reg,Imm), xchgl and xchgq encoding.
Clarify cv*** variants with a comment.
Add tests for movl, addl, imull, imuli, mull, subl, cmpqi, cmpl,
xorq (regs), xorl, movss, movsd, addss, addsd, subss, subsd, mulss,
mulsd, divss, divsd, cvtsi2ss, cvtsi2sd, cvtss2si, cvtss2sd, cvtsd2si,
cvttss2si, cvttsd2si, cvtsd2ss, cvtdq2pd, comiss, comisd, sqrtss,
sqrtsd, xorps, xorpd, fincstp, fsin, fcos, fptan, xchgl (disabled,
see code comment), xchgq, testl, andl, andq, orl, orq, shll, shrl,
sarl, negq, negl, notq, notl, enter and leave, call, ret, and jmp,
and make some older ones more exhaustive.
Follow-up TODOs:
1) Support memory (Address).
2) Support tertiary and quaternary register views.
Bug: 18117217
Change-Id: I1d583a3bec552e3cc7c315925e1e006f393ab687
|
| 1a28fc43ea7daa624ada9af40e30de64d4e946a8 |
|
13-Nov-2014 |
Roland Levillain <rpl@google.com> |
Exercise the generation of SBFX on ARM32 & Thumb-2.
Exercise the generation of the ARM SBFX intruction in
compiler/utils/arm/assembler_arm32_test.cc (ARM
instruction set encoding) and in
compiler/utils/arm/assembler_thumb2_test.cc (Thumb
instruction set encoding).
Change-Id: Ic72683aac6dd6628e227523e352c395e1a63b52e
|