51aff3a6564303cab0b7ac82495b4e2e349c6ff3 |
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18-Mar-2016 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS32: Implement UnsafeCASInt and UnsafeCASObject intrinsics. Change-Id: Ie871763b9a36075fd3d70ee6e2e241ae1ccc36cf
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3acee732f9475fbfc6b046e0044b764e7ff5ac01 |
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18-Nov-2015 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS32: peek*/poke*, and String.charAt intrinsics. - byte libcore.io.Memory.peekByte(long address) - short libcore.io.Memory.peekShort(long address) - int libcore.io.Memory.peekInt(long address) - long libcore.io.Memory.peekLong(long address) - void libcore.io.Memory.pokeByte(long address, byte value) - void libcore.io.Memory.pokeShort(long address, short value) - void libcore.io.Memory.pokeInt(long address, int value) - void libcore.io.Memory.pokeLong(long address, long value) - char java.lang.String.charAt(int index) Change-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa
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92d9060c0cdff7c726549a9d9494e5655404bed7 |
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19-Dec-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS: Implement HRor This also fixes differentiation between the SRL and ROTR instructions in the disassembler. Change-Id: Ie19697f8d6ea8fa4e338adde3e3cf8e4a0383eae
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5c7aed3b9844e240cf785e5885524ac133a04396 |
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26-Nov-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS32: improvements in code generation (mostly 64-bit ALU ops) Specifically: - Use the delay slot in InvokeRuntime() for direct entry points - Use kNoOutputOverlap wherever possible - Improve and/or/xor/add/sub with 64-bit integer constants - Improve 64-bit shifts by a constant amount on R2+ - More efficient load/store of 64-bit constants (especially, 0 & +0.0) Change-Id: I86d2217c8b5b8e2a9371effc2ce38b9eec62782b
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cd7b0ee296b0462961c63e51d99c9c323e2690df |
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04-Dec-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS32: Fuse long and FP compare & condition in Optimizing. This also does a minor clean-up in the assembler and its test. Bug: 25559148 Change-Id: I9bad3c500b592a09013b56745f70752eb284a842
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e384547851a9d9e5d89ae5bb4c16bfd7d93cc12e |
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18-Nov-2015 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS32: int java.lang.*.numberOfLeadingZeros - int java.lang.Integer.numberOfLeadingZeros(int) - int java.lang.Long.numberOfLeadingZeros(long) Change-Id: Icaf746cb807863f944ff4ebb5da6e6b2846eac58
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7d4152f3520a3899ab57b61b884a17a2ba49a2ad |
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20-Oct-2015 |
Chris Larsen <chris.larsen@imgtec.com> |
MIPS64: Disassembler support for rotate instructions. Also, tighten the tests for recognizing the various shift commands. The tests, previously, would be unable to distinguish between "shift right logical" and "rotate right" commands. In particular: - SRLV vs. ROTRV - DSRLV vs. DROTRV, - DSRL vs. DROTR, and - DSRL32 vs. DROTR32 Change-Id: I7a6df8ab0d76fd3d34b1207da9915369ad84fa97
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8c434dcc78d497e18590461700894d1c3e96013d |
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26-Aug-2015 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
MIPS: Assemblers changes needed for optimizing compiler Also add assembler tests for MIPS32. Change-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775
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2fadd7bb67abf5bc3c5370f9508cfb5959d6e536 |
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14-Aug-2015 |
Chris Larsen <chris.larsen@imgtec.com> |
Additional MIPS64 instructions needed by intrinsics code. Change-Id: If2a48300aac7a10dadf485d1765fb5bdeed975fe
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a1935c4fa255b5c20f5e9b2abce6be2d0f7cb0a8 |
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26-Jun-2015 |
Roland Levillain <rpl@google.com> |
MIPS: Initial version of optimizing compiler for MIPS64R6. (cherry picked from commit 4dda3376b71209fae07f5c3c8ac3eb4b54207aa8) (amended for mnc-dev) Bug: 21555893 Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com> Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
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4dda3376b71209fae07f5c3c8ac3eb4b54207aa8 |
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02-Jun-2015 |
Alexey Frunze <Alexey.Frunze@imgtec.com> |
MIPS: Initial version of optimizing compiler for MIPS64R6. Bug: 21555893 Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com> Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
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403e0d55a3e9c18d4228d0aab31dec0c908dc73d |
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08-Apr-2015 |
Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> |
[MIPS] Refactoring code for disassembler Code for mips64 is merged with code for mips. Change-Id: I2e3f2118c69a189787ae8e7f09adb4ee5c0d00d9
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65b798ea10dd716c1bb3dda029f9bf255435af72 |
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06-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Enable more Clang warnings Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
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027f0ff64c2512b9a5f1f54f3fea1bec481eb0f5 |
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28-Feb-2015 |
Douglas Leung <douglas.leung@imgtec.com> |
ART: Add Mips32r6 backend support Add Mips32r6 compiler support. Don't use deprecated Mips32r2 instructions if running in Mips32r6 mode. Change-Id: I54e689aa8c026ccb75c4af515aa2794f471c9f67
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1cd27903529ee10229fa639dc8438a75517de492 |
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14-Feb-2015 |
Douglas Leung <douglas.leung@imgtec.com> |
ART: Fix Mips disassembler for some floating point instructions. Change-Id: I2b661a8dae4cd924c081df85f570007cf645769c
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8d36591d93920e7b7830c3ffee3759b561f5339e |
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13-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Use jalr instead of jr for Mips Use the jalr instruction instead of jr in stubs and compiled code. Change-Id: Idacc5167a5bb0113dc2e7716e4767e5ed07b5e0b
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cf7f19135f0e273f7b0136315633c2abfc715343 |
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23-Oct-2014 |
Ian Rogers <irogers@google.com> |
C++11 related clean-up of DISALLOW_.. Move DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations with no definitions this prompts better warning messages so deal with these by correcting the code. Add a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object. Make X86 assembly operand types ValueObjects to fix compilation errors. Tidy the use of iostream and ostream. Avoid making cutils a dependency via mutex-inl.h for tests that link against libart. Push tracing dependencies into appropriate files and mutex.cc. x86 32-bit host symbols size is increased for libarttest, avoid copying this in run-test 115 by using symlinks and remove this test's higher than normal ulimit. Fix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it returns NULL when the heap is under construction by Runtime. Change-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b
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c7dd295a4e0cc1d15c0c96088e55a85389bade74 |
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22-Oct-2014 |
Ian Rogers <irogers@google.com> |
Tidy up logging. Move gVerboseMethods to CompilerOptions. Now "--verbose-methods=" option to dex2oat rather than runtime argument "-verbose-methods:". Move ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc except for a forward declaration. Remove ConstDumpable as Dump methods are all const (and make this so if not currently true). Make LogSeverity an enum and improve compile time assertions and type checking. Remove log_severity.h that's only used in logging.h. With system headers gone from logging.h, go add to .cc files missing system header includes. Also, make operator new in ValueObject private for compile time instantiation checking. Change-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641
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2cbaccb67e22c0b313a9785bfc65bcb4b25d0676 |
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15-Sep-2014 |
Brian Carlstrom <bdc@google.com> |
Avoid printing absolute addresses in oatdump - Added printing of OatClass offsets. - Added printing of OatMethod offsets. - Added bounds checks for code size size, code size, mapping table, gc map, vmap table. - Added sanity check of 100k for code size. - Added partial disassembly of questionable code. - Added --no-disassemble to disable disassembly. - Added --no-dump:vmap to disable vmap dumping. - Reordered OatMethod info to be in file order. Bug: 15567083 (cherry picked from commit 34fa79ece5b3a1940d412cd94dbdcc4225aae72f) Change-Id: I2c368f3b81af53b735149a866f3e491c9ac33fb8
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34fa79ece5b3a1940d412cd94dbdcc4225aae72f |
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15-Sep-2014 |
Brian Carlstrom <bdc@google.com> |
Avoid printing absolute addresses in oatdump - Added printing of OatClass offsets. - Added printing of OatMethod offsets. - Added bounds checks for code size size, code size, mapping table, gc map, vmap table. - Added sanity check of 100k for code size. - Added partial disassembly of questionable code. - Added --no-disassemble to disable disassembly. - Added --no-dump:vmap to disable vmap dumping. - Reordered OatMethod info to be in file order. Bug: 15567083 Change-Id: Id86a21e06d4a28f29f16fd018cba7e55c57f849a
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dd7624d2b9e599d57762d12031b10b89defc9807 |
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15-Mar-2014 |
Ian Rogers <irogers@google.com> |
Allow mixing of thread offsets between 32 and 64bit architectures. Begin a more full implementation x86-64 REX prefixes. Doesn't implement 64bit thread offset support for the JNI compiler. Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
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38e12034f1ef2b32e98b6e49cb36b7cc37a7f1be |
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14-Mar-2014 |
Ian Rogers <irogers@google.com> |
x86-64 disassembler support. Change-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0
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02ed4c04468ca5f5540c5b704ac3e2f30eb9e8f4 |
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06-Sep-2013 |
Ian Rogers <irogers@google.com> |
Move disassembler out of runtime. Bug: 9877500. Change-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29
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