History log of /external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
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cddc3e03e4ec99c0268c03a126195173e519ed58 04-Mar-2016 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r256229

http://b/26987366

(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)

Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
6948897e478cbd66626159776a8017b3c18579b9 01-Jul-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r239765

Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.

Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
0c7f116bb6950ef819323d855415b2f2b0aad987 06-May-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r235153

Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
4c5e43da7792f75567b693105cc53e3f1992ad98 08-Apr-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master llvm for rebase to r233350

Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
ebe69fe11e48d322045d5949c83283927a0d790b 23-Mar-2015 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r230699.

Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
37ed9c199ca639565f6ce88105f9e39e898d82d0 01-Dec-2014 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r222494.

Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
c6a4f5e819217e1e12c458aed8e7b122e23a3a58 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
23427207ea575f57b571cf5aad1effb1f97e7ee1 18-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code for (ConstantFP 0.0)

Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64
which resulted in an impossible constraint on the register allocation. It now
uses BuildPairF64_64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
bb47fd04c9b1616c0371eb2c488c5f0f665c25f8 12-Nov-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
6ff1ef9931b50763a40e9ae8696cfab9e25cf4de 30-Oct-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics)

This required correcting the definition of the bins[lr]i intrinsics because
the result is also the first operand.

It also required removing the (arbitrary) check for 32-bit immediates in
MipsSEDAGToDAGISel::selectVSplat().

Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d
because the constant is legalized into a ConstantPool. Similar things can
happen with binsri.d with more than 10 bits set in the mask. The resulting
code when this happens is correct but not optimal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
2ef99c5dff1ab9612f2d65e38f725d809672d2fd 15-Oct-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Define a pseudo instruction which writes to both the lower and higher
parts of the accumulators and gets expanded post-RA.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
adb1297d49dd345821d7aa91057a0b22e6209a16 15-Oct-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename isel nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
c8a1fa77a73e7c885035421712ceba951f9024cb 27-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)

Updated some of the vshf since they (correctly) emit splati's now



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
acfa5a203c01d99aac1bdc1e045c08153bcdbbf6 24-Sep-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR.

Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp

This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).

There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.

compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
906ae15d5fa5784595273228b33e16ca16a0431d 13-Sep-2013 Zoran Jovanovic <zoran.jovanovic@imgtec.com> Test commit to verify that commit access works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
2fd3e67dc6438cee5e32e0d7d7d42891df7edd96 28-Aug-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added load/store intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
abbcf3bd47ad8ffa70f48ebd924f99fff5c22131 28-Aug-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added move.v


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
a6c3a4ee76ef8464d3c83472e15af521ade7eeb4 28-Aug-2013 Daniel Sanders <daniel.sanders@imgtec.com> [mips][msa] Added cfcmsa, and ctcmsa

The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
da0860f78e6e43aca3333a7815b2f9bc0f8dfac0 13-Aug-2013 Jack Carter <jack.carter@imgtec.com> [Mips] Support for unaligned load/store microMips instructions

This includes instructions lwl, lwr, swl and swr.

Patch by Zoran Jovnovic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
491d04969d9f29ed891c73238648853954ba4f81 08-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename accumulator register classes and FP register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
94a88c49b0e87ee8c911669ff6c6bbd31b912542 08-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Delete register class HWRegs64.

No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
1858786285139b87961d9ca08de91dcd59364afb 07-Aug-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename register classes CPURegs and CPU64Regs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
ba54bca472a15d0657e1b88776f7069042b60b4e 19-Jun-2013 Bill Wendling <isanbard@gmail.com> Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
6a2e7ac0b6647a409394e58b385e579ea62b5cba 06-Jun-2013 Bill Wendling <isanbard@gmail.com> Cache the TargetLowering info object as a pointer.

Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
ac6d9bec671252dd1e596fa71180ff6b39d06b5d 25-May-2013 Andrew Trick <atrick@apple.com> Track IR ordering of SelectionDAG nodes 2/4.

Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
a2b2200ff8684ba23c64b24c0128a78f4b6e3c73 03-May-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Split the DSP control register and define one register for each field of
its fields.

This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 20-Apr-2013 Michael Liao <michael.liao@intel.com> ArrayRefize getMachineNode(). No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
3d60241c3e86973be281660bc5971c3a46cfdc47 13-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Reapply r179420 and r179421.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
d35d5bdfc41ff401f938e49e844d707462405428 13-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> Revert r179420 and r179421.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
6d224459f42fd1e2a57479b6b60e55053dce38d7 13-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Instruction selection patterns for carry-setting and using add
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
fc82e4db13b46b2f14f5895d2a0b33524d55d06a 11-Apr-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selects
multiply instructions in MipsSEDAGToDAGISel.

This patch was supposed to be part of r178403.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
a430cb613b6e93c05f128b04323c57acfd08686d 09-Apr-2013 Reed Kotler <rkotler@mips.com> This patch enables llvm to switch between compiling for mips32/mips64
and mips16 on a per function basis.

Because this patch is somewhat involved I have provide an overview of the
key pieces of it.

The patch is written so as to not change the behavior of the non mixed
mode. We have tested this a lot but it is something new to switch subtargets
so we don't want any chance of regression in the mainline compiler until
we have more confidence in this.

Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1.
For that reason there are derived versions of the register info, frame info,
instruction info and instruction selection classes.

Now we register three separate passes for instruction selection.
One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then
one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and
MipsSEISelDAGToDAG.cpp).

When the ModuleISel pass runs, it determines if there is a need to switch
subtargets and if so, the owning pointers in MipsTargetMachine are
appropriately changed.

When 16Isel or SEIsel is run, they will return immediately without doing
any work if the current subtarget mode does not apply to them.

In addition, MipsAsmPrinter needs to be reset on a function basis.

The pass BasicTargetTransformInfo is substituted with a null pass since the
pass is immutable and really needs to be a function pass for it to be
used with changing subtargets. This will be fixed in a follow on patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
f5926fd844a84adcf1ae4f193146f2877997b82c 30-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.

The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
275f354d6d459f4bcfb3d3e8b5b7f3ed08585940 14-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Define function MipsSEDAGToDAGISel::selectAddESubE.

No intended functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
f283512d72757aac5bedcb270f9199194e6a12c0 14-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Rename functions and variables to start with proper case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
554d9312b284265f91ac5ee5bf0351d446f669b1 14-Mar-2013 Akira Hatanaka <ahatanaka@mips.com> [mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is for
mips16 and MipsSEDAGToDAGISel is for mips32/64.

No functionality changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp