| cddc3e03e4ec99c0268c03a126195173e519ed58 |
|
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)
Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/test/MC/ARM/diagnostics.s
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/test/MC/ARM/diagnostics.s
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| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/test/MC/ARM/diagnostics.s
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/test/MC/ARM/diagnostics.s
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/test/MC/ARM/diagnostics.s
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| 59e648e3c8966e0678902a2994558f25c8573ce4 |
|
12-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: diagnose invalid system LDM/STM
The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).
(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).
rdar://problem/15223374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
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| 1b91231347c00bf1be46bdd5b27ae8c45fdc0d0c |
|
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| eac623a18b1e7ad9e5a7da76a323039450b7d7ce |
|
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: mark various aliases with their architecture requirements.
If an alias inherits directly from InstAlias then it doesn't get any default
"Requires" values, so llvm-mc will allow it even on architectures that don't
support the underlying instruction.
This tidies up the obvious VFP and NEON cases I found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
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| cdd776d13f799da1aff4b2c9c58a236bee74ea2e |
|
24-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix assert on unpredictable POP instruction.
POP instructions are aliased to the ARM LDM variants but have different syntax.
This caused two problems: we tried to access a non-existent operand to annotate
the '!', and the error message didn't make much sense.
With some vigorous hand-waving in the error message both problems can be
fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
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| 01b0e94bb731310e72f66977e4b57cd3f3280ba4 |
|
22-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: provide diagnostics on more writeback LDM/STM instructions
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.
For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.
rdar://problem/15223374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
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| b5523ce1bb50e86942ad5273e3a89872c4d26b73 |
|
05-Sep-2013 |
Richard Barton <richard.barton@arm.com> |
Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.
The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.
HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.
Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| c19bd321362166805194cbaf170e06a4790d2da9 |
|
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):
+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| c1a91dd97b000128189421eda6c5bb7905b1f467 |
|
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow predicated barriers in Thumb mode
The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| bf811d602d1d81b93846c6cbbd1cec85f2f153cb |
|
18-Jun-2013 |
Kevin Enderby <enderby@apple.com> |
Change the arm assembler to support this from the v7c spec:
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."
In the pre-matcher handler in the asm parser the ".w" (wide) qualifier
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.
Test cases for these were added.
rdar://14064574
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 4e9a96d810eb0cc126ebe6f18e536b474c84940c |
|
10-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| ebf3a37c0a5cea1ded89750e88d672951bf133cc |
|
10-Oct-2012 |
Craig Topper <craig.topper@gmail.com> |
Test case for r165480.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 93c7c449a1351542fa5a275587187154dbedb8e0 |
|
22-Sep-2012 |
Tim Northover <Tim.Northover@arm.com> |
Fix the handling of edge cases in ARM shifted operands.
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 70c9bf3c1a77b5707c92a7cfe74104c320480391 |
|
23-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add a better diagnostic for some out of range immediates.
As an example of how the custom DiagnosticType can be used to provide
better operand-mismatch diagnostics, add a custom diagnostic for
the imm0_15 operand class used for several system instructions.
Update the tests to expect the improved diagnostic.
rdar://8987109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159051 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| a1c7367a5bed459acc88e3ea2a482b4b5dac942a |
|
14-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Replace assertion failure for badly formatted CPS instrution with error message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| be7cf2b377d987f46d10f54f89ae4e1a71c37f55 |
|
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM ldm/stm register lists can be out of order.
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 9b8f2a0b365ea62a5fef80bbaab3cf0252db2fcf |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for the <option> form of LDC/STC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 326efe58918d3f0a431d07938054870fcd0e240f |
|
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| d0588e2a2ed1f7570f13b78c2042855dc4afae10 |
|
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix assembly parser handling of ranges in register lists.
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 2fd2b87ded53f6b87eb240c17d62a23fb4964ba0 |
|
10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| fb8989e64024547e4ad5ab6fe4d94fe146a7899f |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 7e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0 |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 189610f9466686a91fb7d847b572e1645c785323 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM diagnostics for ldrexd/stredx out of order paired register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| ed8384806e56952c44f8a717c1ef54a8468d2c8d |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for SVC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| a46c658c6619e979a54ec1e4dc919b3a0319129a |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM STM tests. Fix check: prefix for diagnostic tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| f49433523e8a39db6d83503e312ae55160eed90a |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9f |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| c27d4f9ea0cb9064d3e2cadb384d73e95e9de449 |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 61b1b21e9ad2b8af163a352766eeb159979f4ff2 |
|
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM PKH assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| ccfd9313d11aa29551f93fe99428946837c97729 |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 1a2be4db5b12cb7bfa351bcebd5e94b0decb021f |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for MOVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 5f16057d1e4b711d492091bc555693a03d4a1b6e |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (register).
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| ffa3225e26cc1977d20f0d9649fcd6f38a3c4815 |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 33c16a27370939de39679245c3dff72383c210bd |
|
15-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| c8ae39e746a20dc326def0ccfc052df3e21f16d3 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| e540c7422ca13c950f0e8f6f93af7225bb7742a9 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 6f9f8845028d4d3b96c33417398034a71137d867 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 83ab070fc1fbb02ca77b0a37e6ae0eacf58001e1 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| fff76ee7ef007b2bb74804f165fee475e30ead0d |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for 16-bit immediates in ARM assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|
| 19906729a490744ce3071d20e3d514cadc12e6c5 |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.
Add some tests for the diagnostics we do want.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/diagnostics.s
|