| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| 29e05fe7a885bd03d8570d2bcf14193013776bcd |
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22-Feb-2013 |
Kristof Beyls <kristof.beyls@arm.com> |
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
The Printer will now print instructions with the correct alignment specifier syntax, like
vld1.8 {d16}, [r0:64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| b1d081230e40e5c86f3cc44a7cfd7241732eabfb |
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14-Feb-2013 |
Kristof Beyls <kristof.beyls@arm.com> |
Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like
vld1.8 {d16}, [r0:64]
, while also still accepting the incorrect syntax
vld1.8 {d16}, [r0, :64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| a57a36abe7d0b769a495ed886246db157aff4add |
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25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| 5e59f7e15ed3770b32481cd72d2c15b159e991e6 |
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25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| e983a134e7e40e214f590c3d8ba565bb85f39628 |
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24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(one lane) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| 8abe7e33641fccfa70a7e335939e83dfbf654fe8 |
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24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(multiple 4 element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| c387fc66bd52e4276fdc2704a3aaed57cc1f9a11 |
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24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(multiple 3-element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| e6949b13997e6d31aa4719a0e80c4b6b405e42a9 |
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21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| 3471d4fbbd50eabb12511b711cbd2afd7bb9d962 |
|
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| 95fad1c6034cdf8010428e61b71cd196ee1698ad |
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20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| eeaf1c1636c664c707fd9ecc96916fd20ddf137a |
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19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| 9b1b3902882675e5ce35eacd639456bd648324b7 |
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15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| a4e3c7fc4ba2d55695b0484480685698132eba20 |
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09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| c4f0b309eeaa479de9bbf62eaf304931a526f622 |
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02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for VLD1 single lane w/ writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| dad2f8e7fb2df5fb080a38fa4c33a01f19729f15 |
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02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| e30171ba0ce10c8a37ee1aabc0d5cd13136dc7c4 |
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30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some tests for all-lanes VLD1 parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| e43862b6a6130ec29ee4e9e6c6c30b5607c9a728 |
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16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for register range syntax for VLD/VST register lists.
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| e052b9afa1301419f8b52eed9ed370393fcad78d |
|
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| c73d73eb881ebe7493e934c00ca1c474ffd0ed2d |
|
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Allow 'q' registers in VLD/VST vector lists.
Just treat it as if the constituent D registers where specified.
rdar://10348896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| 399cdca4d201f7232126c3a0643669971ede780a |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 with writeback.
Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| 5921675ff5ea632ab1e6d7aa5d1f263b858bbafa |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
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| 12431329d617064d6e72dd040a58c1635cc261ab |
|
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
One and two length register list variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| 224180e81b34c99d15e35a4d4de6729357c6d372 |
|
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| 4661d4cac3ba7f480a91d0ccd35fb2d22d9692d3 |
|
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 2-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| b6310316dbaf8716003531d7ed245f77f1a76a11 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| cdcfa280568d5d48ebeba2dcfc87915105e090d1 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| 280dfad48940a0a51726308dd3daa3b1b0d18705 |
|
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| 6b09c77b7a831f57ccedb20c760031492a0af043 |
|
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| 0ebefdf8345d0bdfcccde4057f3cce1c2dbbda9b |
|
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| f0ea0f2b1575868cd238391868d8f51370041303 |
|
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the rest of the vld instructions that we generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| cf667be17b479fe276fd606b8fd72ccfa3065bb8 |
|
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|
| d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5 |
|
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for the "multiple single elements" form of vld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/neon-vld-encoding.s
|