| f8a8f069ee2dae35470c6e2a681e5e110044e6fe |
|
29-Aug-2012 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/msaa: flag _NEW_MULTISAMPLE in the brw_tracked_state
This is required to get the program recompiled when SampleAlphaToCoverage
is enabled.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| e592f7df0361eb8b5c75944f0151c4e6b3f839dd |
|
02-Aug-2012 |
Anuj Phogat <anuj.phogat@gmail.com> |
i965/msaa: Add sample-alpha-to-coverage support for multiple render targets
Render Target Write message should include source zero alpha value when
sample-alpha-to-coverage is enabled for an FBO with multiple render targets.
Source zero alpha value is used as fragment coverage for all the render
targets.
This patch makes piglit tests draw-buffers-alpha-to-coverage and
alpha-to-coverage-no-draw-buffer-zero to pass on Sandybridge. No
regressions are observed with piglit all.tests.
V2: Revert all the changes made in emit_color_write() function to
include src0 alpha for targets > 0. Now handling this case in a if
block.
V3: Correctly calculate the instruction length for buffer zero.
Properly handle the case of dual_src_blend when alpha-to-coverage
is enabled.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| fc3b7c9b56701f23b002543de33a8d8c43f9bdc2 |
|
12-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add performance debug for shader recompiles.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 86e401b771ce4a6f9a728f76c5061c339f012d0a |
|
12-Jul-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Always emit alpha when nr_color_buffers == 0.
If alpha-testing is enabled, we need to send alpha down the pipeline
even if nr_color_buffers == 0. However, tracking whether alpha-testing
is enabled in the WM program key is expensive: it causes us to compile
multiple specializations of the same shader, using program cache space.
This patch removes the check for alpha-testing, and simply emits alpha
whenever nr_color_buffers == 0. We believe this will also be necessary
for alpha-to-coverage, and it should add minimal overhead to an uncommon
case. Saving the recompiles should more than make up the difference.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 82d25963a838cfebdeb9b080169979329ee850ea |
|
20-Jun-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Compute dFdy() correctly for FBOs.
On i965, dFdx() and dFdy() are computed by taking advantage of the
fact that each consecutive set of 4 pixels dispatched to the fragment
shader always constitutes a contiguous 2x2 block of pixels in a fixed
arrangement known as a "sub-span". So we calculate dFdx() by taking
the difference between the values computed for the left and right
halves of the sub-span, and we calculate dFdy() by taking the
difference between the values computed for the top and bottom halves
of the sub-span.
However, there's a subtlety when FBOs are in use: since FBOs use a
coordinate system where the origin is at the upper left, and window
system framebuffers use a coordinate system where the origin is at the
lower left, the computation of dFdy() needs to be negated for FBOs.
This patch modifies the fragment shader back-ends to negate the value
of dFdy() when an FBO is in use. It also modifies the code that
populates the program key (brw_wm_populate_key() and
brw_fs_precompile()) so that they always record in the program key
whether we are rendering to an FBO or to a window system framebuffer;
this ensures that the fragment shader will get recompiled when
switching between FBO and non-FBO use.
This will result in unnecessary recompiles of fragment shaders that
don't use dFdy(). To fix that, we will need to adapt the GLSL and
NV_fragment_program front-ends to record whether or not a given shader
uses dFdy(). I plan to implement this in a future patch series; I've
left FIXME comments in the code as a reminder.
Fixes Piglit test "fbo-deriv".
NOTE: This is a candidate for stable release branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 796f44d77906342e5912e7da6bdba1ba86bab9f0 |
|
20-Jan-2012 |
Eric Anholt <eric@anholt.net> |
intel: Pass the gl_renderbuffer to render_target_supported() vtable method.
I'm going to want to go looking at it for an integer texture fix.
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 1b05fc7cdd0e5d77b50bc8ee2f2c851da5884d72 |
|
07-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Factor out texturing related data from brw_wm_prog_key.
The idea is to reuse this for the VS and (in the future) GS as well.
v2: Include yuvtex data since we're not dropping GL_MESA_ycbycr.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 6661b7596f3b26a773ccde79f018179713b6b6e0 |
|
15-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add the context to the render_target_supported() vtbl method.
We're going to want to provide different answers per chipset
generation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 1ab1b15e9d0da1c5215a20770735b5477f5313df |
|
23-Oct-2011 |
Chia-I Wu <olv@lunarg.com> |
mesa, i965: prepare for more than 8 texture targets
3-bit fields are used store texture target in several places. That will fail
when TEXTURE_EXTERNAL_INDEX, which happends to be the 9th texture target, is
added. Make them 4-bit fields.
Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Jakob Bornecrantz <jakob@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| e04bdeae82797dbdcf6f544a997a4626fdfd4aee |
|
22-Oct-2011 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6+: Parameterize barycentric interpolation modes.
This patch modifies the fragment shader back-end so that instead of
using a single delta_x/delta_y register pair to store barycentric
coordinates, it uses an array of such register pairs, one for each
possible intepolation mode.
When setting up the WM, we intstruct it to only provide the
barycentric coordinates that are actually needed by the fragment
shader--that is computed by brw_compute_barycentric_interp_modes().
Currently this function returns just
BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because this is the only
interpolation mode we support. However, that will change in a later
patch.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 6430df37736d71dd2bd6f1fe447d39f0b68cb567 |
|
10-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/fs: Add support for TXD with shadow comparisons.
Our hardware doesn't have a sample_d_c message, so we have to do a
regular sample_d and emit instructions to manually perform the
comparison.
This requires a state dependent recompile whenever the sampler's compare
mode or function change. This adds the per-sampler comparison functions
to brw_wm_prog_key, but only sets them when the sampler's compare mode
is GL_COMPARE_R_TO_TEXTURE (i.e. only for shadow sampling).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 8752764076e5b3f052a57e0134424a37bf2e9164 |
|
17-May-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Do a FS compile up front at link time to produce link errors.
At glLinkShaders time, a fail() call in FS compile in 8-wide (the one
that's required to succeed, though we may relax that at some point for
pre-Ironlake performance) will now report out as a link error.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| f7b3f40b70dc7dd602897d364011089047583c5d |
|
19-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Pack the lookup and line_aa bits into the first dword of the key.
They were occupying whole 32-bit words, despite being only 10 or so
bits. Reduces code size slightly (80/3300 bytes).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 9a729ab4b273f503747209a9c58dbb664adca838 |
|
19-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove dead shadowtex_mask entry in the WM key.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| f147599ef4b0d14c25a7e0d3f9f1c9b0229bb6fc |
|
19-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove linear_color for GL_PERSPECTIVE_CORRECTION_HINT.
From the GL 2.1 spec:
"Required perspective-correct interpolation for all fragment
attributes except depth in sections 3.4.1 and 3.5.1, effectively
making GL PERSPECTIVE CORRECT HINT a no-op."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| b126a0c0cb30b1e2f2df1953fe14d8596d1cf4f7 |
|
02-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for correct GL_CLAMP behavior by clamping coordinates.
This removes the stupid strict-conformance fallback code I broke when
adding ARB_sampler_objects.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36572
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 03b2e0fcdf92c76411a957c3ea898233fb4ce1be |
|
29-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix fragcoord_w on gen6 with 16-wide.
The payload regs can go all the way up to register 60+, so just give
them 8 bits to be addressed by instead of 3-4 (which made source_w_reg
of 8 end up 0). There's no reason to aggressively pack these fields,
as they are just used as compiler information, where being easier to
access is probably more important than shaving a byte or two off of
the structure.
Fixes piglit fragcoord_w.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36649
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 662f1b48bd1a02907bb42ecda889a3aa52a5755d |
|
12-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965/fs: Add initial support for 16-wide dispatch on gen6.
At this point it doesn't do uniforms, which have to be laid out the
same between 8 and 16. Other than that, it supports everything but
flow control, which was the thing that forced us to choose 8-wide for
general GLSL support.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 79bde19ef9e13d5db30d0516d9e7eae6a3a8d32a |
|
21-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't double-emit fragment.color writes for MRT with ARB_fp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| d22e2ebe35ef9d33ec5f7a67f903f36bcd9fbc91 |
|
15-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_color_buffer_float.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 5e9aa9926b9bdf1260ce7350b88908bda337388b |
|
26-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
mesa: Remove the CompileShader driver hook; it's just a no-op.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| a99447314ca1cfce60f2a22285398fb222b2a440 |
|
12-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix alpha testing when there is no color buffer in the FBO.
We were alpha testing against an unwritten value, resulting in garbage.
(part of) Bug #35073.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| a7bf7230564ac282cc957207224d16f322fa73d8 |
|
08-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add a vtbl hook for determining if a format is renderable.
By relying on just intel_span_supports_format, some formats that
aren't supported pre-gen4 were not reporting FBO incomplete. And we
also complained in stderr when it happened on i915 because draw_region
gets called before framebuffer completeness validation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| d547ab150ae8db64caebbae2b2414a3988b2f089 |
|
08-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Drop KIL_NV from the ff/ARB_fp path since it was only used for GLSL.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 5ba517baa22b05d594b8839ac06fe45b81c1d09f |
|
11-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Nuke brw_wm_glsl.c.
It was only used for gen6 fragment programs (not GLSL shaders) at this
point, and it was clearly unsuited to the task -- missing opcodes,
corrupted texturing, and assertion failures hit various applications
of all sorts. It was easier to patch up the non-glsl for remaining
gen6 changes than to make brw_wm_glsl.c complete.
Bug #30530
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 16f8c823898fd71a3545457eacd2dc31ddeb3592 |
|
11-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move payload reg setup to compile, not lookup time.
Payload reg setup on gen6 depends more on the dispatch width as well
as the uses_depth, computes_depth, and other flags. That's something
we want to decide at compile time, not at cache lookup. As a bonus,
the fragment shader program cache lookup should be cheaper now that
there's less to compute for the hash key.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 3b337f5cd94384d2d5918fb630aa8089e49b1d8d |
|
13-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix gl_FragCoord inversion when drawing to an FBO.
This showed up as cairo-gl gradients being inverted on everyone but
Intel, where I'd apparently tweaked the transformation to work around
the bug. Fixes piglit fbo-fragcoord.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| f30de6964018619658439216cd8bf9371ee6256d |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Disable thread dispatch when the FS doesn't do any work.
This should reduce the cost of generating shadow maps, for example.
No performance difference measured in nexuiz, though it does trigger
this path.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 37758fb1cbb1ddcd106553763c1b1f222f4cfb47 |
|
11-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move FS backend structures to a header.
It's time to start splitting some of this up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| ef8e002c75a5def2c400638336dcd55d411d87be |
|
28-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix up part of my Sandybridge attributes support patch.
I confused the array sizing for number of files for the number of regs
in a file.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| a66e9a4d86d227b65874c43fbf9e299c7a26389f |
|
26-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for attribute interpolation on Sandybridge.
Things are simpler these days thanks to barycentric interpolation
parameters being handed in in the payload.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| dd9a88f4ddf4e5fa384792f891a1cc3d8ff73946 |
|
21-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Track the windowizer's dispatch for kill pixel, promoted, and OQ
Looks like the problem was we weren't passing the depth to the render
target as expected, so the chip would wedge. Fixes GPU hang in
occlusion-query-discard.
Bug #30097
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 23c507f1358833585de330ed313dffafabbbd3cd |
|
21-Sep-2010 |
Eric Anholt <eric@anholt.net> |
i965: Share the KIL_NV implementation between glsl and non-glsl.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 9763d0a82a1ee605a8794f199d432824fb972b6a |
|
26-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start building direct GLSL2 IR to 965 assembly codegen.
Our channel-expressions and vector-splitting changes now happen into a
private copy of the IR that we maintain for ourselves. Uniform
assignment still happens by the core, so we continue using Mesa IR
generation not just for swrast fallbacks but also for uniform values
(since there's no storage for their contents other than
shader_program->FragmentProgram->Parameters->ParameterValues). And
most importantly, at the moment no actual codegen is hooked up other
than emitting our favorite color to the framebuffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| c1dfdcb93a8991788032d4906c5bf1a5b48cdc48 |
|
26-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add new pass to split vectors into scalar variables
Combined with the previous pass, this lets other optimization passes
do their work thanks to ir_tree_grafting. Still have regression in
instruction count with INTEL_NEW_FS, but register count is even
better.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 3a8ad33dde2f059b82ebf09f5cffa66c86f2e734 |
|
13-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a pass for the FS to reduce vector expressions down to scalar.
This is a step towards implementing a GLSL IR backend for the 965
fragment shader. Because it has downsides with the current codegen,
it is hidden under the environment variable INTEL_NEW_FS.
This results in an increase in instruction count at the moment (1444
-> 1752 for glsl-fs-raytrace, 345 -> 359 on my demo), because dot
products are turned into a series of multiplies and adds instead of a
custom expansion of MULs and MACs, and by not splitting the variable
types up we don't get tree grafting and thus there are extra moves of
temporary storage. However, register count drops for the non-GLSL
path (64 -> 56 on my demo shader) because the register allocator sees
all the sub-operations.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| a1bebf73dfdaf2cd23286aa74271b87166589901 |
|
11-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Start building 965 FS backend.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 501c9dc62774a73c080d500a1eab773b0da9577e |
|
17-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Rename nr_depth_regs to nr_payload_regs.
Only 8 out of the up to 13 regs are for source/dest depth, so the name
wasn't particularly appropriate. Note that this doesn't count the
constant or URB payload regs. Also, don't pre-divide by 2, so it's
actually a number of registers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| afe125e0a18ac3886c45c7e6b02b122fb2d327b5 |
|
27-Jul-2010 |
Eric Anholt <eric@anholt.net> |
Merge remote branch 'origin/master' into glsl2
This pulls in multiple i965 driver fixes which will help ensure better
testing coverage during development, and also gets past the conflicts
of the src/mesa/shader -> src/mesa/program move.
Conflicts:
src/mesa/Makefile
src/mesa/main/shaderapi.c
src/mesa/main/shaderobj.h
|
| 4e7d5d0e74c26cac182cea1be0f6b79bb664ad8c |
|
03-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the DP2 opcode, which we use for dot(vec2, vec2).
The original glsl compiler would generate a.x * b.x + a.y * b.y, which
we would do mul+mul+add for instead of this mul+mac.
Fixes glsl-fs-dot-vec2.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| e558786a3ed52222c07f916e213b63dcba1890a2 |
|
01-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for OPCODE_SSG.
The old compiler didn't use SSG, and instead emitted SGT/SGT/SUB. We
can do a little better for SSG than we do for the SGT series.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| ec2b92f98c2e7f161521b447cc1d9a36bce3707c |
|
11-Jun-2010 |
Brian Paul <brianp@vmware.com> |
mesa: rename src/mesa/shader/ to src/mesa/program/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 08b42bc97d77ff1ea7eefe4ec57997b80fb9b458 |
|
23-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix bit allocation for number of color regions for ARB_draw_buffers.
If you used all 4 color targets we currently support, we would see 0
and end up just writing the first output. Give enough bits that we
can do the maximum of 16.
Fixes piglit fbo-drawbuffers-maxtargets.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 4fc57322258a750c0a9cabc77372b5ccde1fa877 |
|
19-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow FS constants to be used as immediates instead of push/pull.
The hope is to later take advantage of the reduced constant usage to
free up regs. This only covers the GLSL path at the moment, because
the brw_wm_emit path doesn't get the information as to whether a float
value is a constant or a uniform.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 48dca99feb394febc3af44e14f23fb12a9cc9204 |
|
10-Mar-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for the CMP opcode in the GLSL path.
This would be triggered by use of sqrt() along with control flow.
Fixes piglit-fs-sqrt-branch and a bug in Yo Frankie!.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| f62c2a0bb89041567467a6c01cf1eb27cec01e9e |
|
26-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Fix fp fragment.position handling and enable HW part of ARB_fcc.
As with swrast, this fixes the default pixel center behavior which was
broken, and implements the previous behavior for integer. Fixes
piglit fp-arb-fragment-coord-conventions-none. The extension won't be
exposed until we get the GLSL part implemented.
The DRI1 origin_x/y parts are dropped since they're no longer relevant.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 92d35b91f132deda1fb27d2071a50e8187301fe5 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Pack the brw_wm_prog_key better.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 5606dfb572bf4b89b4882265924705bacc8c182b |
|
18-Nov-2009 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'outputswritten64'
Add a GLbitfield64 type and several macros to operate on 64-bit
fields. The OutputsWritten field of gl_program is changed to use that
type. This results in a fair amount of fallout in drivers that use
programs.
No changes are strictly necessary at this point as all bits used are
below the 32-bit boundary. Fairly soon several bits will be added for
clip distances written by a vertex shader. This will cause several
bits used for varyings to be pushed above the 32-bit boundary. This
will affect any drivers that support GLSL.
At this point, only the i965 driver has been modified to support this
eventuality.
I did this as a "squash" merge. There were several places through the
outputswritten64 branch where things were broken. I foresee this
causing difficulties later for bisecting. The history is still
available in the branch.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 57f40b18377f87c434f17d5670a13838d58065c9 |
|
19-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.c
This should fix TXB on G45 and older in the GLSL case.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 1be0efcbdc74f9a84136c9d1f953755c1560e52e |
|
19-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.
New comments should explain some of the confusion about how this message
works.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| c5413839b3e99c7b162f1260142f3c175502b0ce |
|
11-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.
For an app that's blowing out the state cache, like sauerbraten, the
memset of the giant arrays ended up taking 11% of the CPU even when only a
"few" of the entries got used. With this, the WM program compile drops back
down to 1% of CPU time.
Bug #24981 (bisected to BRW_WM_MAX_INSN increase).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| ec66644ed0af976cacb069ca7c7f0d6731666359 |
|
19-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| cfa927766ab610a9a76730d337d77008d876ebbd |
|
19-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.c
This should fix issues with antialiased lines in GLSL.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 2b58c31257f8900067276b6d6537bb2ce54b1b10 |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.c
The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's
had been improved, and pixel_w should no longer stomp on a neighbor to dst.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 1e5400c575b72fbde16ef0d55fd3ba577fc1b6a5 |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 7059aa0eff9ff6ec361e584b413f63b25762a89c |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 726ad1560660a1fc769c87e0ea16f8b3334df0d2 |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| bad5b120be8de37cf8481d865790298fd9651381 |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 06c1bc8a2222f00e5a51fa977130a719bdcd8f0b |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 71af5080722afcbbb8a935138d95214ef7afe219 |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.c
This drops support for get_src_reg_imm in these, but the prospect of getting
brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 0f34cdf6210b748db77c5eba2993637f4af6faeb |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Collect GLSL src/dst regs up in generic code.
This matches brw_wm_emit.c, which we'll be using shortly. There's a
possible penalty here in that we'll allocate registers for unused channels,
since we aren't doing ref tracking like brw_wm_pass*.c does. However, my
measurements on GM965 don't show any for either OA or UT2004 with the GLSL
path forced.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 2c30ee9bd69ed606b984c051748a7cdb34905eeb |
|
30-Oct-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix BRW_WM_MAX_INSN to reflect current limits.
Part of fixing bug #24355.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 035b21f365f563cba9bf9b8cb4fef613ceb9d3ac |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: make brw_wm_prog_key a little smaller
GLushort is big enough for the swizzle and origin fields.
The key could probably be made smaller still by re-ordering things.
I'll hold off on that until after the outputswritten64 branch is merged.
The key will get a little larger again with the GLbitfield64 fields.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 9ef33b86855c4d000271774030bd1b19b6d79687 |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: don't use context state in emit_fb_write()
Put the state that we care about in the hash key.
Issue spotted by Keith Whitwell.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| a8d233e509a2c1aada7cd4e83b126ba06cb90565 |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: use macros to get/set prog_instruction::Aux field
This makes things a bit easier to remember/understand.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 57d16c4cc37689710f951cb13981e2efc160cd23 |
|
11-Sep-2009 |
Eric Anholt <eric@anholt.net> |
i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.
Previously, it was trying to mess around with the varying's
WM setup data to produce a result. Along with not actually working when
passed a varying, this wouldn't work if you did dFd[xy]() on a temporary.
Instead, just calculate the derivative using the neighbors in the subspan.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 63fa5fd319c0d0114085f47f028a36f63c1f7295 |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: drop dead scalar handling in GLSL.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 0eb819a2d175cab139f8c672b6d44148b2c99a4e |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Store the dispatch width in the WM compile struct.
I'll be using this in merging brw_wm_emit.c and brw_wm_glsl.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 536476f2432168fb15ac06b52c953a594ad851ad |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.
This is preparation for merging of brw_wm_glsl.c and
brw_wm_emit.c, and glsl.c doesn't swizzle channel results around.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| f44916414ecd2b888c8a680d56b7467ccdff6886 |
|
06-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix source depth reg setting for FSes reading and writing to depth.
For some IZ setups, we'd forget to account for the source depth register
being present, so we'd both read the wrong reg, and write output depth to
the wrong reg.
Bug #22603.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 8d482227915552c414e13743652e6794c4313ae2 |
|
17-Jun-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_5_branch'
Conflicts:
src/mesa/main/api_validate.c
|
| 6b917d0b1787280f976c2f0d1ead0e5d7587a3e9 |
|
17-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix bugs in projective texture coordinates
For the TXP instruction we check if the texcoord is really a 4-component
atttibute which requires the divide by W step. This check involved the
projtex_mask field. However, the projtex_mask field was being miscalculated
because of some confusion between vertex program outputs and fragment
program inputs.
1. Rework the size_masks calculation so we correctly set bits corresponding
to fragment program input attributes.
2. Rename projtex_mask to proj_attrib_mask since we're interested in more
than just texcoords (generic varying vars too).
3. Simply the indexing of the size_masks and proj_attrib_mask fields.
4. The tracker::active[] array was mis-dimensioned. Use MAX_PROGRAM_TEMPS
instead of a magic number.
5. Update comments, add new assertions.
With these changes the Lightsmark demo/benchmark renders correctly, until
we eventually hit a GPU lockup...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 18af7c384cf663533f210d95d074c244d4214f29 |
|
13-Jun-2009 |
Brian Paul <brianp@vmware.com> |
i965: interpolate colors with perspective correction by default
...rather than with linear interpolation. Modern hardware should use
perspective-corrected interpolation for colors (as for texcoords).
glHint(GL_PERSPECTIVE_CORRECTION_HINT, mode) can be used to get
linear interpolation if mode = GL_FASTEST.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 0f5113deed91611ecdda6596542530b1849bb161 |
|
14-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix register allocation of GLSL fp inputs.
Before, if the VP output something that is in the attributes coming into
the WM but which isn't used by the WM, then WM would end up reading subsequent
varyings from the wrong places. This was visible with a GLSL demo
using gl_PointSize in the VS and a varying in the WM, as point size is in
the VUE but not used by the WM. There is now a regression test in piglit,
glsl-unused-varying.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| e2cf522de09bc4afa18ef8d98db69973ee489d58 |
|
08-May-2009 |
Brian Paul <brianp@vmware.com> |
i965: don't use GRF regs 126,127 for WM programs
They seem to be used for something else and using them for shader temps
seems to lead to GPU lock-ups.
Call _mesa_warning() when we run out of temps.
Also, clean up some debug code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 777b9ff43e88e456d686208c83712f26aba2dd95 |
|
27-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: only upload constant buffer data when we actually need the const buffer
Make the use_const_buffer field per-program and only call the code which
updates the constant buffer's data if the flag is set.
This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052
(cherry picked from master, commit dc9705d12d162ba6d087eb762e315de9f97bc456)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| dc9705d12d162ba6d087eb762e315de9f97bc456 |
|
27-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: only upload constant buffer data when we actually need the const buffer
Make the use_const_buffer field per-program and only call the code which
updates the constant buffer's data if the flag is set.
This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| b58b3a786aa38dcc9d72144c2cc691151e46e3d5 |
|
25-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: rework GLSL/WM register allocation
Use a bitvector of used/free flags.
If we run out of temps, examine the live intervals of the temp regs in
the program and free those which are no longer alive.
Also, enable the new WM const buffer code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 1e299ff828e808cbb1d92d9fedd528a3a8a3609e |
|
01-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: another checkpoint commit of new constant buffer support
Everything is in place now for using a true constant buffer for GLSL fragment
shaders. Still some bugs to find though.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| bf28b576cb6aa403b840d8254a1ff3f31d664b46 |
|
23-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix indentation
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 699db6d842c52d0b3b98b320f8ef1104a65fa783 |
|
24-Mar-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix glFrontFacing in twoside GLSL demo.
This also cuts instructions by just using the existing bit in the payload
rather than computing it from the determinant in the SF unit and passing it
as a varying down to the WM. Something still goes wrong with getting the
backface color right, but a simpler shader appears to get the right result.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 2cf296186e2a2a635a461b2498d4afa7762656f5 |
|
13-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: remove unused PROGRAM_INTERNAL_PARAM, added comment
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| faae1994c97746a74f68abeeafd69b27f9651d19 |
|
06-Mar-2009 |
Brian Paul <brianp@vmware.com> |
i965: comments
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| e0d907308150b4863cc4f24543e70e14207e966a |
|
20-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: use the new prog_instruction::TexShadow field
GLSL shadow() sampler calls are properly propogated down to the driver now.
The glean glsl1 shadow() tests work (except for the alpha channel).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| c51c822ee02cb47ddba46da668577d51b7c02831 |
|
14-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: rewrite the code for handling shader subroutine calls
Previously, the prog_instruction::Data field was used to map original Mesa
instructions to brw instructions in order to resolve subroutine calls. This
was a rather tangled mess. Plus it's an obstacle to implementing dynamic
allocation/growing of the instruction buffer (it's still a fixed size).
Mesa's GLSL compiler emits a label for each subroutine and CAL instruction.
Now we use those labels to patch the subroutine calls after code generation
has been done. We just keep a list of all CAL instructions that needs patching
and a list of all subroutine labels. It's a simple matter to resolve them.
This also consolidates some redundant post-emit code between brw_vs_emit.c and
brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data
fields at the end.
Plus, a bunch of new comments.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| c0d3b7679aa90e1a0dca2db152205efaec088b90 |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: implement GL_EXT_texture_swizzle
If the texture swizzle is not XYZW (no-op) add an extra MOV instruction
after the TEX instruction to rearrange the components.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 177eda834ee26656b4f9b2ec64b8b3e915c1854c |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: remove pad field
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| f78c388b6c156cb155f089b00612f00919090a8e |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: widen per-texture bitfields for 16 texture image units
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 8e76ac070dfea5d151d31121af5c8ca1c99caeb0 |
|
27-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i915: Remove dead early z enable bit which was always on.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| ab3e9c481f7517ffc63770dbb9c81fe559884a35 |
|
31-Oct-2008 |
Gary Wong <gtw@gnu.org> |
i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.
(Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| e92a457ac0030e48f5260dc2ac00ca283be7d7ad |
|
28-Oct-2008 |
Gary Wong <gtw@gnu.org> |
i965: Allocate temporaries contiguously with other regs in fragment shaders.
This is required for threads to be spawned with correctly sized GRF
register blocks.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 7936c614abc165270852bc5e7e316747a9cacdfb |
|
21-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] multiple rendering target fix
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| fcb7cb9e72ecac7c165a3a6ed7a033e2e6793a26 |
|
13-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] multiple rendering target support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 7676980d38cff417015bca8d23549d567d74228b |
|
07-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] fix fd.o bug #11471 and #11478
1. Follow EXT_texture_rectangle with YCbCr texture
2. swap UV component for MESA_FORMAT_YCBCR
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 9c8f27ba1366da07e20e86a0d48341ea97f5cda4 |
|
28-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Bug #9151: make fragment.position return window coords not screen coords.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
|
| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
|
29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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| 84a076079d3a038115a39b1c283b46a574591e07 |
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14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] warnings cleanup
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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| 6ef27b88e6f767cd476676b33cb7c4ea6922234e |
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26-Oct-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Merge branch '965-glsl'
Conflicts:
src/mesa/drivers/dri/i965/brw_sf.h
src/mesa/drivers/dri/i965/intel_context.c
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| 4087c90effecdf2f466e2ddcf88ec2faf0db034f |
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28-Sep-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support nested function call in pixel shader
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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| acfeb3b6ea93bcb5b18e6f51a0727e39da608d76 |
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11-Sep-2007 |
Brian <brian.paul@tungstengraphics.com> |
Fix-up #includes to remove some -I options.
eg: #include "shader/program.h" and remove -I$(TOP)/src/mesa/program
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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| c702a7100e2aa83241e89850a97bcc23e1c6fedb |
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24-Jul-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
DDX DDY support, not very accurate
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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| 575f3e918f00bdc0faa4a173820015b24175696f |
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05-Jul-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support "discard";
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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| d19d0596daf004b56d80f78fa1a329b43c2ebf94 |
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21-Jun-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
support branch and loop in pixel shader
most of the sample working with some small modification
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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| 064ae479a770bf434958d673baf6f7530f642697 |
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23-Feb-2007 |
Brian <brian@yutani.localnet.net> |
Update DRI drivers for new glsl compiler.
Mostly:
- update #includes
- update STATE_* token code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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| cb54c056a6d46d03bfa0c4927f5ac8843feab8cd |
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20-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
restore debug output after brw_wm_fp compilation stage
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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| 9f344b3e7d6e23674dd4747faec253f103563b36 |
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09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm.h
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