| e88cfbb95f631ca1275a5cef4ccc5aaffb70aaba |
|
28-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Support mapping multisample miptrees
Add two new functions: intel_miptree_{map,unmap}_multisample, to which
intel_miptree_{map,unmap} dispatch. Only mapping flat, renderbuffer-like
miptrees are supported.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| f4873babdc27f697df9f4642209eca21a02ac476 |
|
19-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Allocate miptree for multisample DRI2 buffers
Immediately after obtaining, with DRI2GetBuffersWithFormat, the DRM buffer
handle for a DRI2 buffer, we wrap that DRM buffer handle with a region and
a miptree. This patch additionally allocates an accompanying multisample
miptree if the DRI2 buffer is multisampled.
Since we do not yet advertise multisample GL configs, the code for
allocating the multisample miptree is currently inactive.
This patch adds the following fields to intel_mipmap_tree:
singlesample_mt
needs_downsample
and the following function stubs:
intel_miptree_downsample
intel_miptree_upsample
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 7a2e40ed283b70e1da8ea762959ca7462b0f2fc3 |
|
01-Aug-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Update stale comment for intel_miptree_slice::map
The comment referred to intel_tex_image_map/unmap, but should more
accurately refer to intel_miptree_map/unmap.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 8dc074cd92dfc2f80f6c69f80f0d169ad5bb10aa |
|
16-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Fix build broken by ETC1 patch
I suck at resolving merge conflicts and broke the build in a5a34b1.
This patch adds the missing field intel_mipmap_tree::wraps_etc1.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| a5a34b153d494ad4374e7b2c8ea13b1073a887e2 |
|
19-Jun-2012 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Enable GL_OES_compressed_ETC1_RGB8_texture
Enable it for all hardware.
No current hardware supports ETC1, so this patch implements it by
translating the ETC1 data to RGBX data during the call to
glCompressedTexImage2D(). For details, see the doxygen for
intel_mipmap_tree::wraps_etc1.
Passes the Piglit test spec/OES_compressed_ETC1_RGB8_texture/miptree and
the ETC1 test in the GLES2 conformance suite.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| ccae1b1cd7b89102a9d9bfc29eb1e7e48aad8969 |
|
03-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Allocate MCS buffer when CMS MSAA is in use.
To implement Gen7's CMS MSAA layout, we need an extra buffer, the MCS
(Multisample Control Surface) buffer. This patch introduces code for
allocating and deallocating the buffer, and storing a pointer to it in
the intel_mipmap_tree struct.
No functional change, since the CMS layout is not enabled yet.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 1bd4d456cdecf7bea55f4e3dac574af54efad994 |
|
04-Jul-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Add an enum to describe MSAA layout.
From the Ivy Bridge PRM, Vol 1 Part 1, p112:
There are three types of multisampled surface layouts designated
as follows:
- IMS Interleaved Multisampled Surface
- CMS Compressed Mulitsampled Surface
- UMS Uncompressed Multisampled Surface
Previously, the i965 driver only used IMS and UMS formats, and
distinguished beetween them using the boolean
intel_mipmap_tree::msaa_is_interleaved. To facilitate adding support
for the CMS format, this patch replaces that boolean (and other
booleans derived from it) with an enum
INTEL_MSAA_LAYOUT_{IMS,CMS,UMS}. It also updates the terminology used
in comments throughout the driver to match the IMS/CMS/UMS terminology
used in the PRM. CMS layout is not yet used.
The enum has a fourth possible value, INTEL_MSAA_LAYOUT_NONE, which is
used for non-multisampled surfaces.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 02ebad900db4ef1ac42cbfb41b433919a4c857a2 |
|
05-Jul-2012 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Add offset field to miptree
This lets us specify an offset into the bo where the miptree starts,
which will let us set up a texture for a single plane in a planar buffer.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 455ac562722f60ac9fb0c3d3c697fa339fa011ad |
|
08-May-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/msaa: Properly handle sliced layout for Gen7.
Starting in Gen7, there are two possible layouts for MSAA surfaces:
- Interleaved, in which additional samples are accommodated by scaling
up the width and height of the surface. This is the only layout
available in Gen6. On Gen7 it is used for depth and stencil
surfaces only.
- Sliced, in which the surface is stored as a 2D array, with array
slice n containing all pixel data for sample n. On Gen7 this layout
is used for color surfaces.
The "Sliced" layout has an additional requirement: it must be used in
ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra
room between array slices for miplevels other than 0.
This patch modifies the surface allocation functions to use the
correct layout when allocating MSAA surfaces in Gen7, and to set the
array offsets properly when using ARYSPC_LOD0 mode. It also modifies
the code that populates SURFACE_STATE structures to ensure that
ARYSPC_LOD0 mode is selected in the appropriate circumstances.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 68216f35814ab8d292f37b8c0fa0a5f181b7f20d |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for fast depth clears.
Improves citybench high-res performance 3.0% +- 0.4%, n=10. Improves
Lightsmark 1024x768 performance 0.74% +/- 0.20% (n=78). No
significant difference on openarena (n=5, didn't fast clear) or nexuiz
(n=3).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 5b226ad603302554f38e6b12a93bd2cf443d4b56 |
|
21-May-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add an interface for doing hiz ops from C code.
This required moving gen6_hiz_op, and I put it in intel_resolve_map.h
for the next commit.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 19e9b24626c2b9d7abef054d57bb2a52106c545b |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.
MSAA support is still fairly preliminary. In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.
v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
of samples to the next higher sample count supported by the
hardware. This ensures that a query of GL_SAMPLES will return the
correct value. It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
so that we won't try to read from a nonexistent sample.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 434fc8bde41f07687ad8941ceba03c4b3e0e75bb |
|
27-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add extern "C" declarations to headers
These declarations are necessary to allow C++ code to call C code
without causing unresolved symbols (which would make the driver fail
to load).
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| fdf18b323156098ba5fb2881aa1a7888d2e0667f |
|
15-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Properly demote the depth mt format for fake packed depth/stencil.
gen7 only supports the non-packed formats, even if you associate a
real separate stencil buffer -- otherwise it's as if the depth test
always fails.
This requires a little bit of care in the match_texture_image case,
since the miptree format no longer matches the texture image format.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 0b8b6c7e974930daf12e97fb8f0b2a2cc29396d9 |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Stop creating the wrapped stencil irb.
There were only two places it was really used at this point, which was
in the batchbuffer emit of the separate stencil packets for gen6/7.
Just write in the ->stencil_mt reference in those two places and ditch
all this flailing around with allocation and refcounts.
v2: Fix separate stencil on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| f22068d5be7c829d3768154845ef3c5a2986fed4 |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move S8 width/height alignment to miptree creation.
We were doing it in the caller in the renderbuffer code, but it was
missed in the separate stencil creation for textures. Apparently our
testing was using renderbuffers or pre-aligned sizes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 5b27e44652119fd01fe93759e2c82348f4b6d707 |
|
30-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Update comment about how depth/stencil miptrees are handled.
This evolved over several commits, and I also wanted to document some
new information about how we handle formats.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 5655ebf4664b2e9a50b976612f8a1aeb26275311 |
|
30-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for LLC-cached reads of X-tiled miptrees using a blit.
This mimics the MapRenderbuffer code, and should improve the
performance of glGetTexImage().
v2: Fix broken error handling.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 221a36514b4ecffdaa3be5c43e67c75cc8c30ab8 |
|
28-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Make mapping of texture slices track the region of interest.
This will be used for things like packed depth/stencil temporaries and
making LLC-cached temporary mappings using blits.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| b75291c61c40a3a690b08f8aa013ad2d3d2deda8 |
|
28-Nov-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move the teximage mapping logic to a miptree level/slice mapping.
This will let us share teximage mapping logic with renderbuffer
mapping, which has an intel_mipmap_tree but not a gl_texture_image.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 017c13d55b5b086774d6afea2ca754482c624c6a |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Store miptree alignment units in the miptree
This allows us to replace all the calls to
intel_get_texture_alignment_unit() with a single call at miptree creation.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 2945abea338031cbe90665df60152982bfca6177 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Add resolve functions for miptrees
Add functions that
- set a miptree slice as needing a resolve
- resolve a single slice of a miptree
- resolve all slices of a miptree
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| cf5e08c8e41473467a8732fc834cec52f8b10dc8 |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Add field intel_mipmap_tree::hiz_map
This is a map of miptree slices to needed resolves.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| a2e44b0813e956440c451c107cf5564b56cbe98e |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]
This is required to correctly implement HiZ for mipmapped and
multi-layered textures.
v2: Accomodate refcount fixes in intel_process_dri2_buffer_*() that were
introduced in v2 of commit
intel: Replace intel_renderbuffer::region with a miptree [v2]
Reviewed-by: Eric Anholt <eric@anholt>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 3eb12dfaeed03f77e31943eea164acb03e86bbc9 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_texture_image::stencil_irb with intel_mipmap_tree::stencil_mt [v3]
For depthstencil textures using separate stencil, we embedded a stencil
buffer in intel_texture_image. The intention was that the embedded stencil
buffer would be the golden copy of the texture's stencil bits. When
necessary, we scattered/gathered the stencil bits between the texture
miptree and the embedded stencil buffer.
This approach had a serious deficiency for mipmapped or multi-layer
textures. Any given moment the embedded stencil buffer was consistent with
exactly one miptree slice, the most recent one to be scattered. This
permitted tests of type A to pass, but broke tests of type B.
Test A:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Read and test stencil data at (level=x1, layer=y1).
4. Upload data into (level=x2,layer=y2).
5. Read and test stencil data at (level=x2, layer=y2).
Test B:
1. Create a depthstencil texture.
2. Upload data into (level=x1,layer=y1).
3. Upload data into (level=x2,layer=y2).
4. Read and test stencil data at (level=x1, layer=y1).
5. Read and test stencil data at (level=x2, layer=y2).
v2:
Only allocate stencil miptree if intel->must_use_separate_stencil,
because we don't make the conversion from must_use_separate_stencil to
has_separate_stencil until commit
intel: Use separate stencil whenever possible
v3:
Don't call ChooseNewTexture in intel_renderbuffer_wrap_miptree() in
order to determine the renderbuffer format. Instead, pass the format as
a param to that function.
CC: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 73540690f71280a2bdda51b45203fd4ed43a1760 |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Define intel_miptree_check_level_layer()
This is a small helper function that asserts that a given level and layer
are valid for a miptree. I will be extensively using it in the future
miptree HiZ functions.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| d7b33309fe160212f2eb73f471f3aedcb5d0b5c1 |
|
15-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Kill intel_mipmap_level::nr_images [v4]
For all texture targets except GL_TEXTURE_CUBE_MAP, the 'nr_images' and
'depth' fields of intel_mipmap_level were identical. In the exceptional
case, nr_images == 6 and depth == 1.
It is simple to determine if a texture is a cube or not, so the presence
of two fields here was not helpful. Worse, it was confusing. When we
eventually implement GL_ARB_texture_cube_map_array, this mess would have
become even more confusing.
This patch removes 'nr_images' and assigns to 'depth' a consistent
meaning: depth is the number of 2D slices at each miplevel. The exact
semantics of depth varies according to the texture target:
- For GL_TEXTURE_CUBE_MAP, depth is 6.
- For GL_TEXTURE_2D_ARRAY, depth is the number of array slices. It is
identical for all miplevels in the texture.
- For GL_TEXTURE_3D, it is the texture's depth at each miplevel. Its
value, like width and height, varies with miplevel.
- For other texture types, depth is 1.
As a consequence, parameters were removed from the following function
signatures:
intel_miptree_set_level_info
Remove 'nr_images'.
i945_miptree_layout
brw_miptree_layout_texture
brw_miptree_layout_texture_array
Remove 'slices'.
v2:
- Replace "It's" with "Its".
- Remove all hunks in intel_fbo.c. The hunks were spurious and sneaked
in during a rebase.
- Remove unneeded hunk in intel_tex_map_image_for_swrast(). It was
a little refactor of the for-loop's upper bound.
v4:
In intel_miptree_get_image_offset(), document the conditions under
which different if-branches are taken.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| c2ddde70daece24d1eb7185946032158993a9e4d |
|
14-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Refactor intel_mipmap_level offsets
Add a new field, intel_mipmap_level::slice, and move the offset fields
into it. Also add some much needed documentation for these fields.
Before this patch, a separate array was allocated for the
intel_mipmap_level::{x,y}_offsets. This was just silly; it incurred an
extra call to malloc and diminished memory locality.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 005149d5860ad55c5e58e2de8a138e3a763f2036 |
|
14-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Define intel_miptree_create_for_renderbuffer()
This function creates a miptree that is suitable as storage for
a non-texture renderbuffer.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| fd99cd0e10849205749aad580fea8c970fb46a31 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add a helper function for getting miptree size from a texture image.
With 1D array textures, we no longer agree between the GL information
about width/height/depth of a texture and how we lay out a miptree.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| b07c78bfe94c17e6fccba70923b03a29c751fde1 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Consolidate texture validation copy code, and reuse it correctly.
The path for ->Data was failing to be called for the FBO draw offset
fallback, and also had mismatched compressed texture support code.
This drops the intel_prepare_render() in the blit path. We aren't
copying to/from a GL_FRONT buffer, so it doesn't matter.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 055995abc4e2f4a73122bd008a0e6f0558300d82 |
|
29-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Clean up the function chain for mapping texture images for swrast.
Too many separate functions each called from one location (in
different files). This code should all die soon when swrast starts
using MapTextureImage.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| db3ada6055814a4bd5aa95fc9505fc101864391d |
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22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the "intel" argument to intel_miptree_release().
We don't have it in the other refcounting functions, and it was
totally unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| d7cdbc3c5415d2dd5eee58834b13714a89eacf2b |
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24-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Remove pointless boolean return value from *_miptree_layout.
i915_miptree_layout, i945_miptree_layout, and brw_miptree_layout always
just return GL_TRUE, so there's really no point to it. Change them to
void functions and remove the (dead) error checking code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| 6f23d9b637602d9997896c6ca5cba0dfe36a092e |
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26-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Silence "warning: unused parameter ‘depth0’"
The depth0 parameter was not used in intel_miptree_create_for_region,
so remove it. All of the places that call this function, pass 1 for
that parameter, and the place where it looks like it should have been
used (the call to intel_miptree_create_internal) also had 1 hard
coded.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| 36a91e45f755af164232ef908419bc4cb64ba45b |
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26-Aug-2011 |
Ian Romanick <ian.d.romanick@intel.com> |
intel: Silence several "warning: unused parameter"
The intel_context and tiling parameters were not used by any if the
i9[14]5_miptree_layout or the functions they call, and the tiling parameter was
not used by brw_miptree_layout. Remove the unnecessary parameters.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| f94fef83db10f0c9327bd3dd43510ad31c94d82a |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the cpp argument to intel_miptree_create().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| 6dcc398ac0837025cf60b4d6a056fa3b0a16466f |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Calculate compress_byte in intel_miptree_create.
One less argument and thing to get wrong.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| 9c5fdbb721147f7304faaa8960f5b64e25a8f673 |
|
09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Use the gl_format to get the base_format for miptree create.
One less argument to this insanely long function call.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| 9a523a48af05118424714f0a34ca3dda6861186a |
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09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop the internal_format field of the mipmap tree.
This has been replaced with the gl_format now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| d5809115b568d8b74f47316607dce0730964517a |
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09-Jun-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add the MESA_FORMAT as a field of the miptree.
We only had internal_format before, which is way more irritating to
work with.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| c270f1a628a625ccc9f6d931f2921e3d92c31818 |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add hiz_region to intel_mipmap_tree
When a texture is attached to multiple FBO's, a separate renderbuffer
wrapper is created for each attachment. This necessitates storing the hiz
region for these renderbuffers in the texture itself instead of the
renderbuffer wrapper.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| 5b3eb7538cd9ceb967b6e9e765896183e7c2c4d4 |
|
10-Jan-2011 |
Eric Anholt <eric@anholt.net> |
Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."
This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663.
This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa.
I was wrong about which generations supported baselevel adjustment --
it's just gen4, nothing earlier. This meant that i915 would have
never used the mag filter when baselevel != 0. Not a severe bug, but
not an intentional regression. I think we can fix the performance
issue another way.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| 7ce6517f3ac41bf770ab39aba4509d4f535ef663 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Always allocate miptrees from level 0, not tObj->BaseLevel.
BaseLevel/MaxLevel are mostly used for two things: clamping texture
access for FBO rendering, and limiting the used mipmap levels when
incrementally loading textures. By restricting our mipmap trees to
just the current BaseLevel/MaxLevel, we caused reallocation thrashing
in the common case, for a theoretical win if someone really did want
just levels 2..4 or whatever of their texture object.
Bug #30366
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
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| 01b70c06284f3a0ab2de61228b73c78ed00a1a14 |
|
06-Jan-2011 |
Eric Anholt <eric@anholt.net> |
intel: Drop unused first/lastlevel args to miptree_create_for_region.
We're always making a single-level, 0-baselevel miptree.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 362c1bf75eb74de5b4655c481b74f79718ed4a34 |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Replace mt->pitch with mt->region->pitch.
The pitch is not really an inherent part of the miptree, since it's
not part of any of the layout calculations, and it's dictated by the
libdrm-allocated region pitch now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 0c51390e4b5e04b992e50fcbed751024e6c329de |
|
17-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove level_offset now that it's unused.
This is the last pitch-dependent part of miptree setup.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 8f30ceaaefc33401b08739a16ce1c5638d6432fa |
|
04-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove duplicated arguments from intel_miptree_match_image().
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 2d17dbfb5346b6d75e87c839148cbe125bf5cd6d |
|
09-Jul-2009 |
Eric Anholt <eric@anholt.net> |
intel: Keep track of x,y offsets in miptrees and use them for blitting.
By just using offsets, we confused the hardware's tiling calculations,
resulting in failures in miptree validation and blit clears.
Fixes piglit fbo-clearmipmap.
Bug #23552. (automatic mipmap generation)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 9c0ba017c8ff7caafc3ff94da3c035e687231596 |
|
23-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix depth-texture Y-tiling detection for sized internal formats.
Fixes assertion failure on norsetto shadow mapping demo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e |
|
03-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 40dd024be618d805b3744e15d25e115018641324 |
|
18-Feb-2009 |
Eric Anholt <eric@anholt.net> |
intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.
This lets us avoid allocing new buffers for renderbuffers, finalized miptrees,
and PBO-uploaded textures when there's an unreferenced but still active one
cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded
textures. The size of BOs allocated for a desktop running current GL
cairogears on i915 is cut in half with this.
Note that this means we require libdrm 2.4.5.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| e5f50f2fa32c50807da3a8f13733f0fbc7868f94 |
|
19-Mar-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Clarify miptree layout by using byte offsets to images.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 6d48779c7e5c9002d1bec4b1266ca05a474218ef |
|
15-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
Add TTM buffer object based texture from pixmap implementation.
Currently only implemented for intel hw.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 3956597962dcf6c8082541199ebac58e0d84f6bc |
|
29-Dec-2007 |
Roland Scheidegger <sroland@tungstengraphics.com> |
Bug #13839: Fix 3D texture offset miscalculation with pixels versus bytes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| a183efc132c8db1bb42525ac177ffff96f69a59b |
|
18-Dec-2007 |
Keith Packard <keithp@keithp.com> |
[Intel] Centralize mipmap pitch computations.
mipmap pitches must account for the device alignment requirements, which
used to be fairly simple; just align to a 4-byte boundary. However, to allow
textures to be drawn to under TTM, they now need to be aligned to a 64-byte
boundary. Placing all of the alignment constraints in a single function
allows this new constraint to be applied uniformly.
There was some pitch constraining code in intel_miptree_create, but that was
modifying the pitch long after the miptree had been layed out, so it only
served to wreck the mipmap and cause rendering errors.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| c0b4257aa9ba783674ccf7162799385734dff211 |
|
16-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Move to using shared texture management code.
This removes the delayed texture upload optimization from 965, in exchange for
bringing us closer to PBO support. It also disables SGIS_generate_mipmap,
which didn't seem to be working before anyway, according to the lodbias demo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|
| 77a5bcaff43df8d54e0e0ef833726e4b41d7eb36 |
|
07-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move over files that will be shared with 965-fbo work.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
|