| e2af295f94c8fb17ba51d0e6a199d5ca265f92da |
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24-Aug-2015 |
Chih-Hung Hsieh <chh@google.com> |
Rename some instructions to compile with llvm and gas.
* Rename .irep to .irp
* Rename "cmp x2, #-8" to "cmn x2, #8"
* Replace "vmov.s32" with "vmov"
* Replace "LSL #COMPONENT_SHIFT" with "LSL #(COMPONENT_SHIFT)"
* Nested .irp in *_Blur.S still cannot be compiled with llvm,
so -no-integrated-as is required.
* Verified before and after objdump binary codes are identical.
BUG: 23217766
Change-Id: I3c0d2eed44b79a39e3efcba3afadc3a14ca07874
/frameworks/rs/cpu_ref/rsCpuIntrinsics_advsimd_3DLUT.S
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| 07e4665c04a71462e6cfc1c2bb2300a9ed111e60 |
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10-Apr-2014 |
Simon Hosie <simon.hosie@arm.com> |
Handle 3DLUT odd-length cases in assembly.
Change-Id: I43802cad1a8ae74e369791a88a9644dc389519af
/frameworks/rs/cpu_ref/rsCpuIntrinsics_advsimd_3DLUT.S
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| 5dcaaa5f50926bebf6877e254c521faa7e2593e3 |
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16-Mar-2014 |
Simon Hosie <simon.hosie@arm.com> |
Optimisations to 3DLUT assembly.
Process more pixels at once to try to keep the register file fuller and more
tightly packed and allow more concurrency. Implementations in AArch32 and
AArch64 assembly.
Change-Id: I683078ff02155cc14bacce35bce3d3fe06857095
/frameworks/rs/cpu_ref/rsCpuIntrinsics_advsimd_3DLUT.S
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