| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SILowerI1Copies.cpp | 107 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); local
110 if (DstRC == &AMDGPU::VReg_1RegClass &&
137 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
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| H A D | SIFixSGPRCopies.cpp | 143 const TargetRegisterClass *DstRC = local
148 return std::make_pair(SrcRC, DstRC);
152 const TargetRegisterClass *DstRC,
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
158 const TargetRegisterClass *DstRC,
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC);
193 const TargetRegisterClass *SrcRC, *DstRC; local
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
204 MRI.setRegClass(DstReg, DstRC);
151 isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument
157 isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument
265 const TargetRegisterClass *SrcRC, *DstRC; local
357 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXCopy.cpp | 132 const TargetRegisterClass *DstRC = local
142 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
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| H A D | PPCVSXSwapRemoval.cpp | 857 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
858 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
871 if (DstRC == &PPC::VRRCRegClass) {
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; local
161 DstRC = MRI->getRegClass(VRBase);
164 DstRC = UseRC;
166 DstRC = TLI->getRegClassFor(VT);
175 VRBase = MRI->createVirtualRegister(DstRC);
333 const TargetRegisterClass *DstRC = nullptr;
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
337 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 758 const TargetRegisterClass *DstRC,
769 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
777 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
755 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const argument
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| H A D | ARMFastISel.cpp | 2043 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); local
2044 unsigned ResultReg = createResultReg(DstRC);
2063 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); local
2065 unsigned ResultReg = createResultReg(DstRC);
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| /external/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 429 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
430 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
431 if (!DstRC)
537 MRI->constrainRegClass(DstReg, DstRC);
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| H A D | RegisterCoalescer.cpp | 343 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); local
351 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
358 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
362 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
365 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
380 CrossClass = NewRC != DstRC || NewRC != SrcRC;
959 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
961 TRI->getCommonSubClass(DefRC, DstRC);
1280 auto DstRC = MRI->getRegClass(CP.getDstReg()); local
1285 std::swap(SrcRC, DstRC);
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 6270 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); local
6275 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6344 const TargetRegisterClass *DstRC = nullptr; local
6346 DstRC = getRegClass(MCID, 0, &RI, MF);
6347 VTs.push_back(*DstRC->vt_begin());
6380 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
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