1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the Emit routines for the SelectionDAG class, which creates
11// MachineInstrs based on the decisions of the SelectionDAG instruction
12// selection.
13//
14//===----------------------------------------------------------------------===//
15
16#include "InstrEmitter.h"
17#include "SDNodeDbgValue.h"
18#include "llvm/ADT/Statistic.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/StackMaps.h"
24#include "llvm/IR/DataLayout.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Target/TargetInstrInfo.h"
29#include "llvm/Target/TargetLowering.h"
30#include "llvm/Target/TargetSubtargetInfo.h"
31using namespace llvm;
32
33#define DEBUG_TYPE "instr-emitter"
34
35/// MinRCSize - Smallest register class we allow when constraining virtual
36/// registers.  If satisfying all register class constraints would require
37/// using a smaller register class, emit a COPY to a new virtual register
38/// instead.
39const unsigned MinRCSize = 4;
40
41/// CountResults - The results of target nodes have register or immediate
42/// operands first, then an optional chain, and optional glue operands (which do
43/// not go into the resulting MachineInstr).
44unsigned InstrEmitter::CountResults(SDNode *Node) {
45  unsigned N = Node->getNumValues();
46  while (N && Node->getValueType(N - 1) == MVT::Glue)
47    --N;
48  if (N && Node->getValueType(N - 1) == MVT::Other)
49    --N;    // Skip over chain result.
50  return N;
51}
52
53/// countOperands - The inputs to target nodes have any actual inputs first,
54/// followed by an optional chain operand, then an optional glue operand.
55/// Compute the number of actual operands that will go into the resulting
56/// MachineInstr.
57///
58/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59/// the chain and glue. These operands may be implicit on the machine instr.
60static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61                              unsigned &NumImpUses) {
62  unsigned N = Node->getNumOperands();
63  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
64    --N;
65  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
66    --N; // Ignore chain if it exists.
67
68  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69  NumImpUses = N - NumExpUses;
70  for (unsigned I = N; I > NumExpUses; --I) {
71    if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
72      continue;
73    if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
74      if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
75        continue;
76    NumImpUses = N - I;
77    break;
78  }
79
80  return N;
81}
82
83/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84/// implicit physical register output.
85void InstrEmitter::
86EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87                unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
88  unsigned VRBase = 0;
89  if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
90    // Just use the input register directly!
91    SDValue Op(Node, ResNo);
92    if (IsClone)
93      VRBaseMap.erase(Op);
94    bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95    (void)isNew; // Silence compiler warning.
96    assert(isNew && "Node emitted out of order - early");
97    return;
98  }
99
100  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101  // the CopyToReg'd destination register instead of creating a new vreg.
102  bool MatchReg = true;
103  const TargetRegisterClass *UseRC = nullptr;
104  MVT VT = Node->getSimpleValueType(ResNo);
105
106  // Stick to the preferred register classes for legal types.
107  if (TLI->isTypeLegal(VT))
108    UseRC = TLI->getRegClassFor(VT);
109
110  if (!IsClone && !IsCloned)
111    for (SDNode *User : Node->uses()) {
112      bool Match = true;
113      if (User->getOpcode() == ISD::CopyToReg &&
114          User->getOperand(2).getNode() == Node &&
115          User->getOperand(2).getResNo() == ResNo) {
116        unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117        if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
118          VRBase = DestReg;
119          Match = false;
120        } else if (DestReg != SrcReg)
121          Match = false;
122      } else {
123        for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124          SDValue Op = User->getOperand(i);
125          if (Op.getNode() != Node || Op.getResNo() != ResNo)
126            continue;
127          MVT VT = Node->getSimpleValueType(Op.getResNo());
128          if (VT == MVT::Other || VT == MVT::Glue)
129            continue;
130          Match = false;
131          if (User->isMachineOpcode()) {
132            const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133            const TargetRegisterClass *RC = nullptr;
134            if (i+II.getNumDefs() < II.getNumOperands()) {
135              RC = TRI->getAllocatableClass(
136                TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
137            }
138            if (!UseRC)
139              UseRC = RC;
140            else if (RC) {
141              const TargetRegisterClass *ComRC =
142                TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
143              // If multiple uses expect disjoint register classes, we emit
144              // copies in AddRegisterOperand.
145              if (ComRC)
146                UseRC = ComRC;
147            }
148          }
149        }
150      }
151      MatchReg &= Match;
152      if (VRBase)
153        break;
154    }
155
156  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
158
159  // Figure out the register class to create for the destreg.
160  if (VRBase) {
161    DstRC = MRI->getRegClass(VRBase);
162  } else if (UseRC) {
163    assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
164    DstRC = UseRC;
165  } else {
166    DstRC = TLI->getRegClassFor(VT);
167  }
168
169  // If all uses are reading from the src physical register and copying the
170  // register is either impossible or very expensive, then don't create a copy.
171  if (MatchReg && SrcRC->getCopyCost() < 0) {
172    VRBase = SrcReg;
173  } else {
174    // Create the reg, emit the copy.
175    VRBase = MRI->createVirtualRegister(DstRC);
176    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
177            VRBase).addReg(SrcReg);
178  }
179
180  SDValue Op(Node, ResNo);
181  if (IsClone)
182    VRBaseMap.erase(Op);
183  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
184  (void)isNew; // Silence compiler warning.
185  assert(isNew && "Node emitted out of order - early");
186}
187
188/// getDstOfCopyToRegUse - If the only use of the specified result number of
189/// node is a CopyToReg, return its destination register. Return 0 otherwise.
190unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
191                                                unsigned ResNo) const {
192  if (!Node->hasOneUse())
193    return 0;
194
195  SDNode *User = *Node->use_begin();
196  if (User->getOpcode() == ISD::CopyToReg &&
197      User->getOperand(2).getNode() == Node &&
198      User->getOperand(2).getResNo() == ResNo) {
199    unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
200    if (TargetRegisterInfo::isVirtualRegister(Reg))
201      return Reg;
202  }
203  return 0;
204}
205
206void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
207                                       MachineInstrBuilder &MIB,
208                                       const MCInstrDesc &II,
209                                       bool IsClone, bool IsCloned,
210                                       DenseMap<SDValue, unsigned> &VRBaseMap) {
211  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
212         "IMPLICIT_DEF should have been handled as a special case elsewhere!");
213
214  unsigned NumResults = CountResults(Node);
215  for (unsigned i = 0; i < II.getNumDefs(); ++i) {
216    // If the specific node value is only used by a CopyToReg and the dest reg
217    // is a vreg in the same register class, use the CopyToReg'd destination
218    // register instead of creating a new vreg.
219    unsigned VRBase = 0;
220    const TargetRegisterClass *RC =
221      TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
222    // Always let the value type influence the used register class. The
223    // constraints on the instruction may be too lax to represent the value
224    // type correctly. For example, a 64-bit float (X86::FR64) can't live in
225    // the 32-bit float super-class (X86::FR32).
226    if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
227      const TargetRegisterClass *VTRC =
228        TLI->getRegClassFor(Node->getSimpleValueType(i));
229      if (RC)
230        VTRC = TRI->getCommonSubClass(RC, VTRC);
231      if (VTRC)
232        RC = VTRC;
233    }
234
235    if (II.OpInfo[i].isOptionalDef()) {
236      // Optional def must be a physical register.
237      unsigned NumResults = CountResults(Node);
238      VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
239      assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
240      MIB.addReg(VRBase, RegState::Define);
241    }
242
243    if (!VRBase && !IsClone && !IsCloned)
244      for (SDNode *User : Node->uses()) {
245        if (User->getOpcode() == ISD::CopyToReg &&
246            User->getOperand(2).getNode() == Node &&
247            User->getOperand(2).getResNo() == i) {
248          unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
249          if (TargetRegisterInfo::isVirtualRegister(Reg)) {
250            const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
251            if (RegRC == RC) {
252              VRBase = Reg;
253              MIB.addReg(VRBase, RegState::Define);
254              break;
255            }
256          }
257        }
258      }
259
260    // Create the result registers for this node and add the result regs to
261    // the machine instruction.
262    if (VRBase == 0) {
263      assert(RC && "Isn't a register operand!");
264      VRBase = MRI->createVirtualRegister(RC);
265      MIB.addReg(VRBase, RegState::Define);
266    }
267
268    // If this def corresponds to a result of the SDNode insert the VRBase into
269    // the lookup map.
270    if (i < NumResults) {
271      SDValue Op(Node, i);
272      if (IsClone)
273        VRBaseMap.erase(Op);
274      bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
275      (void)isNew; // Silence compiler warning.
276      assert(isNew && "Node emitted out of order - early");
277    }
278  }
279}
280
281/// getVR - Return the virtual register corresponding to the specified result
282/// of the specified node.
283unsigned InstrEmitter::getVR(SDValue Op,
284                             DenseMap<SDValue, unsigned> &VRBaseMap) {
285  if (Op.isMachineOpcode() &&
286      Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
287    // Add an IMPLICIT_DEF instruction before every use.
288    unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
289    // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
290    // does not include operand register class info.
291    if (!VReg) {
292      const TargetRegisterClass *RC =
293        TLI->getRegClassFor(Op.getSimpleValueType());
294      VReg = MRI->createVirtualRegister(RC);
295    }
296    BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
297            TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
298    return VReg;
299  }
300
301  DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
302  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
303  return I->second;
304}
305
306
307/// AddRegisterOperand - Add the specified register as an operand to the
308/// specified machine instr. Insert register copies if the register is
309/// not in the required register class.
310void
311InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
312                                 SDValue Op,
313                                 unsigned IIOpNum,
314                                 const MCInstrDesc *II,
315                                 DenseMap<SDValue, unsigned> &VRBaseMap,
316                                 bool IsDebug, bool IsClone, bool IsCloned) {
317  assert(Op.getValueType() != MVT::Other &&
318         Op.getValueType() != MVT::Glue &&
319         "Chain and glue operands should occur at end of operand list!");
320  // Get/emit the operand.
321  unsigned VReg = getVR(Op, VRBaseMap);
322  assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
323
324  const MCInstrDesc &MCID = MIB->getDesc();
325  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
326    MCID.OpInfo[IIOpNum].isOptionalDef();
327
328  // If the instruction requires a register in a different class, create
329  // a new virtual register and copy the value into it, but first attempt to
330  // shrink VReg's register class within reason.  For example, if VReg == GR32
331  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
332  if (II) {
333    const TargetRegisterClass *DstRC = nullptr;
334    if (IIOpNum < II->getNumOperands())
335      DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
336    if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
337      unsigned NewVReg = MRI->createVirtualRegister(DstRC);
338      BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
339              TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
340      VReg = NewVReg;
341    }
342  }
343
344  // If this value has only one use, that use is a kill. This is a
345  // conservative approximation. InstrEmitter does trivial coalescing
346  // with CopyFromReg nodes, so don't emit kill flags for them.
347  // Avoid kill flags on Schedule cloned nodes, since there will be
348  // multiple uses.
349  // Tied operands are never killed, so we need to check that. And that
350  // means we need to determine the index of the operand.
351  bool isKill = Op.hasOneUse() &&
352                Op.getNode()->getOpcode() != ISD::CopyFromReg &&
353                !IsDebug &&
354                !(IsClone || IsCloned);
355  if (isKill) {
356    unsigned Idx = MIB->getNumOperands();
357    while (Idx > 0 &&
358           MIB->getOperand(Idx-1).isReg() &&
359           MIB->getOperand(Idx-1).isImplicit())
360      --Idx;
361    bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
362    if (isTied)
363      isKill = false;
364  }
365
366  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
367             getDebugRegState(IsDebug));
368}
369
370/// AddOperand - Add the specified operand to the specified machine instr.  II
371/// specifies the instruction information for the node, and IIOpNum is the
372/// operand number (in the II) that we are adding.
373void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
374                              SDValue Op,
375                              unsigned IIOpNum,
376                              const MCInstrDesc *II,
377                              DenseMap<SDValue, unsigned> &VRBaseMap,
378                              bool IsDebug, bool IsClone, bool IsCloned) {
379  if (Op.isMachineOpcode()) {
380    AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
381                       IsDebug, IsClone, IsCloned);
382  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
383    MIB.addImm(C->getSExtValue());
384  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
385    MIB.addFPImm(F->getConstantFPValue());
386  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
387    // Turn additional physreg operands into implicit uses on non-variadic
388    // instructions. This is used by call and return instructions passing
389    // arguments in registers.
390    bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
391    MIB.addReg(R->getReg(), getImplRegState(Imp));
392  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
393    MIB.addRegMask(RM->getRegMask());
394  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
395    MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
396                         TGA->getTargetFlags());
397  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
398    MIB.addMBB(BBNode->getBasicBlock());
399  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
400    MIB.addFrameIndex(FI->getIndex());
401  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
402    MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
403  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
404    int Offset = CP->getOffset();
405    unsigned Align = CP->getAlignment();
406    Type *Type = CP->getType();
407    // MachineConstantPool wants an explicit alignment.
408    if (Align == 0) {
409      Align = MF->getDataLayout().getPrefTypeAlignment(Type);
410      if (Align == 0) {
411        // Alignment of vector types.  FIXME!
412        Align = MF->getDataLayout().getTypeAllocSize(Type);
413      }
414    }
415
416    unsigned Idx;
417    MachineConstantPool *MCP = MF->getConstantPool();
418    if (CP->isMachineConstantPoolEntry())
419      Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
420    else
421      Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
422    MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
423  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
424    MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
425  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
426    MIB.addSym(SymNode->getMCSymbol());
427  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
428    MIB.addBlockAddress(BA->getBlockAddress(),
429                        BA->getOffset(),
430                        BA->getTargetFlags());
431  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
432    MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
433  } else {
434    assert(Op.getValueType() != MVT::Other &&
435           Op.getValueType() != MVT::Glue &&
436           "Chain and glue operands should occur at end of operand list!");
437    AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
438                       IsDebug, IsClone, IsCloned);
439  }
440}
441
442unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
443                                          MVT VT, DebugLoc DL) {
444  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
445  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
446
447  // RC is a sub-class of VRC that supports SubIdx.  Try to constrain VReg
448  // within reason.
449  if (RC && RC != VRC)
450    RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
451
452  // VReg has been adjusted.  It can be used with SubIdx operands now.
453  if (RC)
454    return VReg;
455
456  // VReg couldn't be reasonably constrained.  Emit a COPY to a new virtual
457  // register instead.
458  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
459  assert(RC && "No legal register class for VT supports that SubIdx");
460  unsigned NewReg = MRI->createVirtualRegister(RC);
461  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
462    .addReg(VReg);
463  return NewReg;
464}
465
466/// EmitSubregNode - Generate machine code for subreg nodes.
467///
468void InstrEmitter::EmitSubregNode(SDNode *Node,
469                                  DenseMap<SDValue, unsigned> &VRBaseMap,
470                                  bool IsClone, bool IsCloned) {
471  unsigned VRBase = 0;
472  unsigned Opc = Node->getMachineOpcode();
473
474  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
475  // the CopyToReg'd destination register instead of creating a new vreg.
476  for (SDNode *User : Node->uses()) {
477    if (User->getOpcode() == ISD::CopyToReg &&
478        User->getOperand(2).getNode() == Node) {
479      unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
480      if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
481        VRBase = DestReg;
482        break;
483      }
484    }
485  }
486
487  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
488    // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub.  There are no
489    // constraints on the %dst register, COPY can target all legal register
490    // classes.
491    unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
492    const TargetRegisterClass *TRC =
493      TLI->getRegClassFor(Node->getSimpleValueType(0));
494
495    unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
496    MachineInstr *DefMI = MRI->getVRegDef(VReg);
497    unsigned SrcReg, DstReg, DefSubIdx;
498    if (DefMI &&
499        TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
500        SubIdx == DefSubIdx &&
501        TRC == MRI->getRegClass(SrcReg)) {
502      // Optimize these:
503      // r1025 = s/zext r1024, 4
504      // r1026 = extract_subreg r1025, 4
505      // to a copy
506      // r1026 = copy r1024
507      VRBase = MRI->createVirtualRegister(TRC);
508      BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
509              TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
510      MRI->clearKillFlags(SrcReg);
511    } else {
512      // VReg may not support a SubIdx sub-register, and we may need to
513      // constrain its register class or issue a COPY to a compatible register
514      // class.
515      VReg = ConstrainForSubReg(VReg, SubIdx,
516                                Node->getOperand(0).getSimpleValueType(),
517                                Node->getDebugLoc());
518
519      // Create the destreg if it is missing.
520      if (VRBase == 0)
521        VRBase = MRI->createVirtualRegister(TRC);
522
523      // Create the extract_subreg machine instruction.
524      BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
525              TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
526    }
527  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
528             Opc == TargetOpcode::SUBREG_TO_REG) {
529    SDValue N0 = Node->getOperand(0);
530    SDValue N1 = Node->getOperand(1);
531    SDValue N2 = Node->getOperand(2);
532    unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
533
534    // Figure out the register class to create for the destreg.  It should be
535    // the largest legal register class supporting SubIdx sub-registers.
536    // RegisterCoalescer will constrain it further if it decides to eliminate
537    // the INSERT_SUBREG instruction.
538    //
539    //   %dst = INSERT_SUBREG %src, %sub, SubIdx
540    //
541    // is lowered by TwoAddressInstructionPass to:
542    //
543    //   %dst = COPY %src
544    //   %dst:SubIdx = COPY %sub
545    //
546    // There is no constraint on the %src register class.
547    //
548    const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
549    SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
550    assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
551
552    if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
553      VRBase = MRI->createVirtualRegister(SRC);
554
555    // Create the insert_subreg or subreg_to_reg machine instruction.
556    MachineInstrBuilder MIB =
557      BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
558
559    // If creating a subreg_to_reg, then the first input operand
560    // is an implicit value immediate, otherwise it's a register
561    if (Opc == TargetOpcode::SUBREG_TO_REG) {
562      const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
563      MIB.addImm(SD->getZExtValue());
564    } else
565      AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
566                 IsClone, IsCloned);
567    // Add the subregster being inserted
568    AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
569               IsClone, IsCloned);
570    MIB.addImm(SubIdx);
571    MBB->insert(InsertPos, MIB);
572  } else
573    llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
574
575  SDValue Op(Node, 0);
576  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
577  (void)isNew; // Silence compiler warning.
578  assert(isNew && "Node emitted out of order - early");
579}
580
581/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
582/// COPY_TO_REGCLASS is just a normal copy, except that the destination
583/// register is constrained to be in a particular register class.
584///
585void
586InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
587                                     DenseMap<SDValue, unsigned> &VRBaseMap) {
588  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
589
590  // Create the new VReg in the destination class and emit a copy.
591  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
592  const TargetRegisterClass *DstRC =
593    TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
594  unsigned NewVReg = MRI->createVirtualRegister(DstRC);
595  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
596    NewVReg).addReg(VReg);
597
598  SDValue Op(Node, 0);
599  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
600  (void)isNew; // Silence compiler warning.
601  assert(isNew && "Node emitted out of order - early");
602}
603
604/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
605///
606void InstrEmitter::EmitRegSequence(SDNode *Node,
607                                  DenseMap<SDValue, unsigned> &VRBaseMap,
608                                  bool IsClone, bool IsCloned) {
609  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
610  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
611  unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
612  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
613  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
614  unsigned NumOps = Node->getNumOperands();
615  assert((NumOps & 1) == 1 &&
616         "REG_SEQUENCE must have an odd number of operands!");
617  for (unsigned i = 1; i != NumOps; ++i) {
618    SDValue Op = Node->getOperand(i);
619    if ((i & 1) == 0) {
620      RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
621      // Skip physical registers as they don't have a vreg to get and we'll
622      // insert copies for them in TwoAddressInstructionPass anyway.
623      if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
624        unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
625        unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
626        const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
627        const TargetRegisterClass *SRC =
628        TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
629        if (SRC && SRC != RC) {
630          MRI->setRegClass(NewVReg, SRC);
631          RC = SRC;
632        }
633      }
634    }
635    AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
636               IsClone, IsCloned);
637  }
638
639  MBB->insert(InsertPos, MIB);
640  SDValue Op(Node, 0);
641  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
642  (void)isNew; // Silence compiler warning.
643  assert(isNew && "Node emitted out of order - early");
644}
645
646/// EmitDbgValue - Generate machine instruction for a dbg_value node.
647///
648MachineInstr *
649InstrEmitter::EmitDbgValue(SDDbgValue *SD,
650                           DenseMap<SDValue, unsigned> &VRBaseMap) {
651  uint64_t Offset = SD->getOffset();
652  MDNode *Var = SD->getVariable();
653  MDNode *Expr = SD->getExpression();
654  DebugLoc DL = SD->getDebugLoc();
655  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
656         "Expected inlined-at fields to agree");
657
658  if (SD->getKind() == SDDbgValue::FRAMEIX) {
659    // Stack address; this needs to be lowered in target-dependent fashion.
660    // EmitTargetCodeForFrameDebugValue is responsible for allocation.
661    return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
662        .addFrameIndex(SD->getFrameIx())
663        .addImm(Offset)
664        .addMetadata(Var)
665        .addMetadata(Expr);
666  }
667  // Otherwise, we're going to create an instruction here.
668  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
669  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
670  if (SD->getKind() == SDDbgValue::SDNODE) {
671    SDNode *Node = SD->getSDNode();
672    SDValue Op = SDValue(Node, SD->getResNo());
673    // It's possible we replaced this SDNode with other(s) and therefore
674    // didn't generate code for it.  It's better to catch these cases where
675    // they happen and transfer the debug info, but trying to guarantee that
676    // in all cases would be very fragile; this is a safeguard for any
677    // that were missed.
678    DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
679    if (I==VRBaseMap.end())
680      MIB.addReg(0U);       // undef
681    else
682      AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
683                 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
684  } else if (SD->getKind() == SDDbgValue::CONST) {
685    const Value *V = SD->getConst();
686    if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
687      if (CI->getBitWidth() > 64)
688        MIB.addCImm(CI);
689      else
690        MIB.addImm(CI->getSExtValue());
691    } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
692      MIB.addFPImm(CF);
693    } else {
694      // Could be an Undef.  In any case insert an Undef so we can see what we
695      // dropped.
696      MIB.addReg(0U);
697    }
698  } else {
699    // Insert an Undef so we can see what we dropped.
700    MIB.addReg(0U);
701  }
702
703  // Indirect addressing is indicated by an Imm as the second parameter.
704  if (SD->isIndirect())
705    MIB.addImm(Offset);
706  else {
707    assert(Offset == 0 && "direct value cannot have an offset");
708    MIB.addReg(0U, RegState::Debug);
709  }
710
711  MIB.addMetadata(Var);
712  MIB.addMetadata(Expr);
713
714  return &*MIB;
715}
716
717/// EmitMachineNode - Generate machine code for a target-specific node and
718/// needed dependencies.
719///
720void InstrEmitter::
721EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
722                DenseMap<SDValue, unsigned> &VRBaseMap) {
723  unsigned Opc = Node->getMachineOpcode();
724
725  // Handle subreg insert/extract specially
726  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
727      Opc == TargetOpcode::INSERT_SUBREG ||
728      Opc == TargetOpcode::SUBREG_TO_REG) {
729    EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
730    return;
731  }
732
733  // Handle COPY_TO_REGCLASS specially.
734  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
735    EmitCopyToRegClassNode(Node, VRBaseMap);
736    return;
737  }
738
739  // Handle REG_SEQUENCE specially.
740  if (Opc == TargetOpcode::REG_SEQUENCE) {
741    EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
742    return;
743  }
744
745  if (Opc == TargetOpcode::IMPLICIT_DEF)
746    // We want a unique VR for each IMPLICIT_DEF use.
747    return;
748
749  const MCInstrDesc &II = TII->get(Opc);
750  unsigned NumResults = CountResults(Node);
751  unsigned NumDefs = II.getNumDefs();
752  const MCPhysReg *ScratchRegs = nullptr;
753
754  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
755  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
756    // Stackmaps do not have arguments and do not preserve their calling
757    // convention. However, to simplify runtime support, they clobber the same
758    // scratch registers as AnyRegCC.
759    unsigned CC = CallingConv::AnyReg;
760    if (Opc == TargetOpcode::PATCHPOINT) {
761      CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
762      NumDefs = NumResults;
763    }
764    ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
765  }
766
767  unsigned NumImpUses = 0;
768  unsigned NodeOperands =
769    countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
770  bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
771#ifndef NDEBUG
772  unsigned NumMIOperands = NodeOperands + NumResults;
773  if (II.isVariadic())
774    assert(NumMIOperands >= II.getNumOperands() &&
775           "Too few operands for a variadic node!");
776  else
777    assert(NumMIOperands >= II.getNumOperands() &&
778           NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
779                            NumImpUses &&
780           "#operands for dag node doesn't match .td file!");
781#endif
782
783  // Create the new machine instruction.
784  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
785
786  // Add result register values for things that are defined by this
787  // instruction.
788  if (NumResults)
789    CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
790
791  // Emit all of the actual operands of this instruction, adding them to the
792  // instruction as appropriate.
793  bool HasOptPRefs = NumDefs > NumResults;
794  assert((!HasOptPRefs || !HasPhysRegOuts) &&
795         "Unable to cope with optional defs and phys regs defs!");
796  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
797  for (unsigned i = NumSkip; i != NodeOperands; ++i)
798    AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
799               VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
800
801  // Add scratch registers as implicit def and early clobber
802  if (ScratchRegs)
803    for (unsigned i = 0; ScratchRegs[i]; ++i)
804      MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
805                                 RegState::EarlyClobber);
806
807  // Transfer all of the memory reference descriptions of this instruction.
808  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
809                 cast<MachineSDNode>(Node)->memoperands_end());
810
811  // Insert the instruction into position in the block. This needs to
812  // happen before any custom inserter hook is called so that the
813  // hook knows where in the block to insert the replacement code.
814  MBB->insert(InsertPos, MIB);
815
816  // The MachineInstr may also define physregs instead of virtregs.  These
817  // physreg values can reach other instructions in different ways:
818  //
819  // 1. When there is a use of a Node value beyond the explicitly defined
820  //    virtual registers, we emit a CopyFromReg for one of the implicitly
821  //    defined physregs.  This only happens when HasPhysRegOuts is true.
822  //
823  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
824  //
825  // 3. A glued instruction may implicitly use a physreg.
826  //
827  // 4. A glued instruction may use a RegisterSDNode operand.
828  //
829  // Collect all the used physreg defs, and make sure that any unused physreg
830  // defs are marked as dead.
831  SmallVector<unsigned, 8> UsedRegs;
832
833  // Additional results must be physical register defs.
834  if (HasPhysRegOuts) {
835    for (unsigned i = NumDefs; i < NumResults; ++i) {
836      unsigned Reg = II.getImplicitDefs()[i - NumDefs];
837      if (!Node->hasAnyUseOfValue(i))
838        continue;
839      // This implicitly defined physreg has a use.
840      UsedRegs.push_back(Reg);
841      EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
842    }
843  }
844
845  // Scan the glue chain for any used physregs.
846  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
847    for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
848      if (F->getOpcode() == ISD::CopyFromReg) {
849        UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
850        continue;
851      } else if (F->getOpcode() == ISD::CopyToReg) {
852        // Skip CopyToReg nodes that are internal to the glue chain.
853        continue;
854      }
855      // Collect declared implicit uses.
856      const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
857      UsedRegs.append(MCID.getImplicitUses(),
858                      MCID.getImplicitUses() + MCID.getNumImplicitUses());
859      // In addition to declared implicit uses, we must also check for
860      // direct RegisterSDNode operands.
861      for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
862        if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
863          unsigned Reg = R->getReg();
864          if (TargetRegisterInfo::isPhysicalRegister(Reg))
865            UsedRegs.push_back(Reg);
866        }
867    }
868  }
869
870  // Finally mark unused registers as dead.
871  if (!UsedRegs.empty() || II.getImplicitDefs())
872    MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
873
874  // Run post-isel target hook to adjust this instruction if needed.
875  if (II.hasPostISelHook())
876    TLI->AdjustInstrPostInstrSelection(MIB, Node);
877}
878
879/// EmitSpecialNode - Generate machine code for a target-independent node and
880/// needed dependencies.
881void InstrEmitter::
882EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
883                DenseMap<SDValue, unsigned> &VRBaseMap) {
884  switch (Node->getOpcode()) {
885  default:
886#ifndef NDEBUG
887    Node->dump();
888#endif
889    llvm_unreachable("This target-independent node should have been selected!");
890  case ISD::EntryToken:
891    llvm_unreachable("EntryToken should have been excluded from the schedule!");
892  case ISD::MERGE_VALUES:
893  case ISD::TokenFactor: // fall thru
894    break;
895  case ISD::CopyToReg: {
896    unsigned SrcReg;
897    SDValue SrcVal = Node->getOperand(2);
898    if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
899      SrcReg = R->getReg();
900    else
901      SrcReg = getVR(SrcVal, VRBaseMap);
902
903    unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
904    if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
905      break;
906
907    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
908            DestReg).addReg(SrcReg);
909    break;
910  }
911  case ISD::CopyFromReg: {
912    unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
913    EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
914    break;
915  }
916  case ISD::EH_LABEL: {
917    MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
918    BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
919            TII->get(TargetOpcode::EH_LABEL)).addSym(S);
920    break;
921  }
922
923  case ISD::LIFETIME_START:
924  case ISD::LIFETIME_END: {
925    unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
926    TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
927
928    FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
929    BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
930    .addFrameIndex(FI->getIndex());
931    break;
932  }
933
934  case ISD::INLINEASM: {
935    unsigned NumOps = Node->getNumOperands();
936    if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
937      --NumOps;  // Ignore the glue operand.
938
939    // Create the inline asm machine instruction.
940    MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
941                                      TII->get(TargetOpcode::INLINEASM));
942
943    // Add the asm string as an external symbol operand.
944    SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
945    const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
946    MIB.addExternalSymbol(AsmStr);
947
948    // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
949    // bits.
950    int64_t ExtraInfo =
951      cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
952                          getZExtValue();
953    MIB.addImm(ExtraInfo);
954
955    // Remember to operand index of the group flags.
956    SmallVector<unsigned, 8> GroupIdx;
957
958    // Remember registers that are part of early-clobber defs.
959    SmallVector<unsigned, 8> ECRegs;
960
961    // Add all of the operand registers to the instruction.
962    for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
963      unsigned Flags =
964        cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
965      const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
966
967      GroupIdx.push_back(MIB->getNumOperands());
968      MIB.addImm(Flags);
969      ++i;  // Skip the ID value.
970
971      switch (InlineAsm::getKind(Flags)) {
972      default: llvm_unreachable("Bad flags!");
973        case InlineAsm::Kind_RegDef:
974        for (unsigned j = 0; j != NumVals; ++j, ++i) {
975          unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
976          // FIXME: Add dead flags for physical and virtual registers defined.
977          // For now, mark physical register defs as implicit to help fast
978          // regalloc. This makes inline asm look a lot like calls.
979          MIB.addReg(Reg, RegState::Define |
980                  getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
981        }
982        break;
983      case InlineAsm::Kind_RegDefEarlyClobber:
984      case InlineAsm::Kind_Clobber:
985        for (unsigned j = 0; j != NumVals; ++j, ++i) {
986          unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
987          MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber |
988                  getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg)));
989          ECRegs.push_back(Reg);
990        }
991        break;
992      case InlineAsm::Kind_RegUse:  // Use of register.
993      case InlineAsm::Kind_Imm:  // Immediate.
994      case InlineAsm::Kind_Mem:  // Addressing mode.
995        // The addressing mode has been selected, just add all of the
996        // operands to the machine instruction.
997        for (unsigned j = 0; j != NumVals; ++j, ++i)
998          AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
999                     /*IsDebug=*/false, IsClone, IsCloned);
1000
1001        // Manually set isTied bits.
1002        if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1003          unsigned DefGroup = 0;
1004          if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1005            unsigned DefIdx = GroupIdx[DefGroup] + 1;
1006            unsigned UseIdx = GroupIdx.back() + 1;
1007            for (unsigned j = 0; j != NumVals; ++j)
1008              MIB->tieOperands(DefIdx + j, UseIdx + j);
1009          }
1010        }
1011        break;
1012      }
1013    }
1014
1015    // GCC inline assembly allows input operands to also be early-clobber
1016    // output operands (so long as the operand is written only after it's
1017    // used), but this does not match the semantics of our early-clobber flag.
1018    // If an early-clobber operand register is also an input operand register,
1019    // then remove the early-clobber flag.
1020    for (unsigned Reg : ECRegs) {
1021      if (MIB->readsRegister(Reg, TRI)) {
1022        MachineOperand *MO = MIB->findRegisterDefOperand(Reg, false, TRI);
1023        assert(MO && "No def operand for clobbered register?");
1024        MO->setIsEarlyClobber(false);
1025      }
1026    }
1027
1028    // Get the mdnode from the asm if it exists and add it to the instruction.
1029    SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1030    const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1031    if (MD)
1032      MIB.addMetadata(MD);
1033
1034    MBB->insert(InsertPos, MIB);
1035    break;
1036  }
1037  }
1038}
1039
1040/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1041/// at the given position in the given block.
1042InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1043                           MachineBasicBlock::iterator insertpos)
1044    : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1045      TII(MF->getSubtarget().getInstrInfo()),
1046      TRI(MF->getSubtarget().getRegisterInfo()),
1047      TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1048      InsertPos(insertpos) {}
1049