/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterInfo.cpp | 36 unsigned FIOperandNum, 34 eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument
|
H A D | SIRegisterInfo.cpp | 257 int SPAdj, unsigned FIOperandNum, 267 MachineOperand &FIOp = MI->getOperand(FIOperandNum); 268 int Index = MI->getOperand(FIOperandNum).getIndex(); 383 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) { 256 eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument
|
/external/llvm/lib/Target/BPF/ |
H A D | BPFRegisterInfo.cpp | 45 int SPAdj, unsigned FIOperandNum, 44 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument
|
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 92 int SPAdj, unsigned FIOperandNum, 97 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 101 MI.getOperand(FIOperandNum + 1).getImm(); 104 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false); 105 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 91 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430RegisterInfo.cpp | 105 int SPAdj, unsigned FIOperandNum, 114 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 128 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); 154 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); 155 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 104 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument
|
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 59 int SPAdj, unsigned FIOperandNum, 71 int FrameIndex = MI->getOperand(FIOperandNum).getIndex(); 74 MI->getOperand(FIOperandNum + 1).getImm()); 78 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false); 79 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 88 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); 106 && MI->getOperand(FIOperandNum + 2).getReg() == 0) { 110 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); 111 MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg, 128 MI->getOperand(FIOperandNum) 58 eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument [all...] |
/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegisterInfo.cpp | 56 unsigned FIOperandNum, RegScavenger * /*RS*/) const { 62 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 84 MI.getOperand(FIOperandNum).ChangeToRegister(OffsetReg, /*IsDef=*/false); 54 eliminateFrameIndex( MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger * ) const argument
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsRegisterInfo.cpp | 264 unsigned FIOperandNum, RegScavenger *RS) const { 271 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 279 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); 263 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument
|
/external/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.cpp | 112 unsigned FIOperandNum, int Offset, 119 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false); 120 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 141 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false); 142 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset)); 159 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false); 160 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0); 166 int SPAdj, unsigned FIOperandNum, 172 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 181 Offset += MI.getOperand(FIOperandNum 108 replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, DebugLoc dl, unsigned FIOperandNum, int Offset, unsigned FramePtr) argument 165 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | RegisterScavenging.cpp | 423 unsigned FIOperandNum = getFrameIndexOperandNum(II); local 424 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this); 431 FIOperandNum = getFrameIndexOperandNum(II); 432 TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.cpp | 356 int SPAdj, unsigned FIOperandNum, 367 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 376 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 377 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 378 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 384 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII)) 396 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true); 355 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 262 int SPAdj, unsigned FIOperandNum, 266 MachineOperand &FrameOp = MI.getOperand(FIOperandNum); 293 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 294 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 299 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 300 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0); 261 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument
|
/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 538 int SPAdj, unsigned FIOperandNum, 543 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 566 MachineOperand &FI = MI.getOperand(FIOperandNum); 581 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); 599 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset; 600 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 604 if (MI.getOperand(FIOperandNum+3).isImm()) { 606 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm()); 610 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset); 614 (uint64_t)MI.getOperand(FIOperandNum 537 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 680 int SPAdj, unsigned FIOperandNum, 691 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 716 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 719 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 739 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 751 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 679 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 733 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 735 unsigned FIOperandNum) { 737 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 739 OffsetOperandNo = FIOperandNum - 1; 742 OffsetOperandNo = FIOperandNum + 1; 749 int SPAdj, unsigned FIOperandNum, 766 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 769 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 812 MI.getOperand(FIOperandNum).ChangeToRegister( 888 unsigned StackReg = MI.getOperand(FIOperandNum) 734 getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum) argument 748 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const argument 1002 unsigned FIOperandNum = 0; local [all...] |