1//===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetRegisterInfo class.
11// This file is responsible for the frame pointer elimination optimization
12// on X86.
13//
14//===----------------------------------------------------------------------===//
15
16#include "X86RegisterInfo.h"
17#include "X86FrameLowering.h"
18#include "X86InstrBuilder.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86Subtarget.h"
21#include "X86TargetMachine.h"
22#include "llvm/ADT/BitVector.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/MachineValueType.h"
31#include "llvm/IR/Constants.h"
32#include "llvm/IR/Function.h"
33#include "llvm/IR/Type.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Target/TargetFrameLowering.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Target/TargetOptions.h"
41
42using namespace llvm;
43
44#define GET_REGINFO_TARGET_DESC
45#include "X86GenRegisterInfo.inc"
46
47static cl::opt<bool>
48EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
49          cl::desc("Enable use of a base pointer for complex stack frames"));
50
51X86RegisterInfo::X86RegisterInfo(const Triple &TT)
52    : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
53                         X86_MC::getDwarfRegFlavour(TT, false),
54                         X86_MC::getDwarfRegFlavour(TT, true),
55                         (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
56  X86_MC::InitLLVM2SEHRegisterMapping(this);
57
58  // Cache some information.
59  Is64Bit = TT.isArch64Bit();
60  IsWin64 = Is64Bit && TT.isOSWindows();
61
62  // Use a callee-saved register as the base pointer.  These registers must
63  // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
64  // requires GOT in the EBX register before function calls via PLT GOT pointer.
65  if (Is64Bit) {
66    SlotSize = 8;
67    // This matches the simplified 32-bit pointer code in the data layout
68    // computation.
69    // FIXME: Should use the data layout?
70    bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
71    StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
72    FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
73    BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
74  } else {
75    SlotSize = 4;
76    StackPtr = X86::ESP;
77    FramePtr = X86::EBP;
78    BasePtr = X86::ESI;
79  }
80}
81
82bool
83X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
84  // ExeDepsFixer and PostRAScheduler require liveness.
85  return true;
86}
87
88int
89X86RegisterInfo::getSEHRegNum(unsigned i) const {
90  return getEncodingValue(i);
91}
92
93const TargetRegisterClass *
94X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
95                                       unsigned Idx) const {
96  // The sub_8bit sub-register index is more constrained in 32-bit mode.
97  // It behaves just like the sub_8bit_hi index.
98  if (!Is64Bit && Idx == X86::sub_8bit)
99    Idx = X86::sub_8bit_hi;
100
101  // Forward to TableGen's default version.
102  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
103}
104
105const TargetRegisterClass *
106X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
107                                          const TargetRegisterClass *B,
108                                          unsigned SubIdx) const {
109  // The sub_8bit sub-register index is more constrained in 32-bit mode.
110  if (!Is64Bit && SubIdx == X86::sub_8bit) {
111    A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
112    if (!A)
113      return nullptr;
114  }
115  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
116}
117
118const TargetRegisterClass *
119X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
120                                           const MachineFunction &MF) const {
121  // Don't allow super-classes of GR8_NOREX.  This class is only used after
122  // extracting sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
123  // to the full GR8 register class in 64-bit mode, so we cannot allow the
124  // reigster class inflation.
125  //
126  // The GR8_NOREX class is always used in a way that won't be constrained to a
127  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
128  // full GR8 class.
129  if (RC == &X86::GR8_NOREXRegClass)
130    return RC;
131
132  const TargetRegisterClass *Super = RC;
133  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
134  do {
135    switch (Super->getID()) {
136    case X86::GR8RegClassID:
137    case X86::GR16RegClassID:
138    case X86::GR32RegClassID:
139    case X86::GR64RegClassID:
140    case X86::FR32RegClassID:
141    case X86::FR64RegClassID:
142    case X86::RFP32RegClassID:
143    case X86::RFP64RegClassID:
144    case X86::RFP80RegClassID:
145    case X86::VR128RegClassID:
146    case X86::VR256RegClassID:
147      // Don't return a super-class that would shrink the spill size.
148      // That can happen with the vector and float classes.
149      if (Super->getSize() == RC->getSize())
150        return Super;
151    }
152    Super = *I++;
153  } while (Super);
154  return RC;
155}
156
157const TargetRegisterClass *
158X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
159                                    unsigned Kind) const {
160  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
161  switch (Kind) {
162  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
163  case 0: // Normal GPRs.
164    if (Subtarget.isTarget64BitLP64())
165      return &X86::GR64RegClass;
166    return &X86::GR32RegClass;
167  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
168    if (Subtarget.isTarget64BitLP64())
169      return &X86::GR64_NOSPRegClass;
170    return &X86::GR32_NOSPRegClass;
171  case 2: // NOREX GPRs.
172    if (Subtarget.isTarget64BitLP64())
173      return &X86::GR64_NOREXRegClass;
174    return &X86::GR32_NOREXRegClass;
175  case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
176    if (Subtarget.isTarget64BitLP64())
177      return &X86::GR64_NOREX_NOSPRegClass;
178    return &X86::GR32_NOREX_NOSPRegClass;
179  case 4: // Available for tailcall (not callee-saved GPRs).
180    return getGPRsForTailCall(MF);
181  }
182}
183
184const TargetRegisterClass *
185X86RegisterInfo::getGPRsForTailCall(const MachineFunction &MF) const {
186  const Function *F = MF.getFunction();
187  if (IsWin64 || (F && F->getCallingConv() == CallingConv::X86_64_Win64))
188    return &X86::GR64_TCW64RegClass;
189  else if (Is64Bit)
190    return &X86::GR64_TCRegClass;
191
192  bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
193  if (hasHipeCC)
194    return &X86::GR32RegClass;
195  return &X86::GR32_TCRegClass;
196}
197
198const TargetRegisterClass *
199X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
200  if (RC == &X86::CCRRegClass) {
201    if (Is64Bit)
202      return &X86::GR64RegClass;
203    else
204      return &X86::GR32RegClass;
205  }
206  return RC;
207}
208
209unsigned
210X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
211                                     MachineFunction &MF) const {
212  const X86FrameLowering *TFI = getFrameLowering(MF);
213
214  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
215  switch (RC->getID()) {
216  default:
217    return 0;
218  case X86::GR32RegClassID:
219    return 4 - FPDiff;
220  case X86::GR64RegClassID:
221    return 12 - FPDiff;
222  case X86::VR128RegClassID:
223    return Is64Bit ? 10 : 4;
224  case X86::VR64RegClassID:
225    return 4;
226  }
227}
228
229const MCPhysReg *
230X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
231  const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
232  bool HasSSE = Subtarget.hasSSE1();
233  bool HasAVX = Subtarget.hasAVX();
234  bool HasAVX512 = Subtarget.hasAVX512();
235  bool CallsEHReturn = MF->getMMI().callsEHReturn();
236
237  assert(MF && "MachineFunction required");
238  switch (MF->getFunction()->getCallingConv()) {
239  case CallingConv::GHC:
240  case CallingConv::HiPE:
241    return CSR_NoRegs_SaveList;
242  case CallingConv::AnyReg:
243    if (HasAVX)
244      return CSR_64_AllRegs_AVX_SaveList;
245    return CSR_64_AllRegs_SaveList;
246  case CallingConv::PreserveMost:
247    return CSR_64_RT_MostRegs_SaveList;
248  case CallingConv::PreserveAll:
249    if (HasAVX)
250      return CSR_64_RT_AllRegs_AVX_SaveList;
251    return CSR_64_RT_AllRegs_SaveList;
252  case CallingConv::CXX_FAST_TLS:
253    if (Is64Bit)
254      return CSR_64_TLS_Darwin_SaveList;
255    break;
256  case CallingConv::Intel_OCL_BI: {
257    if (HasAVX512 && IsWin64)
258      return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
259    if (HasAVX512 && Is64Bit)
260      return CSR_64_Intel_OCL_BI_AVX512_SaveList;
261    if (HasAVX && IsWin64)
262      return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
263    if (HasAVX && Is64Bit)
264      return CSR_64_Intel_OCL_BI_AVX_SaveList;
265    if (!HasAVX && !IsWin64 && Is64Bit)
266      return CSR_64_Intel_OCL_BI_SaveList;
267    break;
268  }
269  case CallingConv::HHVM:
270    return CSR_64_HHVM_SaveList;
271  case CallingConv::Cold:
272    if (Is64Bit)
273      return CSR_64_MostRegs_SaveList;
274    break;
275  case CallingConv::X86_64_Win64:
276    return CSR_Win64_SaveList;
277  case CallingConv::X86_64_SysV:
278    if (CallsEHReturn)
279      return CSR_64EHRet_SaveList;
280    return CSR_64_SaveList;
281  case CallingConv::X86_INTR:
282    if (Is64Bit) {
283      if (HasAVX)
284        return CSR_64_AllRegs_AVX_SaveList;
285      else
286        return CSR_64_AllRegs_SaveList;
287    } else {
288      if (HasSSE)
289        return CSR_32_AllRegs_SSE_SaveList;
290      else
291        return CSR_32_AllRegs_SaveList;
292    }
293  default:
294    break;
295  }
296
297  if (Is64Bit) {
298    if (IsWin64)
299      return CSR_Win64_SaveList;
300    if (CallsEHReturn)
301      return CSR_64EHRet_SaveList;
302    return CSR_64_SaveList;
303  }
304  if (CallsEHReturn)
305    return CSR_32EHRet_SaveList;
306  return CSR_32_SaveList;
307}
308
309const uint32_t *
310X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
311                                      CallingConv::ID CC) const {
312  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
313  bool HasSSE = Subtarget.hasSSE1();
314  bool HasAVX = Subtarget.hasAVX();
315  bool HasAVX512 = Subtarget.hasAVX512();
316
317  switch (CC) {
318  case CallingConv::GHC:
319  case CallingConv::HiPE:
320    return CSR_NoRegs_RegMask;
321  case CallingConv::AnyReg:
322    if (HasAVX)
323      return CSR_64_AllRegs_AVX_RegMask;
324    return CSR_64_AllRegs_RegMask;
325  case CallingConv::PreserveMost:
326    return CSR_64_RT_MostRegs_RegMask;
327  case CallingConv::PreserveAll:
328    if (HasAVX)
329      return CSR_64_RT_AllRegs_AVX_RegMask;
330    return CSR_64_RT_AllRegs_RegMask;
331  case CallingConv::CXX_FAST_TLS:
332    if (Is64Bit)
333      return CSR_64_TLS_Darwin_RegMask;
334    break;
335  case CallingConv::Intel_OCL_BI: {
336    if (HasAVX512 && IsWin64)
337      return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
338    if (HasAVX512 && Is64Bit)
339      return CSR_64_Intel_OCL_BI_AVX512_RegMask;
340    if (HasAVX && IsWin64)
341      return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
342    if (HasAVX && Is64Bit)
343      return CSR_64_Intel_OCL_BI_AVX_RegMask;
344    if (!HasAVX && !IsWin64 && Is64Bit)
345      return CSR_64_Intel_OCL_BI_RegMask;
346    break;
347  }
348  case CallingConv::HHVM:
349    return CSR_64_HHVM_RegMask;
350  case CallingConv::Cold:
351    if (Is64Bit)
352      return CSR_64_MostRegs_RegMask;
353    break;
354  case CallingConv::X86_64_Win64:
355    return CSR_Win64_RegMask;
356  case CallingConv::X86_64_SysV:
357    return CSR_64_RegMask;
358  case CallingConv::X86_INTR:
359    if (Is64Bit) {
360      if (HasAVX)
361        return CSR_64_AllRegs_AVX_RegMask;
362      else
363        return CSR_64_AllRegs_RegMask;
364    } else {
365      if (HasSSE)
366        return CSR_32_AllRegs_SSE_RegMask;
367      else
368        return CSR_32_AllRegs_RegMask;
369    }
370    default:
371      break;
372  }
373
374  // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
375  // callsEHReturn().
376  if (Is64Bit) {
377    if (IsWin64)
378      return CSR_Win64_RegMask;
379    return CSR_64_RegMask;
380  }
381  return CSR_32_RegMask;
382}
383
384const uint32_t*
385X86RegisterInfo::getNoPreservedMask() const {
386  return CSR_NoRegs_RegMask;
387}
388
389const uint32_t *X86RegisterInfo::getDarwinTLSCallPreservedMask() const {
390  return CSR_64_TLS_Darwin_RegMask;
391}
392
393BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
394  BitVector Reserved(getNumRegs());
395  const X86FrameLowering *TFI = getFrameLowering(MF);
396
397  // Set the stack-pointer register and its aliases as reserved.
398  for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
399       ++I)
400    Reserved.set(*I);
401
402  // Set the instruction pointer register and its aliases as reserved.
403  for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
404       ++I)
405    Reserved.set(*I);
406
407  // Set the frame-pointer register and its aliases as reserved if needed.
408  if (TFI->hasFP(MF)) {
409    for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
410         ++I)
411      Reserved.set(*I);
412  }
413
414  // Set the base-pointer register and its aliases as reserved if needed.
415  if (hasBasePointer(MF)) {
416    CallingConv::ID CC = MF.getFunction()->getCallingConv();
417    const uint32_t *RegMask = getCallPreservedMask(MF, CC);
418    if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
419      report_fatal_error(
420        "Stack realignment in presence of dynamic allocas is not supported with"
421        "this calling convention.");
422
423    unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), MVT::i64,
424                                              false);
425    for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
426         I.isValid(); ++I)
427      Reserved.set(*I);
428  }
429
430  // Mark the segment registers as reserved.
431  Reserved.set(X86::CS);
432  Reserved.set(X86::SS);
433  Reserved.set(X86::DS);
434  Reserved.set(X86::ES);
435  Reserved.set(X86::FS);
436  Reserved.set(X86::GS);
437
438  // Mark the floating point stack registers as reserved.
439  for (unsigned n = 0; n != 8; ++n)
440    Reserved.set(X86::ST0 + n);
441
442  // Reserve the registers that only exist in 64-bit mode.
443  if (!Is64Bit) {
444    // These 8-bit registers are part of the x86-64 extension even though their
445    // super-registers are old 32-bits.
446    Reserved.set(X86::SIL);
447    Reserved.set(X86::DIL);
448    Reserved.set(X86::BPL);
449    Reserved.set(X86::SPL);
450
451    for (unsigned n = 0; n != 8; ++n) {
452      // R8, R9, ...
453      for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
454        Reserved.set(*AI);
455
456      // XMM8, XMM9, ...
457      for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
458        Reserved.set(*AI);
459    }
460  }
461  if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
462    for (unsigned n = 16; n != 32; ++n) {
463      for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
464        Reserved.set(*AI);
465    }
466  }
467
468  return Reserved;
469}
470
471void X86RegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
472  // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
473  // because the calling convention defines the EFLAGS register as NOT
474  // preserved.
475  //
476  // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
477  // an assert to track this and clear the register afterwards to avoid
478  // unnecessary crashes during release builds.
479  assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
480         "EFLAGS are not live-out from a patchpoint.");
481
482  // Also clean other registers that don't need preserving (IP).
483  for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
484    Mask[Reg / 32] &= ~(1U << (Reg % 32));
485}
486
487//===----------------------------------------------------------------------===//
488// Stack Frame Processing methods
489//===----------------------------------------------------------------------===//
490
491static bool CantUseSP(const MachineFrameInfo *MFI) {
492  return MFI->hasVarSizedObjects() || MFI->hasOpaqueSPAdjustment();
493}
494
495bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
496   const MachineFrameInfo *MFI = MF.getFrameInfo();
497
498   if (!EnableBasePointer)
499     return false;
500
501   // When we need stack realignment, we can't address the stack from the frame
502   // pointer.  When we have dynamic allocas or stack-adjusting inline asm, we
503   // can't address variables from the stack pointer.  MS inline asm can
504   // reference locals while also adjusting the stack pointer.  When we can't
505   // use both the SP and the FP, we need a separate base pointer register.
506   bool CantUseFP = needsStackRealignment(MF);
507   return CantUseFP && CantUseSP(MFI);
508}
509
510bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
511  if (!TargetRegisterInfo::canRealignStack(MF))
512    return false;
513
514  const MachineFrameInfo *MFI = MF.getFrameInfo();
515  const MachineRegisterInfo *MRI = &MF.getRegInfo();
516
517  // Stack realignment requires a frame pointer.  If we already started
518  // register allocation with frame pointer elimination, it is too late now.
519  if (!MRI->canReserveReg(FramePtr))
520    return false;
521
522  // If a base pointer is necessary.  Check that it isn't too late to reserve
523  // it.
524  if (CantUseSP(MFI))
525    return MRI->canReserveReg(BasePtr);
526  return true;
527}
528
529bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
530                                           unsigned Reg, int &FrameIdx) const {
531  // Since X86 defines assignCalleeSavedSpillSlots which always return true
532  // this function neither used nor tested.
533  llvm_unreachable("Unused function on X86. Otherwise need a test case.");
534}
535
536void
537X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
538                                     int SPAdj, unsigned FIOperandNum,
539                                     RegScavenger *RS) const {
540  MachineInstr &MI = *II;
541  MachineFunction &MF = *MI.getParent()->getParent();
542  const X86FrameLowering *TFI = getFrameLowering(MF);
543  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
544  unsigned BasePtr;
545
546  unsigned Opc = MI.getOpcode();
547  bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
548                    Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
549
550  if (hasBasePointer(MF))
551    BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
552  else if (needsStackRealignment(MF))
553    BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
554  else if (AfterFPPop)
555    BasePtr = StackPtr;
556  else
557    BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
558
559  // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
560  // simple FP case, and doesn't work with stack realignment. On 32-bit, the
561  // offset is from the traditional base pointer location.  On 64-bit, the
562  // offset is from the SP at the end of the prologue, not the FP location. This
563  // matches the behavior of llvm.frameaddress.
564  unsigned IgnoredFrameReg;
565  if (Opc == TargetOpcode::LOCAL_ESCAPE) {
566    MachineOperand &FI = MI.getOperand(FIOperandNum);
567    int Offset;
568    Offset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
569    FI.ChangeToImmediate(Offset);
570    return;
571  }
572
573  // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
574  // register as source operand, semantic is the same and destination is
575  // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
576  if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
577    BasePtr = getX86SubSuperRegister(BasePtr, MVT::i64, false);
578
579  // This must be part of a four operand memory reference.  Replace the
580  // FrameIndex with base register with EBP.  Add an offset to the offset.
581  MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
582
583  // Now add the frame object offset to the offset from EBP.
584  int FIOffset;
585  if (AfterFPPop) {
586    // Tail call jmp happens after FP is popped.
587    const MachineFrameInfo *MFI = MF.getFrameInfo();
588    FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
589  } else
590    FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
591
592  if (BasePtr == StackPtr)
593    FIOffset += SPAdj;
594
595  // The frame index format for stackmaps and patchpoints is different from the
596  // X86 format. It only has a FI and an offset.
597  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
598    assert(BasePtr == FramePtr && "Expected the FP as base register");
599    int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
600    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
601    return;
602  }
603
604  if (MI.getOperand(FIOperandNum+3).isImm()) {
605    // Offset is a 32-bit integer.
606    int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
607    int Offset = FIOffset + Imm;
608    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
609           "Requesting 64-bit offset in 32-bit immediate!");
610    MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
611  } else {
612    // Offset is symbolic. This is extremely rare.
613    uint64_t Offset = FIOffset +
614      (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
615    MI.getOperand(FIOperandNum + 3).setOffset(Offset);
616  }
617}
618
619unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
620  const X86FrameLowering *TFI = getFrameLowering(MF);
621  return TFI->hasFP(MF) ? FramePtr : StackPtr;
622}
623
624unsigned
625X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
626  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
627  unsigned FrameReg = getFrameRegister(MF);
628  if (Subtarget.isTarget64BitILP32())
629    FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
630  return FrameReg;
631}
632
633namespace llvm {
634unsigned getX86SubSuperRegisterOrZero(unsigned Reg, MVT::SimpleValueType VT,
635                                      bool High) {
636  switch (VT) {
637  default: return 0;
638  case MVT::i8:
639    if (High) {
640      switch (Reg) {
641      default: return getX86SubSuperRegister(Reg, MVT::i64);
642      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
643        return X86::SI;
644      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
645        return X86::DI;
646      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
647        return X86::BP;
648      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
649        return X86::SP;
650      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
651        return X86::AH;
652      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
653        return X86::DH;
654      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
655        return X86::CH;
656      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
657        return X86::BH;
658      }
659    } else {
660      switch (Reg) {
661      default: return 0;
662      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
663        return X86::AL;
664      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
665        return X86::DL;
666      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
667        return X86::CL;
668      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
669        return X86::BL;
670      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
671        return X86::SIL;
672      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
673        return X86::DIL;
674      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
675        return X86::BPL;
676      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
677        return X86::SPL;
678      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
679        return X86::R8B;
680      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
681        return X86::R9B;
682      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
683        return X86::R10B;
684      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
685        return X86::R11B;
686      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
687        return X86::R12B;
688      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
689        return X86::R13B;
690      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
691        return X86::R14B;
692      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
693        return X86::R15B;
694      }
695    }
696  case MVT::i16:
697    switch (Reg) {
698    default: return 0;
699    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
700      return X86::AX;
701    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
702      return X86::DX;
703    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
704      return X86::CX;
705    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
706      return X86::BX;
707    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
708      return X86::SI;
709    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
710      return X86::DI;
711    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
712      return X86::BP;
713    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
714      return X86::SP;
715    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
716      return X86::R8W;
717    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
718      return X86::R9W;
719    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
720      return X86::R10W;
721    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
722      return X86::R11W;
723    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
724      return X86::R12W;
725    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
726      return X86::R13W;
727    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
728      return X86::R14W;
729    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
730      return X86::R15W;
731    }
732  case MVT::i32:
733    switch (Reg) {
734    default: return 0;
735    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
736      return X86::EAX;
737    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
738      return X86::EDX;
739    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
740      return X86::ECX;
741    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
742      return X86::EBX;
743    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
744      return X86::ESI;
745    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
746      return X86::EDI;
747    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
748      return X86::EBP;
749    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
750      return X86::ESP;
751    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
752      return X86::R8D;
753    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
754      return X86::R9D;
755    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
756      return X86::R10D;
757    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
758      return X86::R11D;
759    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
760      return X86::R12D;
761    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
762      return X86::R13D;
763    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
764      return X86::R14D;
765    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
766      return X86::R15D;
767    }
768  case MVT::i64:
769    switch (Reg) {
770    default: return 0;
771    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
772      return X86::RAX;
773    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
774      return X86::RDX;
775    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
776      return X86::RCX;
777    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
778      return X86::RBX;
779    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
780      return X86::RSI;
781    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
782      return X86::RDI;
783    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
784      return X86::RBP;
785    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
786      return X86::RSP;
787    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
788      return X86::R8;
789    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
790      return X86::R9;
791    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
792      return X86::R10;
793    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
794      return X86::R11;
795    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
796      return X86::R12;
797    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
798      return X86::R13;
799    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
800      return X86::R14;
801    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
802      return X86::R15;
803    }
804  }
805}
806
807unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
808                                bool High) {
809  unsigned Res = getX86SubSuperRegisterOrZero(Reg, VT, High);
810  if (Res == 0)
811    llvm_unreachable("Unexpected register or VT");
812  return Res;
813}
814
815unsigned get512BitSuperRegister(unsigned Reg) {
816  if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
817    return X86::ZMM0 + (Reg - X86::XMM0);
818  if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
819    return X86::ZMM0 + (Reg - X86::YMM0);
820  if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
821    return Reg;
822  llvm_unreachable("Unexpected SIMD register");
823}
824
825}
826