Searched defs:Src1 (Results 1 - 18 of 18) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ExpandSpecialInstrs.cpp98 unsigned Src1 = 0; local
102 Src1 = MI.getOperand(2).getReg();
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
153 .addReg(Src1)
/external/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp112 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
116 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
304 const MachineOperand *Src1 = local
306 if (Src1)
307 Inst32.addOperand(*Src1);
H A DR600ExpandSpecialInstrs.cpp225 unsigned Src1 = BMI->getOperand( local
229 (void) Src1;
231 (TRI.getEncodingValue(Src1) & 0xff) < 127)
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
276 unsigned Src1 = 0; local
282 Src1 = MI.getOperand(Src1Idx).getReg();
288 Src1 = TRI.getSubReg(Src1, SubRegIndex);
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
328 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
[all...]
H A DSIInstrInfo.cpp835 unsigned Src1 = MI->getOperand(2).getReg(); local
840 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
844 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
911 MachineOperand &Src1 = MI->getOperand(Src1Idx);
927 if (!Src1.isReg()) {
929 if (NewMI || !Src1.isImm() ||
954 if (Src1.isImm())
955 Src0.ChangeToImmediate(Src1.getImm());
959 Src1.ChangeToRegister(Reg, false);
960 Src1
1063 MachineOperand *Src1 = getNamedOperand(*UseMI, AMDGPU::OpName::src1); local
[all...]
H A DR600InstrInfo.cpp1266 MachineOperand &Src1 = MI->getOperand( local
1269 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
/external/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp159 MachineOperand &Src1 = MI->getOperand(1); local
161 if (Src1.getImm() != 0)
176 MachineOperand &Src1 = MI->getOperand(1); local
181 unsigned SrcReg = Src1.getReg();
H A DHexagonGenMux.cpp92 unsigned getMuxOpcode(const MachineOperand &Src1,
171 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, argument
173 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
262 MachineOperand *Src1 = &Def1->getOperand(2), *Src2 = &Def2->getOperand(2); local
263 unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0;
280 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2;
281 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2;
H A DHexagonISelDAGToDAG.cpp1112 SDNode* Src1 = N->getOperand(0).getNode(); local
1113 if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
1114 || Src1->getValueType(0) != MVT::i32) {
1122 Src1->getOperand(0),
1123 Src1->getOperand(1));
/external/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
55 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, argument
66 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, argument
77 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, argument
88 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, argument
99 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, argument
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1
138 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument
152 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument
166 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp215 unsigned Src1 = 0, SubReg1; local
233 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
234 if (Src1)
238 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1))
308 unsigned Src1 = 0, SubReg1; local
326 Src1 = getSrcFromCopy(&*Def, MRI, SubReg1);
329 if (Src1 && MRI->hasOneNonDBGUse(OrigSrc1)) {
330 assert(Src1 && "Can't delete copy w/o a valid original source!");
342 if (!Src1) {
344 Src1
[all...]
H A DAArch64FastISel.cpp4482 const Value *Src1 = I->getOperand(1); local
4485 std::swap(Src0, Src1);
4488 if (const auto *C = dyn_cast<ConstantInt>(Src1))
/external/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp151 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size),
154 SDValue Src1, SDValue Src2, uint64_t Size) {
156 EVT PtrVT = Src1.getValueType();
166 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
169 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
188 SDValue Src1, SDValue Src2, SDValue Size,
194 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes);
242 SDValue Src1, SDValue Src2,
245 SDVTList VTs = DAG.getVTList(Src1
153 emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument
187 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
241 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
[all...]
/external/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp369 const MachineOperand &Src1 = MI->getOperand(SrcR1 == DstR ? 1 : 3); local
373 .addOperand(Src1)
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp1050 unsigned Src1 = MI->getOperand(1).getReg(); local
1051 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1053 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2817 SDValue Src1 = Op.getOperand(0); local
2818 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2819 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1476 SDValue Src1 = N->getOperand(2); local
1492 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
/external/clang/lib/CodeGen/
H A DCGBuiltin.cpp6869 llvm::Value *Src1 = CGF.EmitScalarExpr(E->getArg(1)); local
6873 return CGF.Builder.CreateCall(F, {Src0, Src1, Src2});
6881 llvm::Value *Src1 = CGF.EmitScalarExpr(E->getArg(1)); local
6884 return CGF.Builder.CreateCall(F, {Src0, Src1});
6919 llvm::Value *Src1 = EmitScalarExpr(E->getArg(1)); local
6926 return Builder.CreateCall(F, {Src0, Src1, Src2, Src3ToBool});
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp9084 unsigned Src1 = MI->getOperand(1).getReg(); local
9099 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);

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