Searched defs:op2 (Results 1 - 8 of 8) sorted by relevance
/art/compiler/optimizing/ |
H A D | codegen_test.cc | 845 HInstruction* op2; local 848 op2 = graph->GetIntConstant(j); 852 op2 = graph->GetLongConstant(j); 861 comparison = new (&allocator) HEqual(op1, op2); 865 comparison = new (&allocator) HNotEqual(op1, op2); 869 comparison = new (&allocator) HLessThan(op1, op2); 873 comparison = new (&allocator) HLessThanOrEqual(op1, op2); 877 comparison = new (&allocator) HGreaterThan(op1, op2); 881 comparison = new (&allocator) HGreaterThanOrEqual(op1, op2); 885 comparison = new (&allocator) HBelow(op1, op2); [all...] |
H A D | intrinsics_arm.cc | 333 Register op2 = locations->InAt(1).AsRegister<Register>(); local 336 __ cmp(op1, ShifterOperand(op2)); 340 __ mov(out, ShifterOperand(op2), is_min ? Condition::GE : Condition::LE);
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H A D | intrinsics_arm64.cc | 480 Location op2 = locations->InAt(1); local 484 FPRegister op2_reg = is_double ? DRegisterFrom(op2) : SRegisterFrom(op2); 540 Location op2 = locations->InAt(1); local 544 Register op2_reg = is_long ? XRegisterFrom(op2) : WRegisterFrom(op2);
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H A D | intrinsics_x86.cc | 420 // out <=? op2 423 // if op2 is min jmp op2_label 429 // out := op2 436 XmmRegister op2 = op2_loc.AsFpuRegister<XmmRegister>(); local 440 __ ucomisd(out, op2); 442 __ ucomiss(out, op2); 453 __ orpd(out, op2); 455 __ orps(out, op2); 459 __ andpd(out, op2); 461 __ andps(out, op2); 609 Register op2 = op2_loc.AsRegister<Register>(); local [all...] |
H A D | intrinsics_x86_64.cc | 308 // out <=? op2 311 // if op2 is min jmp op2_label 317 // out := op2 324 XmmRegister op2 = op2_loc.AsFpuRegister<XmmRegister>(); local 328 __ ucomisd(out, op2); 330 __ ucomiss(out, op2); 341 __ orpd(out, op2); 343 __ orps(out, op2); 347 __ andpd(out, op2); 349 __ andps(out, op2); 437 CpuRegister op2 = op2_loc.AsRegister<CpuRegister>(); local [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_arm32.cc | 754 uint8_t op2, uint32_t a_part, 760 (op2 << 5) | 768 uint8_t op1, uint8_t op2) { 778 EmitMiscellaneous(cond, op1, op2, 0b1111, encoding); 753 EmitMiscellaneous(Condition cond, uint8_t op1, uint8_t op2, uint32_t a_part, uint32_t rest) argument 767 EmitReverseBytes(Register rd, Register rm, Condition cond, uint8_t op1, uint8_t op2) argument
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H A D | assembler_thumb2.cc | 653 uint32_t op2 = 0U /* 0b00 */; local 657 op2 << 4 | 672 uint32_t op2 = 0U /* 0b00 */; local 675 op2 << 4 | 690 uint32_t op2 = 01 /* 0b01 */; local 693 op2 << 4 | 708 uint32_t op2 = 0U /* 0b0000 */; local 711 op2 << 4 | 726 uint32_t op2 = 0U /* 0b0000 */; local 729 op2 << 743 uint32_t op2 = 15U /* 0b1111 */; local 760 uint32_t op2 = 15U /* 0b1111 */; local 2596 Emit32Miscellaneous(uint8_t op1, uint8_t op2, uint32_t rest_encoding) argument [all...] |
/art/disassembler/ |
H A D | disassembler_arm.cc | 492 // |111|op1| op2 | | | 502 uint32_t op2 = (instr >> 20) & 0x7F; local 509 if ((op2 & 0x64) == 0) { // 00x x0xx 517 // |111|01| op2 | | | 554 } else if ((op2 & 0x64) == 4) { // 00x x1xx 681 } else if ((op2 & 0x60) == 0x20) { // 01x xxxx 805 } else if ((op2 & 0x40) == 0x40) { // 1xx xxxx 1068 if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) { 1131 } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) { 1212 // |111|10| op2 | | 1336 opcode << "UNKNOWN " << op2 << " [SIMD]"; local 1588 opcode << "UNKNOWN " << op2; local [all...] |
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